.. so that trampoline and IST stacks fit without undue squeezing.
Signed-off-by: Jan Beulich <jbeulich@novell.com>
Index: 2007-07-03/xen/arch/x86/hvm/svm/svm.c
==================================================================---
2007-07-03.orig/xen/arch/x86/hvm/svm/svm.c 2007-07-02 08:13:50.000000000 +0200
+++ 2007-07-03/xen/arch/x86/hvm/svm/svm.c 2007-07-03 10:34:45.000000000 +0200
@@ -807,9 +807,9 @@ static void svm_ctxt_switch_from(struct
#ifdef __x86_64__
/* Resume use of ISTs now that the host TR is reinstated. */
- idt_tables[cpu][TRAP_double_fault].a |= 1UL << 32; /* IST1 */
- idt_tables[cpu][TRAP_nmi].a |= 2UL << 32; /* IST2 */
- idt_tables[cpu][TRAP_machine_check].a |= 3UL << 32; /* IST3 */
+ idt_tables[cpu][TRAP_double_fault].a |= IST_DF << 32;
+ idt_tables[cpu][TRAP_nmi].a |= IST_NMI << 32;
+ idt_tables[cpu][TRAP_machine_check].a |= IST_MCE << 32;
#endif
}
@@ -832,9 +832,9 @@ static void svm_ctxt_switch_to(struct vc
* Cannot use ISTs for NMI/#MC/#DF while we are running with the guest TR.
* But this doesn''t matter: the IST is only req''d to
handle SYSCALL/SYSRET.
*/
- idt_tables[cpu][TRAP_double_fault].a &= ~(3UL << 32);
- idt_tables[cpu][TRAP_nmi].a &= ~(3UL << 32);
- idt_tables[cpu][TRAP_machine_check].a &= ~(3UL << 32);
+ idt_tables[cpu][TRAP_double_fault].a &= ~(7UL << 32);
+ idt_tables[cpu][TRAP_nmi].a &= ~(7UL << 32);
+ idt_tables[cpu][TRAP_machine_check].a &= ~(7UL << 32);
#endif
svm_restore_dr(v);
Index: 2007-07-03/xen/arch/x86/setup.c
==================================================================---
2007-07-03.orig/xen/arch/x86/setup.c 2007-06-22 16:57:45.000000000 +0200
+++ 2007-07-03/xen/arch/x86/setup.c 2007-07-03 10:30:34.000000000 +0200
@@ -109,7 +109,7 @@ extern void early_cpu_init(void);
struct tss_struct init_tss[NR_CPUS];
-char __attribute__ ((__section__(".bss.page_aligned")))
cpu0_stack[STACK_SIZE];
+char __attribute__ ((__section__(".bss.stack_aligned")))
cpu0_stack[STACK_SIZE];
struct cpuinfo_x86 boot_cpu_data = { 0, 0, 0, 0, -1, 1, 0, 0, -1 };
Index: 2007-07-03/xen/arch/x86/x86_32/xen.lds.S
==================================================================---
2007-07-03.orig/xen/arch/x86/x86_32/xen.lds.S 2007-01-05 10:09:13.000000000
+0100
+++ 2007-07-03/xen/arch/x86/x86_32/xen.lds.S 2007-07-03 10:30:34.000000000 +0200
@@ -70,12 +70,14 @@ SECTIONS
.data.percpu : { *(.data.percpu) } :text
__per_cpu_data_end = .;
. = __per_cpu_start + (NR_CPUS << PERCPU_SHIFT);
- . = ALIGN(STACK_SIZE);
+ . = ALIGN(PAGE_SIZE);
__per_cpu_end = .;
__bss_start = .; /* BSS */
.bss : {
+ . = ALIGN(STACK_SIZE);
*(.bss.stack_aligned)
+ . = ALIGN(PAGE_SIZE);
*(.bss.page_aligned)
*(.bss)
} :text
Index: 2007-07-03/xen/arch/x86/x86_64/traps.c
==================================================================---
2007-07-03.orig/xen/arch/x86/x86_64/traps.c 2007-06-22 16:57:45.000000000 +0200
+++ 2007-07-03/xen/arch/x86/x86_64/traps.c 2007-07-03 10:34:30.000000000 +0200
@@ -292,11 +292,11 @@ void __init percpu_traps_init(void)
if ( cpu == 0 )
{
- /* Specify dedicated interrupt stacks for NMIs and double faults. */
+ /* Specify dedicated interrupt stacks for NMI, #DF, and #MC. */
set_intr_gate(TRAP_double_fault, &double_fault);
- idt_table[TRAP_double_fault].a |= 1UL << 32; /* IST1 */
- idt_table[TRAP_nmi].a |= 2UL << 32; /* IST2 */
- idt_table[TRAP_machine_check].a |= 3UL << 32; /* IST3 */
+ idt_table[TRAP_double_fault].a |= IST_DF << 32;
+ idt_table[TRAP_nmi].a |= IST_NMI << 32;
+ idt_table[TRAP_machine_check].a |= IST_MCE << 32;
/*
* The 32-on-64 hypercall entry vector is only accessible from ring 1.
@@ -311,17 +311,18 @@ void __init percpu_traps_init(void)
stack_bottom = (char *)get_stack_bottom();
stack = (char *)((unsigned long)stack_bottom & ~(STACK_SIZE -
1));
- /* Machine Check handler has its own per-CPU 1kB stack. */
- init_tss[cpu].ist[2] = (unsigned long)&stack[1024];
+ /* Machine Check handler has its own per-CPU 4kB stack. */
+ init_tss[cpu].ist[IST_MCE] = (unsigned long)&stack[IST_MCE *
PAGE_SIZE];
- /* Double-fault handler has its own per-CPU 1kB stack. */
- init_tss[cpu].ist[0] = (unsigned long)&stack[2048];
+ /* Double-fault handler has its own per-CPU 4kB stack. */
+ init_tss[cpu].ist[IST_DF] = (unsigned long)&stack[IST_DF * PAGE_SIZE];
- /* NMI handler has its own per-CPU 1kB stack. */
- init_tss[cpu].ist[1] = (unsigned long)&stack[3072];
+ /* NMI handler has its own per-CPU 4kB stack. */
+ init_tss[cpu].ist[IST_NMI] = (unsigned long)&stack[IST_NMI *
PAGE_SIZE];
/* Trampoline for SYSCALL entry from long mode. */
- stack = &stack[3072]; /* Skip the NMI and DF stacks. */
+ BUILD_BUG_ON((IST_MAX + 1) * PAGE_SIZE + DEBUG_STACK_SIZE > STACK_SIZE);
+ stack = &stack[IST_MAX * PAGE_SIZE]; /* Skip the IST stacks. */
wrmsr(MSR_LSTAR, (unsigned long)stack, ((unsigned long)stack>>32));
stack += write_stack_trampoline(stack, stack_bottom, FLAT_KERNEL_CS64);
Index: 2007-07-03/xen/arch/x86/x86_64/xen.lds.S
==================================================================---
2007-07-03.orig/xen/arch/x86/x86_64/xen.lds.S 2007-06-04 08:35:35.000000000
+0200
+++ 2007-07-03/xen/arch/x86/x86_64/xen.lds.S 2007-07-03 10:30:34.000000000 +0200
@@ -68,12 +68,14 @@ SECTIONS
.data.percpu : { *(.data.percpu) } :text
__per_cpu_data_end = .;
. = __per_cpu_start + (NR_CPUS << PERCPU_SHIFT);
- . = ALIGN(STACK_SIZE);
+ . = ALIGN(PAGE_SIZE);
__per_cpu_end = .;
__bss_start = .; /* BSS */
.bss : {
+ . = ALIGN(STACK_SIZE);
*(.bss.stack_aligned)
+ . = ALIGN(PAGE_SIZE);
*(.bss.page_aligned)
*(.bss)
} :text
Index: 2007-07-03/xen/include/asm-x86/config.h
==================================================================---
2007-07-03.orig/xen/include/asm-x86/config.h 2007-06-11 15:01:03.000000000 +0200
+++ 2007-07-03/xen/include/asm-x86/config.h 2007-07-03 10:30:34.000000000 +0200
@@ -77,7 +77,11 @@
#define MEMORY_GUARD
#endif
+#ifdef __i386__
#define STACK_ORDER 2
+#else
+#define STACK_ORDER 3
+#endif
#define STACK_SIZE (PAGE_SIZE << STACK_ORDER)
/* Debug stack is restricted to 8kB by guard pages. */
Index: 2007-07-03/xen/include/asm-x86/processor.h
==================================================================---
2007-07-03.orig/xen/include/asm-x86/processor.h 2007-07-02 08:13:50.000000000
+0200
+++ 2007-07-03/xen/include/asm-x86/processor.h 2007-07-03 10:30:34.000000000
+0200
@@ -448,6 +448,13 @@ struct tss_struct {
u8 __cacheline_filler[24];
} __cacheline_aligned __attribute__((packed));
+#ifdef __x86_64__
+# define IST_DF 1UL
+# define IST_NMI 2UL
+# define IST_MCE 3UL
+# define IST_MAX 3UL
+#endif
+
#define IDT_ENTRIES 256
extern idt_entry_t idt_table[];
extern idt_entry_t *idt_tables[];
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