Hi,
I'm from Intel compiler department.
I am proposing the integration of a backend targeting Nios II processor
architecture.
Nios II is a 32-bit general-purpose RISC processor core designed specifically
for the Altera family of FPGAs.
All information at about Nios II can be found at Altera website
https://www.altera.com/products/processors/support.html, including the current
ISA specification
https://www.altera.com/en_US/pdfs/literature/hb/nios2/n2cpu-nii5v1gen2.pdf
Nios II has two different binary incompatible ISA, that is called R1 and R2.
I'm going to support both of them.
Nios II code generation for both ISA already is supported by GNU compiler. GNU
compiler also supports big-endian mode of code generation that is not a high
priority for me. I'm going to have the same level of support (as GNU
compiler has )in LLVM including major number of Nios II specific options and
built-ins, but without big-endian mode at the moment. The link below illustrates
current GNU compiler specific related to Nios II.
https://gcc.gnu.org/onlinedocs/gcc/Nios-II-Options.html#Nios-II-Options
https://gcc.gnu.org/onlinedocs/gcc/Altera-Nios-II-Built-in-Functions.html#Altera-Nios-II-Built-in-Functions
LLVM is a key part of our development plan, and with community approval I would
like to act as maintainer for the backend.
The current status is that I just started the backend implementation based on
Cpu0 backend described here
http://jonathan2251.github.io/lbd/TutorialLLVMBackendCpu0.pdf as it based on
backend for MIPS 32-bit architecture that is quite similar to Nios II.
I've added Nios II register and instruction set. I was managed to compile an
assembly for "Hello World" program for Nios II target.
My development roadmap corresponds to the book for Cpu0 backend implementation.
Even I already have the workable backend I plan to review it part by part and
prepare appropriate patches for community review.
All Nios II specific names will have prefix "Nios2". For example, for
the files "Nios2CallingConv.td", for classes
"Nios2AsmPrinter".
Plan for initial implementation corresponding to patches (obviously the plan can
be changed after comments)
- Target registration
a) Nios2.td, Nios2.h, Nios2TargetMachine.h, Nios2TargetMachine.cpp,
Nios2Subtarget.h, Nios2Subtarget.cpp, TargetInfo/Nios2TargetInfo.cpp
b) MCTargetDesc/Nios2MCTargetDesc.h, MCTargetDesc/Nios2MCTargetDesc.cpp...
- Register information (Nios2RegisterInfo.cpp, Nios2RegisterInfo.h,
Nios2RegisterInfo.td)
- ISA specification (Nios2InstrFormats.td, Nios2InstrInfo.cpp, Nios2InstrInfo.h,
Nios2InstrInfo.td)
- GlobalISel (At the moment I use DAG selector, but work on porting to
GlobalISel is already started)
- Assembly printer (InstPrinter/Nios2InstPrinter.h,
InstPrinter/Nios2InstPrinter.cpp, Nios2AsmPrinter.cpp, Nios2AsmPrinter.h,
MCTargetDesc/Nios2MCAsmInfo.cpp, MCTargetDesc/Nios2MCAsmInfo.h, .)
- Target triple registration in clang
- Built-in functions (clang and codegen part)
- New options support (clang driver and codegen part)
- Direct ELF streaming (binary emission)
All comments and suggestions are very welcome,
Andrei Grischenko.
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