llvm dev - Nov 2015 - Post definition register alias in tablegen.

I have two registers A and B that are aliases of each other. I have not found a
way to define this in tablegen yet. Would anyone know how?

I've tried:
def A : Register<"%a">;
def B : Register<"%b">;
let Aliases = [A] in {
B;
}
let Aliases = [B] in {
A;
}

I've also tried forward definitions.
def A;
def B : RegisterWithAlias<"%b", A>;
def A: RegisterWithAlias<"%a", B>;


So, is there a way to specify that they are aliases of each other? Or does
setting A as an alias of B also make sure that B is an alias of A?

Thanks,
Micah
-------------- next part --------------
An HTML attachment was scrubbed...
URL:
<http://lists.llvm.org/pipermail/llvm-dev/attachments/20151124/d5d4e4d7/attachment.html>

Aliases are supposed to be symmetric.  Having something like
   def A: Register<...>;
   let Aliases = [A] in
   def B: Register<...>;
should be enough.

-Krzysztof


On 11/24/2015 10:28 AM, Micah Villmow via llvm-dev
wrote:
> I have two registers A and B that are aliases of each other. I have not
> found a way to define this in tablegen yet. Would anyone know how?
>
> I’ve tried:
>
> def A : Register<”%a”>;
>
> def B : Register<”%b”>;
>
> let Aliases = [A] in {
>
> B;
>
> }
>
> let Aliases = [B] in {
>
> A;
>
> }
>
> I’ve also tried forward definitions.
>
> def A;
>
> def B : RegisterWithAlias<”%b”, A>;
>
> def A: RegisterWithAlias<”%a”, B>;
>
> So, is there a way to specify that they are aliases of each other? Or
> does setting A as an alias of B also make sure that B is an alias of A?
>
> Thanks,
>
> Micah
>
>
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
hosted by The Linux Foundation

Thanks

-----Original Message-----
From: llvm-dev [mailto:llvm-dev-bounces at lists.llvm.org] On Behalf Of
Krzysztof Parzyszek via llvm-dev
Sent: Tuesday, November 24, 2015 10:01 AM
To: llvm-dev at lists.llvm.org
Subject: Re: [llvm-dev] Post definition register alias in tablegen.

Aliases are supposed to be symmetric.  Having something like
   def A: Register<...>;
   let Aliases = [A] in
   def B: Register<...>;
should be enough.

-Krzysztof


On 11/24/2015 10:28 AM, Micah Villmow via llvm-dev
wrote:
> I have two registers A and B that are aliases of each other. I have 
> not found a way to define this in tablegen yet. Would anyone know how?
>
> I’ve tried:
>
> def A : Register<”%a”>;
>
> def B : Register<”%b”>;
>
> let Aliases = [A] in {
>
> B;
>
> }
>
> let Aliases = [B] in {
>
> A;
>
> }
>
> I’ve also tried forward definitions.
>
> def A;
>
> def B : RegisterWithAlias<”%b”, A>;
>
> def A: RegisterWithAlias<”%a”, B>;
>
> So, is there a way to specify that they are aliases of each other? Or 
> does setting A as an alias of B also make sure that B is an alias of A?
>
> Thanks,
>
> Micah
>
>
>
> _______________________________________________
> LLVM Developers mailing list
> llvm-dev at lists.llvm.org
> http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev
>

--
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The
Linux Foundation _______________________________________________
LLVM Developers mailing list
llvm-dev at lists.llvm.org
http://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-dev