llvm dev - Mar 2014 - [LLVMdev] Named Register Implementation

On 28 March 2014 15:56, Krzysztof Parzyszek <kparzysz at codeaurora.org>
wrote:
> How are you going to represent the side-effects of such builtins?
Do you mean the possible adverse effects they can have on the program
if you write to the wrong register at the wrong time? I don't think we
should represent it at all.

That brings me to a related question: is there an attribute that makes
sure those intrinsic calls don't get moved around, or hoisted out of
loops, etc? A function or parameter attribute that means the same as
"load volatile"?

cheers,
--renato

On 3/28/2014 11:09 AM, Renato Golin wrote:
> On 28 March 2014 15:56, Krzysztof Parzyszek <kparzysz at
codeaurora.org> wrote:
>> How are you going to represent the side-effects of such builtins?
>
> Do you mean the possible adverse effects they can have on the program
> if you write to the wrong register at the wrong time? I don't think we
> should represent it at all.
I mean how do you make sure that the "write" builtin does not look
like
dead code, and at the same time it's not treated as something that 
"changes everything".  Do you expect a read of "sp" to have
a dependency
with a write of "ax"?  If not, how is that going to be communicated to
the optimizer?

-K

-- 
Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, 
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On 28 March 2014 16:12, Krzysztof Parzyszek <kparzysz at codeaurora.org>
wrote:
> I mean how do you make sure that the "write" builtin does not
look like dead
> code, and at the same time it's not treated as something that
"changes
> everything".
On the IR level, I expect a call to an intrinsic to never be pruned.
But I also need more guarantees regarding code movement, which I'm not
there is. Function calls that are not const can't be moved around, so
I expected that an intrinsic (being a function call in the IR level)
without any annotation regarding its safety would guarantee that it
doesn't happen.

That could be very optimistic, I know, thus my new thread asking for
those hard questions. ;)

>  Do you expect a read of "sp" to have a dependency with a write
> of "ax"?
No. On the IR level you don't have to worry about registers yet, and
at the DAG level, that intrinsic will be converted to a
CopyToReg/CopyFromReg, so the dependency is clearly on that register
only from there onwards.

>  If not, how is that going to be communicated to the optimizer?
The high-level IR optimisation passes should treat the intrinsics as
unassuming function calls, and the low-level pattern-matching
optimizations will already have the register in hand.

If you're not concerned about those, can you be more specific?

thanks,
--renato