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On Mar 26, 2014, at 6:56 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > On 3/26/2014 11:39 AM, İsmail Dönmez wrote: >> >> make check-all but yes make check would suffice. Thanks! > > I see two reported failures: > > > FAIL: LLVM :: BugPoint/compile-custom.ll (459 of 9992) > ******************** TEST &...

...rzysztof, The R_CASS definition is as follows: class R_CASS<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { let Namespace = "X86"; let HWEncoding = Enc; let SubRegs = subregs; } On Thu, Jul 20, 2017 at 4:14 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > I tried reproducing the problem, but the file doesn't have everything I > need (the class R_CLASS is not defined for example). > > Craig's getLane patch fixes the shifts, but if you want to use a larger > type than uint64_t, there is more work...

Hi, On Wed, Mar 26, 2014 at 6:27 PM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > On 3/26/2014 8:04 AM, İsmail Dönmez wrote: > >> >> Recent trunk has a lot of failures on PPC64/Linux. One seems to be crash >> with a backtrace like: >> > > Is this with "make check"? I can try it on my G5/FreeBSD box wh...

...XMM8 && RegNo <= X86::XMM31) || fatal error: too many errors emitted, stopping now [-ferror-limit=] 20 errors generated. When i comment out the line to construct 65536 bit register in registerinfo.td. it run fine. What to do? On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > Those couldn't be done generically, that's why the asserts were added. > > -Krzysztof > > On 7/19/2017 4:30 PM, Craig Topper wrote: > >> What about the static asserts protecting a Log call and another in the >> parser? >> &...

Ugh, that would be a “yes” then… -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Krzysztof Parzyszek via llvm-dev Sent: Friday, September 27, 2019 10:05 AM To: Dangeti Tharun kumar <cs15mtech11002 at iith.ac.in>; llvm-dev at l...

On 4/28/2016 2:11 PM, Rail Shafigulin wrote: > > On Thu, Apr 28, 2016 at 6:13 AM, Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: > > > IIRC, > > What is IIRC? If I remember correctly... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

.... it looks as if i need to replace each occurrence of unsigned with uint64_t. Should i do it for complete llvm folder or codegen only?? i am continuously getting such errors which require changing unsigned with uint64_t. What to do now??? On Thu, Jul 20, 2017 at 1:03 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > It is possible that you have more than 64 lanes. In such case you would > need to reimplement LaneBitmask with a larger underlying type. Most of the > functionality is already localized to the header file, the only exception > may be the "getAsIntege...

...h llvm-tblgen to see all expanded records). vtInt: &nbsp; (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824! ------------------&nbsp;Original&nbsp;------------------ From:&nbsp;"Krzysztof Parzyszek"<kparzysz at quicinc.com&gt;; Date:&nbsp;Fri, Nov 22, 2019 09:51 PM To:&nbsp;"Celine"<595602881 at qq.com&gt;;"llvm-dev"<llvm-dev at lists.llvm.org&gt;; Subject:&nbsp;RE: Re:RE: Re:RE: Re:RE: [llvm-dev] Tablegen PAT limitation? Thanks. Looking at th...

...reaches another def (1598) in statement (s1597), that’s why it’s needed. 2. The reason why the def of R11 in s1578 is not connected directly to the use in s1725 is that there may be an intervening def between them (that phi node of the register mask may be one such def). -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: Scott Douglas Constable <sdconsta at syr.edu> Sent: Friday, December 27, 2019 5:58 PM To: Krzysztof Parzyszek <kparzysz at quicinc.com> Cc: llvm-dev at lists.llvm.org Subject: [EXT] Re: [llvm-dev] Registe...

I don't remember the details of the particular case where we encountered this, but I think the loop started with the condition check and ended with an unconditional branch back to the beginning. -- Krzysztof Parzyszek  kparzysz at quicinc.com   LLVM compiler development -----Original Message----- From: Philip Reames <listmail at philipreames.com> Sent: Thursday, May 30, 2019 3:00 PM To: Krzysztof Parzyszek <kparzysz at quicinc.com>; Finkel, Hal J. <hfinkel at anl.gov>; Kit Barton <kit.barton at gmai...

Hi Scott, That #1073741833 is a register mask. They are treated as aggregate registers (essentially sets of registers), so if it includes R9D and R11D, it will be treated as being aliased with both. These separate defs are there because they reach disjoint registers. -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: Scott Douglas Constable <sdconsta at syr.edu> Sent: Monday, December 23, 2019 2:10 PM To: Scott Douglas Constable <sdconsta at syr.edu> Cc: Krzysztof Parzyszek <kparzysz at quicinc.com>; llvm-dev at...

Hi, Compiling on PP64/FreeBSd, I get several of these: /usr/home/kparzysz/bld.lv/tools/llvm-mc/Release+Asserts/llvm-mc.o: In function `llvm::formatted_raw_ostream::~formatted_raw_ostream()': llvm-mc.cpp:(.text.startup.main+0xe4): undefined reference to `LLVMInitializeARM64TargetInfo' llvm-mc.cpp:(.text.startup.main+0x154): undefined reference to `LLVMInitializ...

Do you know whether it has been fixed on the 8.0.1 release? Scott On Fri, Nov 8, 2019 at 9:45 AM Krzysztof Parzyszek <kparzysz at quicinc.com<mailto:kparzysz at quicinc.com>> wrote: The one blocking issue that existed in the past has been fixed. I haven’t had time to do any work on it lately, but I’m not aware of any fundamental problems that would make it not work on x86. -- Krzysztof Parzyszek kparzysz at qui...

...ter&gt; Defs = []; &nbsp; int CodeSize = 0; &nbsp; int AddedComplexity = 0; &nbsp; bit isReturn = 0; &nbsp; bit isBranch = 0; &nbsp; bit isEHScopeReturn = 0; ------------------&nbsp;Original&nbsp;------------------ From:&nbsp;"Krzysztof Parzyszek"<kparzysz at quicinc.com&gt;; Date:&nbsp;Fri, Nov 22, 2019 00:48 AM To:&nbsp;"Celine"<595602881 at qq.com&gt;;"llvm-dev"<llvm-dev at lists.llvm.org&gt;; Subject:&nbsp;RE: Re:RE: Re:RE: [llvm-dev] Tablegen PAT limitation? Could you run llvm-tblgen with...

I came across this thread from a couple years ago: http://lists.llvm.org/pipermail/llvm-dev/2017-November/119346.html Has there been any progress on RDF for X86? Or is there some other preferred alternative for performing reachability analysis after register allocation? Thanks, Scott Constable -------------- next part -------------- An HTML attachment was scrubbed... URL:

LaneMask isn't as self contained as it should be. 64 bits is enough here. The problem is accidental leaking of the current size. For example there was a hard coded compare with 32 in tablegen until I fixed it recently. On Wed, Jul 19, 2017 at 1:36 PM Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > LaneBitmask should be self-contained. If 64 bits aren't enough, there > is no point in using uint64_t, you need something wider. > > -Krzysztof > > On 7/19/2017 3:25 PM, hameeza ahmed wrote: > > You are right. Regarding lanes i can commen...

Hi, In "target-features" list in LLVM-IR, there are "+feature", "-feature". My question is, does "-feature" is equivalent to not specifying a feature at all? For example: *attributes #0 = { "target-cpu"="znver2" "target-features"="+avx -avx2" }* Wheather it is equalent to omitting the avx2 from list? *attributes #0

...e all operands are i32, for example. > > Actual mixed types are less likely to happen, but if you are doing your > own target-specific lowering, you can end up with mixed types, simply > because your code doesn't have to make them all the same. > > -- > Krzysztof Parzyszek kparzysz at quicinc.com AI tools development > > > -----Original Message----- > > From: Cameron McInally <cameron.mcinally at nyu.edu> > > Sent: Tuesday, July 7, 2020 10:10 AM > > To: Krzysztof Parzyszek <kparzysz at quicinc.com> > > Cc: llvm-dev at lists.llvm....

What about the static asserts protecting a Log call and another in the parser? On Wed, Jul 19, 2017 at 2:26 PM Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > On 7/19/2017 4:18 PM, Craig Topper wrote: > > LaneMask isn't as self contained as it should be. 64 bits is enough > > here. The problem is accidental leaking of the current size. > > > > For example there was a hard coded compare with 3...

...ue, Jul 7, 2020 at 10:58 AM Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Mixed integer types are ok, but the values will get truncated to the element type of the output value. It's pretty much what the comment says. > > -- > Krzysztof Parzyszek kparzysz at quicinc.com AI tools development > > > -----Original Message----- > > From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Cameron > > McInally via llvm-dev > > Sent: Tuesday, July 7, 2020 9:53 AM > > To: LLVM Developers Mailing List <llvm-...