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I don't remember the details of the particular case where we encountered this, but I think the loop started with the condition check and ended with an unconditional branch back to the beginning. -- Krzysztof Parzyszek  kparzysz at quicinc.com   LLVM compiler development -----Original Message----- From: Philip Reames <listmail at philipreames.com> Sent: Thursday, May 30, 2019 3:00 PM To: Krzysztof Parzyszek <kparzysz at quicinc.com>; Finkel, Hal J. <hfinkel at anl.gov>; Kit Barton <kit.bart...

Ugh, that would be a “yes” then… -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: llvm-dev <llvm-dev-bounces at lists.llvm.org> On Behalf Of Krzysztof Parzyszek via llvm-dev Sent: Friday, September 27, 2019 10:05 AM To: Dangeti Tharun kumar <cs15mtech11002 at iith.ac.in>; llv...

Mixed types aren't allowed. They are checked for in VerifySDNode in SelectionDAG.cpp and will fail an asserts build. ~Craig On Tue, Jul 7, 2020 at 8:25 AM Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > The problem can happen when you want to build a vector of i8, but i8 > itself is not legal on your target. All operands to BUILD_VECTOR will be > legalized to the next legal integer type, so you can end up with a > BUILD_VECTOR...

Thanks for the clarification. The `except` seemed dangling to me, but it's early here. Just curious... how do we end up with a mixed type BUILD_VECTOR? That's counterintuitive. On Tue, Jul 7, 2020 at 10:58 AM Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Mixed integer types are ok, but the values will get truncated to the element type of the output value. It's pretty much what the comment says. > > -- > Krzysztof Parzyszek kparzysz at quicinc.com AI tools development...

> On Jul 3, 2019, at 4:43 PM, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > -----Original Message----- > From: David Greene <dag at cray.com> > Sent: Wednesday, July 3, 2019 2:44 PM > To: Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> > Cc: Krzysztof Parzyszek <kparz...

Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> writes: > Vectorization must know the data layout: whether we have vectors (r1, > i1, r2, i2...) or (r1, r2, ...), (i1, i2, ...). These two approaches > are not compatible. If you have vector registers that can hold 8 > floats, with the...

...-print-records with llvm-tblgen to see all expanded records). vtInt: &nbsp; (vt:{ *:[Other] }) UNREACHABLE executed at /home/nancy/work/rpp_clang/llvm/utils/TableGen/CodeGenDAGPatterns.cpp:824! ------------------&nbsp;Original&nbsp;------------------ From:&nbsp;"Krzysztof Parzyszek"<kparzysz at quicinc.com&gt;; Date:&nbsp;Fri, Nov 22, 2019 09:51 PM To:&nbsp;"Celine"<595602881 at qq.com&gt;;"llvm-dev"<llvm-dev at lists.llvm.org&gt;; Subject:&nbsp;RE: Re:RE: Re:RE: Re:RE: [llvm-dev] Tablegen PAT limitation? Thank...

Hi, Is there a mechanism in place to use the new pass manager with target-specific passes added (at the moment) via addIRPasses in TargetPassConfig? I did see any code related to that, did I miss something? Is it in plan? -- Krzysztof Parzyszek kparzysz at quicinc.com AI tools development

On 22 Jan 2018, at 14:15, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > On 1/19/2018 7:21 PM, 陳韋任 wrote: >> I see X86, Mips, XCore and Hexagon define their own EH_RETURN and lower to it, but others don't. May I know why it's so on Hexagon? > > Our exception handling runtime uses __bu...

Hello Krzysztof, The R_CASS definition is as follows: class R_CASS<string n, bits<16> Enc, list<Register> subregs = []> : Register<n> { let Namespace = "X86"; let HWEncoding = Enc; let SubRegs = subregs; } On Thu, Jul 20, 2017 at 4:14 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > I tried reproducing the problem, but the file doesn't have everything I > need (the class R_CLASS is not defined for example). > > Craig's getLane patch fixes the shifts, but if you want to use a larger > type than uint64_t, there...

On Jan 19, 2013, at 7:04 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: > On 1/19/2013 8:36 PM, Chris Lattner wrote: >> >> See: >> http://llvm.org/docs/ProgrammersManual.html#picking-the-right-data-structure-for-a-task > > Were the "small n" characteristics the main motivation? It is one...

On 3/16/2016 12:36 PM, Krzysztof Parzyszek via llvm-dev wrote: > If the action is "Expand", which will convert the operation into Unfinished edit. Should be If the action is "Expand", the legalizer will replace the operation with... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum,...

On 4/28/2016 2:11 PM, Rail Shafigulin wrote: > > On Thu, Apr 28, 2016 at 6:13 AM, Krzysztof Parzyszek > <kparzysz at codeaurora.org <mailto:kparzysz at codeaurora.org>> wrote: > > > IIRC, > > What is IIRC? If I remember correctly... -Krzysztof -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> writes: > Some architectures have instructions that assist with complex > arithmetic. Without intrinsics it may be hard to use such > instructions especially because of the arithmetic simplifications. > Perhaps, depending on TTI, those i...

Doh. I missed the list in my first reply... Here's the replay of the conversation: ----- Renato: On 10 August 2015 at 14:05, Krzysztof Parzyszek via llvm-dev <llvm-dev at lists.llvm.org> wrote: > --> %SP<def,tied1> = t2LDMIA_RET %SP<tied0>, pred:8, pred:%CPSR, > %R7<def>, %PC<def>, %SP<imp-use,undef>, %R7<imp-use,undef>, > %PC<imp-use,undef> > > Here the instruction...

...nbsp; list<Register&gt; Defs = []; &nbsp; int CodeSize = 0; &nbsp; int AddedComplexity = 0; &nbsp; bit isReturn = 0; &nbsp; bit isBranch = 0; &nbsp; bit isEHScopeReturn = 0; ------------------&nbsp;Original&nbsp;------------------ From:&nbsp;"Krzysztof Parzyszek"<kparzysz at quicinc.com&gt;; Date:&nbsp;Fri, Nov 22, 2019 00:48 AM To:&nbsp;"Celine"<595602881 at qq.com&gt;;"llvm-dev"<llvm-dev at lists.llvm.org&gt;; Subject:&nbsp;RE: Re:RE: Re:RE: [llvm-dev] Tablegen PAT limitation? Could you ru...

...gNo >= X86::XMM8 && RegNo <= X86::XMM31) || fatal error: too many errors emitted, stopping now [-ferror-limit=] 20 errors generated. When i comment out the line to construct 65536 bit register in registerinfo.td. it run fine. What to do? On Thu, Jul 20, 2017 at 2:36 AM, Krzysztof Parzyszek < kparzysz at codeaurora.org> wrote: > Those couldn't be done generically, that's why the asserts were added. > > -Krzysztof > > On 7/19/2017 4:30 PM, Craig Topper wrote: > >> What about the static asserts protecting a Log call and another in the >> pars...

On 1/19/2013 10:00 PM, Chris Lattner wrote: > On Jan 19, 2013, at 7:04 PM, Krzysztof Parzyszek <kparzysz at codeaurora.org> wrote: >> >> Were the "small n" characteristics the main motivation? > > It is one of the motivations. What were the others? The reason I ask is that STL comes all ready, with containers and algorithms. They may not be optimal for e...

...ef (d3225) reaches another def (1598) in statement (s1597), that’s why it’s needed. 2. The reason why the def of R11 in s1578 is not connected directly to the use in s1725 is that there may be an intervening def between them (that phi node of the register mask may be one such def). -- Krzysztof Parzyszek kparzysz at quicinc.com<mailto:kparzysz at quicinc.com> AI tools development From: Scott Douglas Constable <sdconsta at syr.edu> Sent: Friday, December 27, 2019 5:58 PM To: Krzysztof Parzyszek <kparzysz at quicinc.com> Cc: llvm-dev at lists.llvm.org Subject: [EXT] Re: [llvm-de...

On 3/16/2016 12:53 PM, Rail Shafigulin wrote: > > On Wed, Mar 16, 2016 at 10:39 AM, Krzysztof Parzyszek via llvm-dev > <llvm-dev at lists.llvm.org <mailto:llvm-dev at lists.llvm.org>> wrote: > > On 3/16/2016 12:36 PM, Krzysztof Parzyszek via llvm-dev wrote: > > If the action is "Expand", which will convert the operation into > > > Unfinish...