llvm dev - Oct 2012 - [LLVMdev] help writing an IR targeting backend

I've got a newbie question and am looking for some pointers.  I want to
implement a backend that targets another compiler IR format.  Looking through
the backend documentation, the infrastructure is stated to be flexible enough to
do this (and refers to a hypothetical GCC IR backend).  However, all of the
documentation I've run across addresses actual ISA targets.  Is there any
documentation or examples of IR targeting backends?

In particular, I'm wondering the best way to output the IR format - do I use
the asm printer classes, JIT interface, or something else?  What are the best
practices in representing another IR through the instruction classes?  How do I
handle register allocation - disable it? Etc.

BTW, I already have an implementation that directly emits the target IR format
using a function pass, much like it looks like the C generating back end did. 
The translation is quite straight forward.  However, I'd like to be able to
leverage the existing backend passes.  In particular, the target IR is not in
SSA form, so I'd like to use the existing phi node instantiation pass in the
backend.  My impression is that I need an actual backend that represents the
target IR as machine instructions to be able to leverage the generic back end
passes.

Thanks for any help,
Jon

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On 10/30/2012 6:32 PM, Humphreys, Jonathan wrote:
>
> I’ve got a newbie question and am looking for some pointers.  I want 
> to implement a backend that targets another compiler IR format.  
> Looking through the backend documentation, the infrastructure is 
> stated to be flexible enough to do this (and refers to a hypothetical 
> GCC IR backend).  However, all of the documentation I’ve run across 
> addresses actual ISA targets.  Is there any documentation or examples 
> of IR targeting backends?
>
The closest example I can think of is the NVPTX backend, whose output 
format uses virtual registers (although it doesn't really have any 
types, IIRC).

-- 
Joshua Cranmer
News submodule owner
DXR coauthor

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