How about vector parameters?
define internal fastcc <4 x float> @add(<4 x float> %a.val, <4 x
float>
%b.val) nounwind {
entry:
%tmp4 = fadd <4 x float> %a.val, %b.val
ret <4 x float> %tmp4
}
a and b are flattened by SelectionDAGISel::LowerArguments(const BasicBlock
*LLVMBB) before letting the target handle it.
SDValue NewRoot = TLI.LowerFormalArguments(DAG.getRoot(),
F.getCallingConv(),
F.isVarArg(), Ins,
dl, DAG, InVals);
The "Ins" have all the parameters flattened to primitive types. I
would
like the vector parameters to be lowered using vector registers.
On Tue, Sep 4, 2012 at 11:35 AM, Krzysztof Parzyszek <
kparzysz at codeaurora.org> wrote:
> On 9/4/2012 11:16 AM, Khaled Mohammed wrote:
>
>>
>> Is there an option to do sret demotion via a register? if yes, do we
>> have a Target to see an example implementation?
>>
>
> Hi Khaled,
>
> Check out X86TargetLowering::**LowerReturn, and the call to
> getSRetReturnReg.
>
> The SRetReturnReg looks like a hack (each target that uses it, declares
> this variable individually), but that seems to be the current way of
> handling it.
>
> -K
>
> --
> Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted
> by The Linux Foundation
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