llvm dev - May 2012 - [LLVMdev] [TableGen] How to specify multiple types to one register class.

Hi all,

In our architecture, there is a set of general purpose registers which could be
used to store integer and floating point numbers. My problem is how to correctly
specify the type of this register class. For now, its type is
specified as i32, and
it is problematic if it is used in floating point instructions, since
tablegen cannot
correctly infer the type information of such a pattern. Here is an example:

    // Definition of the register class
    def RegCRF : RegisterClass<"Foo", [i32], 32, (sequence
"R%u", 0, 255)>;

    // Tablegen: error: In FADD: Type inference contradiction found
    //           no floating point types found
    def FADD : InstFoo<(outs RegCRF:$d),
                       (ins RegCRF:$a, RegCRF:$b),
                       "FADD\t$d, $a, $b",
                       [(set RegCRF:$d, (fadd RegCRF:$a, RegCRF:$b))]>;

I also tried to type RegCRF as [i32, f32], but then the type inference error
appears in my load/store instructions, when RegCRF is used as an address
operand. So what is the correct way to solve this problem? Thank you in
advance!

Regards,
Lei Mou

On Thu, May 24, 2012 at 10:25:36PM +0800, Lei Mou wrote:
> Hi all,
> 
> In our architecture, there is a set of general purpose registers which
could be
> used to store integer and floating point numbers. My problem is how to
correctly
> specify the type of this register class. For now, its type is
> specified as i32, and
> it is problematic if it is used in floating point instructions, since
> tablegen cannot
> correctly infer the type information of such a pattern. Here is an example:
> 
>     // Definition of the register class
>     def RegCRF : RegisterClass<"Foo", [i32], 32, (sequence
"R%u", 0, 255)>;
> 
>     // Tablegen: error: In FADD: Type inference contradiction found
>     //           no floating point types found
>     def FADD : InstFoo<(outs RegCRF:$d),
>                        (ins RegCRF:$a, RegCRF:$b),
>                        "FADD\t$d, $a, $b",
>                        [(set RegCRF:$d, (fadd RegCRF:$a, RegCRF:$b))]>;
> 
> I also tried to type RegCRF as [i32, f32], but then the type inference
error
> appears in my load/store instructions, when RegCRF is used as an address
> operand. So what is the correct way to solve this problem? Thank you in
> advance!
>
Hi,

Typing RegCRF as [i32, f32] should work.  What type inference error were
you getting when you tried this?  If a register class can hold more than
one type, sometimes you need to explicitly tell tablegen what types to
expect e.g. for your load instruction you might need this pattern:

(set (f32 RegCRF:$d), (load (i32 RegCRF:$a)))

-Tom
> Regards,
> Lei Mou
> _______________________________________________
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> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>

Hi Tom,

Thank you very much! After following your suggestion, the errors are
gone, and the instruction selector works as expected. :-)

Regards,
Lei Mou
> Hi,
>
> Typing RegCRF as [i32, f32] should work.  What type inference error were
> you getting when you tried this?  If a register class can hold more than
> one type, sometimes you need to explicitly tell tablegen what types to
> expect e.g. for your load instruction you might need this pattern:
>
> (set (f32 RegCRF:$d), (load (i32 RegCRF:$a)))
>
> -Tom
>
>> Regards,
>> Lei Mou
>> _______________________________________________
>> LLVM Developers mailing list
>> LLVMdev at cs.uiuc.edu         http://llvm.cs.uiuc.edu
>> http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
>>
>