Displaying 20 results from an estimated 10000 matches similar to: "[LLVMdev] [TableGen] How to specify multiple types to one register class."
2012 May 24
0
[LLVMdev] [TableGen] How to specify multiple types to one register class.
On Thu, May 24, 2012 at 10:25:36PM +0800, Lei Mou wrote:
> Hi all,
>
> In our architecture, there is a set of general purpose registers which could be
> used to store integer and floating point numbers. My problem is how to correctly
> specify the type of this register class. For now, its type is
> specified as i32, and
> it is problematic if it is used in floating point
2012 May 30
2
[LLVMdev] Legalizing truncating store using atomic load.
Hi,
Our target only has native support for i32 and f32 types. For data
types smaller than these, I have to custom lowering truncating store
using two atomic load instruction (which have the same semantics as
ISD::ATOMIC_LOAD_AND and ATOMIC_LOAD_OR, respectively). I run into a
problem during the legalization process, where the legalizer complains
that ISD::STORE and ISD::ATOMIC_LOAD_OR (generated
2012 May 31
1
[LLVMdev] Legalizing truncating store using atomic load.
Hi Lei,
Le 31/05/2012 03:44, Lei Mou a écrit :
> Problem solved by returning the second result of the ATOMIC_LOAD_OR node...
You got the chain instead of the loaded value.
IMHO, a better solution would have been to add a Pat<> rule to match
truncstores and expand them into target store/load/and/or.
Pat : <(truncstore16 GPR:$val, MEM:$mem),
(store MEM:$mem,
(or
2012 May 31
0
[LLVMdev] Legalizing truncating store using atomic load.
Problem solved by returning the second result of the ATOMIC_LOAD_OR node...
On Wed, May 30, 2012 at 9:38 PM, Lei Mou <lei.mou.uu at gmail.com> wrote:
> Hi,
>
> Our target only has native support for i32 and f32 types. For data
> types smaller than these, I have to custom lowering truncating store
> using two atomic load instruction (which have the same semantics as
>
2012 Apr 16
2
[LLVMdev] Question about PTXFrameLowering
Hi all,
I'm learning the PTX backend and confused by the following problem. In the
constructor of PTXFrameLowering, StackAlignment and LocalAreaOffset are
assigned 2 and -2, respectively. Since PTX has neither stack frame nor
stack pointer, why StackAlignment and LocalAreaOffset are needed and where
does 2 and -2 come from? Any explanation is appreciated. Thank you in
advance!
Yours
2012 Apr 16
0
[LLVMdev] Question about PTXFrameLowering
On Mon, Apr 16, 2012 at 3:48 AM, Lei Mou <lei.mou.uu at gmail.com> wrote:
> Hi all,
>
> I'm learning the PTX backend and confused by the following problem. In the
> constructor of PTXFrameLowering, StackAlignment and LocalAreaOffset are
> assigned 2 and -2, respectively. Since PTX has neither stack frame nor
> stack pointer, why StackAlignment and LocalAreaOffset are
2011 Nov 03
3
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
Hi,
I'm working on an LLVM backend for GPUs. One thing that is a little
different about some GPUs is that instructions can take registers or
32-bit floating point immediates as arguments. I was wondering if there
is a way to model this using tablegen, without having to define an
instruction for each possible combination of registers and immediates
(e.g. For ADD it would require four
2019 Apr 04
5
[RFC] Changes to llvm.experimental.vector.reduce intrinsics
Hi all,
While working on a patch to improve codegen for fadd reductions on AArch64, I stumbled upon an outstanding issue with the experimental.vector.reduce.fadd/fmul intrinsics where the accumulator argument is ignored when fast-math is set on the intrinsic call. This behaviour is described in the LangRef (https://www.llvm.org/docs/LangRef.html#id1905) and is mentioned in
2012 Apr 18
2
[LLVMdev] Conceptual difference between "Unallocatable" and "Reserved" registers.
Hi,
I'm writing to ask the differences between a "reserved" register and an
"unallocable" register. In X86 backend, for example, the stack pointer
register and instruction pointer are reserved but allocatable. In the
Doxygen document of function llvm::TargetRegisterInfo::getReservedRegs,
it says that a reserved register is one that *has particular uses and
should be
2019 Apr 05
4
[RFC] Changes to llvm.experimental.vector.reduce intrinsics
On 05/04/2019 09:37, Simon Pilgrim via llvm-dev wrote:
> On 04/04/2019 14:11, Sander De Smalen wrote:
>> Proposed change:
>>
>> ----------------------------
>>
>> In this RFC I propose changing the intrinsics for
>> llvm.experimental.vector.reduce.fadd and
>> llvm.experimental.vector.reduce.fmul (see options A and B). I also
>> propose renaming
2011 Dec 20
2
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote:
>
> On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote:
>
> > Here's my "thought experiment" (from PR11589): I have a bunch of
> > load-fadd-store chains to schedule. A store takes two cycles to
> > clear
> > its last pipeline stage. The fadd takes longer to compute its result
> > (say 5
2011 Dec 20
0
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote:
> Here's my "thought experiment" (from PR11589): I have a bunch of
> load-fadd-store chains to schedule. A store takes two cycles to clear
> its last pipeline stage. The fadd takes longer to compute its result
> (say 5 cycles), but can sustain a rate of 1 independent add per cycle.
> As the scheduling is bottom-up, it
2012 Apr 18
0
[LLVMdev] Conceptual difference between "Unallocatable" and "Reserved" registers.
On Apr 17, 2012, at 9:09 PM, Lei Mou wrote:
> I'm writing to ask the differences between a "reserved" register and an "unallocable" register. In X86 backend, for example, the stack pointer register and instruction pointer are reserved but allocatable. In the Doxygen document of function llvm::TargetRegisterInfo::getReservedRegs, it says that a reserved register is one
2015 Dec 30
2
Substitute instruction with a jump to a library code
I'm trying to find a way to emulate a floating point instruction, say a
floating point add. My understanding is that in order to do that I need to
execute
setOperationAction(ISD::FADD, (MVT::f32, Expand);
setOperationAction(ISD::FADD, (MVT::f64, Expand);
in MyTargetISelLowering.cpp, MyTargetLowering::MyTargetLowering(...).
However for some reason I'm still seeing a floating point add in
2011 Nov 03
0
[LLVMdev] Tablegen: Instructions that take immediates or registers as operands
Tom,
There is no way to do this that I know of. Maybe David Greene or someone who hacks on Tablegen a lot would know.
Micah
> -----Original Message-----
> From: llvmdev-bounces at cs.uiuc.edu [mailto:llvmdev-bounces at cs.uiuc.edu]
> On Behalf Of Tom Stellard
> Sent: Thursday, November 03, 2011 10:23 AM
> To: LLVM Developers Mailing List
> Subject: [LLVMdev] Tablegen:
2015 Jun 25
2
What are the restrictions around loading indirect constbuf values
Hello,
We recently tracked down a bug on Tesla GPUs (i.e. G80-GT218) whereby
it appears that instructions like
00000028: b5000409 08000780 add rn f32 $r2 $r2 neg c0[$a1]
00000040: b500060d 08004780 add rn f32 $r3 $r3 neg c0[$a1+0x4]
or with nvdisasm:
.headerflags @"EF_CUDA_SM12 EF_CUDA_PTX_SM(EF_CUDA_SM12)"
/*0000*/ FADD R2, R2, -c[0x0][A1+0x0]; /*
2011 Dec 20
0
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
On Tue, 2011-12-20 at 10:35 -0600, Hal Finkel wrote:
> On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote:
> >
> > On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote:
> >
> > > Here's my "thought experiment" (from PR11589): I have a bunch of
> > > load-fadd-store chains to schedule. A store takes two cycles to
> > > clear
> >
2012 Apr 17
1
[LLVMdev] some thoughts on the semantics of !fpmath
On Apr 16, 2012, at 11:50 PM, Duncan Sands <baldrick at free.fr> wrote:
> Hi Dan,
>
>> I realize that some of these thoughts apply equally to the
>> prior !fpaccuracy metadata that's been around a while, but I
>> hadn't looked at it closely until now.
>>
>> The !fpmath metadata violates the original spirit of
>> metadata, which is that
2011 Dec 20
1
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
On Dec 20, 2011, at 10:29 AM, Hal Finkel wrote:
> On Tue, 2011-12-20 at 10:35 -0600, Hal Finkel wrote:
>> On Mon, 2011-12-19 at 23:20 -0800, Andrew Trick wrote:
>>>
>>> On Dec 19, 2011, at 10:53 PM, Hal Finkel wrote:
>>>
>>>> Here's my "thought experiment" (from PR11589): I have a bunch of
>>>> load-fadd-store chains to
2011 Dec 20
3
[LLVMdev] specializing hybrid_ls_rr_sort (was: Re: Bottom-Up Scheduling?)
On Mon, 2011-12-19 at 22:14 -0800, Andrew Trick wrote:
> On Dec 19, 2011, at 3:19 PM, Hal Finkel wrote:
>
> > On Mon, 2011-12-19 at 07:41 -0800, Andrew Trick wrote:
> >> On Dec 19, 2011, at 6:51 AM, Hal Finkel <hfinkel at anl.gov> wrote:
> >>
> >>> On Tue, 2011-10-25 at 21:00 -0700, Andrew Trick wrote:
> >>> Now, to generate the best