Ok,
Scratching the surface this morning on Bug 1388. Happy to find that CCR has
already been defined in ARMRegisterInfo.td
However all uses in the instruction info tablegen files indicate that a
two-value operand can't be used where a dag node expects two operands.
// FIXME: should be able to write a pattern for ARMBrcond, but can't use
// a two-value operand where a dag node expects two operands. :(
def Bcc : ABI<0b1010, (outs), (ins br_target:$target),
IIC_Br, "b", "\t$target",
[/*(ARMbrcond bb:$target, imm:$cc, CCR:$ccr)*/]> {
bits<24> target;
let Inst{23-0} = target;
let DecoderMethod = "DecodeBranchImmInstruction";
}
// FIXME: should be able to write a pattern for ARMcmov, but can't use
// a two-value operand where a dag node expects two operands. :(
let neverHasSideEffects = 1 in {
def MOVCCr : ARMPseudoInst<(outs GPR:$Rd), (ins GPR:$false, GPR:$Rm,
pred:$p),
4, IIC_iCMOVr,
[/*(set GPR:$Rd, (ARMcmov GPR:$false, GPR:$Rm, imm:$cc, CCR:$ccr))*/]>,
RegConstraint<"$false = $Rd">;
It would appear that ISelDAGToDag and ISelLowering have "knowledge" of
the CCR, but ... I'm wondering if that's a moot point since the
instruction definitions could care less.
K, well I guess I get to learn more about the DAG data model in LLVM.
Any pointers would be much obliged...
Cheers,
Joe Abbey
Software Architect
Arxan Technologies, Inc.
1305 Cumberland Ave, Ste 215
West Lafayette, IN 47906
jabbey at arxan.com<mailto:jabbey at arxan.com>
www.arxan.com<http://www.arxan.com/>
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