llvm dev - Nov 2011 - [LLVMdev] itineraries for x86 and optimization in the target

Hello,

Is there code in place for lowering the bitcode SSA into an optimized
sequence for the itineraries? I have been curious whether or not such
descriptions exist for the x86 family or whether there are techniques to
make a clear determination of this information.

Regards,

Carter.
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On Nov 1, 2011, at 1:03 AM, Carter Cheng wrote:
> Is there code in place for lowering the bitcode SSA into an optimized
sequence for the itineraries? I have been curious whether or not such
descriptions exist for the x86 family or whether there are techniques to make a
clear determination of this information.
This thread might partially answer your question:

http://thread.gmane.org/gmane.comp.compilers.llvm.devel/43347

-Andy

Thanks Andy.

On Thu, Nov 3, 2011 at 7:19 PM, Andrew Trick <atrick at apple.com> wrote:
> On Nov 1, 2011, at 1:03 AM, Carter Cheng wrote:
> > Is there code in place for lowering the bitcode SSA into an optimized
> sequence for the itineraries? I have been curious whether or not such
> descriptions exist for the x86 family or whether there are techniques to
> make a clear determination of this information.
>
> This thread might partially answer your question:
>
> http://thread.gmane.org/gmane.comp.compilers.llvm.devel/43347
>
> -Andy
>
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