Hi Chris, Chris Lattner wrote:>> 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved registers. >> However, Linux and Darwin do not have the same set >> of non-callee saved registers. I don't know how to make the if(isDarwin) test >> in here >> > > Take a look at ARM/ARMRegisterInfo.td for an example of thisI tried to define Defs just like ARMRegisterInfo.td does with different subtargets, but i get the obvious message: Value 'Defs' of type 'list<Register>' is incompatible with initializer '[{ (the code is at the end of this mail) I'm not sure how to play with Defs and what to write in a .td file. I tried a top-level if with a Predicate: def IsMacho : Predicate<"Subtarget->isMachoABI()">; if (isMacho) let Defs = .... else Defs = ... But this fails too. Any other ideas on how to get this right? Thx, Nicolas let isCall = 1, noResults = 1, PPC970_Unit = 7, // All calls clobber the non-callee saved registers... Defs = [{ static const unsigned Defs_ELF[] = {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10, V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, LR,CTR, CR0,CR1,CR5,CR6,CR7} static const unsigned Defs_Macho[] = {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, LR,CTR, CR0,CR1,CR5,CR6,CR7} GPRClass::iterator GPRClass::allocation_order_begin(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); const PPCSubtarget &Subtarget = TM.getSubtarget<PPCSubtarget>(); if (Subtarget.isMachoABI()){ return Defs_Macho; } else { return Defs_ELF; } } GPRClass::iterator GPRClass::allocation_order_end(const MachineFunction &MF) const { const TargetMachine &TM = MF.getTarget(); const MRegisterInfo *RI = TM.getRegisterInfo(); const PPCSubtarget &Subtarget = TM.getSubtarget<PPCSubtarget>(); GPRClass::iterator I; if (Subtarget.isMachoABI()) { I = Defs_Macho + (sizeof(Defs_Macho)/sizeof(unsigned)); } else { I = Defs_ELF + (sizeof(Defs_ELF)/sizeof(unsigned)); } return I; } }] in { // Convenient aliases for call instructions def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), "bl $func", BrB, []>; // See Pat patterns below. def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), "bla $func", BrB, [(PPCcall (i32 imm:$func))]>; def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB, [(PPCbctrl)]>; }
I think the easiest thing for you to do is to define a separate CALL instruction with a different set of Defs. This instruction should only be selected when the predicate isMacho is true. Also update PPCRegisterInfo.cpp getCalleeSavedRegs() to return a different list when subtarget->isMachoABI() is true. Evan On Feb 14, 2007, at 7:19 AM, Nicolas Geoffray wrote:> Hi Chris, > > Chris Lattner wrote: >>> 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved >>> registers. >>> However, Linux and Darwin do not have the same set >>> of non-callee saved registers. I don't know how to make the if >>> (isDarwin) test >>> in here >>> >> >> Take a look at ARM/ARMRegisterInfo.td for an example of this > I tried to define Defs just like ARMRegisterInfo.td does with > different > subtargets, but i get the obvious > message: > Value 'Defs' of type 'list<Register>' is incompatible with > initializer '[{ > (the code is at the end of this mail) > > > I'm not sure how to play with Defs and what to write in a .td file. I > tried a top-level if with a Predicate: > def IsMacho : Predicate<"Subtarget->isMachoABI()">; > if (isMacho) let Defs = .... > else Defs = ... > > But this fails too. > > Any other ideas on how to get this right? > > Thx, > Nicolas > > > > let isCall = 1, noResults = 1, PPC970_Unit = 7, > // All calls clobber the non-callee saved registers... > Defs = [{ > > > static const unsigned Defs_ELF[] > {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, > F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10, > > V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, > LR,CTR, > CR0,CR1,CR5,CR6,CR7} > > static const unsigned Defs_Macho[] > {R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12, > F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13, > > V0,V1,V2,V3,V4,V5,V6,V7,V8,V9,V10,V11,V12,V13,V14,V15,V16,V17,V18,V19, > LR,CTR, > CR0,CR1,CR5,CR6,CR7} > > GPRClass::iterator > GPRClass::allocation_order_begin(const MachineFunction &MF) > const { > const TargetMachine &TM = MF.getTarget(); > const PPCSubtarget &Subtarget = TM.getSubtarget<PPCSubtarget>(); > if (Subtarget.isMachoABI()){ > return Defs_Macho; > } else { > return Defs_ELF; > } > } > > GPRClass::iterator > GPRClass::allocation_order_end(const MachineFunction &MF) const { > const TargetMachine &TM = MF.getTarget(); > const MRegisterInfo *RI = TM.getRegisterInfo(); > const PPCSubtarget &Subtarget = TM.getSubtarget<PPCSubtarget>(); > GPRClass::iterator I; > if (Subtarget.isMachoABI()) { > I = Defs_Macho + (sizeof(Defs_Macho)/sizeof(unsigned)); > } else { > I = Defs_ELF + (sizeof(Defs_ELF)/sizeof(unsigned)); > } > > return I; > } > }] > > in { > // Convenient aliases for call instructions > def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops), > "bl $func", BrB, []>; // See Pat patterns > below. > def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops), > "bla $func", BrB, [(PPCcall (i32 imm: > $func))]>; > def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), > "bctrl", BrB, > [(PPCbctrl)]>; > } > > > _______________________________________________ > LLVM Developers mailing list > LLVMdev at cs.uiuc.edu http://llvm.cs.uiuc.edu > http://lists.cs.uiuc.edu/mailman/listinfo/llvmdev
Evan Cheng wrote:> I think the easiest thing for you to do is to define a separate CALL > instruction with a different set of Defs. This instruction should > only be selected when the predicate isMacho is true. Also update > PPCRegisterInfo.cpp getCalleeSavedRegs() to return a different list > when subtarget->isMachoABI() is true. >Alright, thx Evan, that's what I did. Here are the final patches I think can be committed. I tried to separate them into independent chunks, but I'm not sure how to do this in a good way because of CVS and since everything is kind of related. CallABIELF.patch file changes PPCISelLowering.cpp file for ELF ABI call support CalleeSavedLinuxPPC.patch changes the callee saved registers for function calls Creqv.patch adds some XLForm_1 classes to PPCInstrFormats.td for the CREQV instruction support Frame.patch modifies PPCFrameInfo.h to take into account the ELF ABI for frame manipulation JITLinuxPPC.patch adds support to detect a Linux/PPC JIT and separate the ELF ABI with the MachO ABI I didn't sign any licence paper for LLVM. Let me know if I have to do something to commit to CVS. I can also give my code without any restriction if someone wants to commit. Cheers, Nicolas -------------- next part -------------- A non-text attachment was scrubbed... Name: CallABIELF.patch Type: text/x-patch Size: 13361 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070217/299a214d/attachment.bin> -------------- next part -------------- A non-text attachment was scrubbed... Name: CalleeSavedLinuxPPC.patch Type: text/x-patch Size: 9325 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070217/299a214d/attachment-0001.bin> -------------- next part -------------- A non-text attachment was scrubbed... Name: Creqv.patch Type: text/x-patch Size: 1388 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070217/299a214d/attachment-0002.bin> -------------- next part -------------- A non-text attachment was scrubbed... Name: Frame.patch Type: text/x-patch Size: 10953 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070217/299a214d/attachment-0003.bin> -------------- next part -------------- A non-text attachment was scrubbed... Name: JITLinuxPPC.patch Type: text/x-patch Size: 4390 bytes Desc: not available URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20070217/299a214d/attachment-0004.bin>