search for: creqv

Hi all, I'm currently implementing a linux/ppc target in llvm. The abis between Darwin/ppc and linux/ppc are different and I'm running into problems with vararg calls. Before a variadic method is called, an extra instruction must be executed (which is creqv 6, 6, 6). This instruction is not necessary in Darwin/ppc. I looked into the PowerPC target implementation and the code generation uses Dags (lib/Target/PowerPC/PPCISelLowering.cpp, LowerCALL). I need some help on how to insert the creqv instruction in the calling sequence. After this is impleme...

...wrote: > I'm currently implementing a linux/ppc target in llvm. The abis between cool > Darwin/ppc and linux/ppc are different and I'm running into problems > with vararg calls. ok > Before a variadic method is called, an extra instruction must be > executed (which is creqv 6, 6, 6). This instruction is not necessary in > Darwin/ppc. > I looked into the PowerPC target implementation and the code generation uses > Dags (lib/Target/PowerPC/PPCISelLowering.cpp, LowerCALL). right. > I need some help on how to insert the creqv instruction in the calling &gt...

...them into independent chunks, but I'm not sure how to do this in a good way because of CVS and since everything is kind of related. CallABIELF.patch file changes PPCISelLowering.cpp file for ELF ABI call support CalleeSavedLinuxPPC.patch changes the callee saved registers for function calls Creqv.patch adds some XLForm_1 classes to PPCInstrFormats.td for the CREQV instruction support Frame.patch modifies PPCFrameInfo.h to take into account the ELF ABI for frame manipulation JITLinuxPPC.patch adds support to detect a Linux/PPC JIT and separate the ELF ABI with the MachO ABI I didn't...

I think the easiest thing for you to do is to define a separate CALL instruction with a different set of Defs. This instruction should only be selected when the predicate isMacho is true. Also update PPCRegisterInfo.cpp getCalleeSavedRegs() to return a different list when subtarget->isMachoABI() is true. Evan On Feb 14, 2007, at 7:19 AM, Nicolas Geoffray wrote: > Hi Chris, >

...ted the implementation of a linux/ppc backend in llvm. There were a few things to modify in lib/Target/PowerPC with a lot of "if (!isDarwin)". There are some places where I need help before saying the port is complete. I attached the diff file as a reference 1) In order to generate a creqv instruction before a vararg call, I created a new instruction in PPCInstrInfo.td: SETCR which uses the new XForm_1_ext format. It does not use the XForm_1 format because I wanted to give only one register as operand. I'm not sure if this is the correct way to do this, but it works. 2) Line 3...

Hi Chris, Chris Lattner wrote: >> 2) Line 369 of PPCInstrInfo.td, we declare the non-callee saved registers. >> However, Linux and Darwin do not have the same set >> of non-callee saved registers. I don't know how to make the if(isDarwin) test >> in here >> > > Take a look at ARM/ARMRegisterInfo.td for an example of this I tried to define Defs just

...ppc backend > in llvm. There were a few things to modify in > lib/Target/PowerPC with a lot of "if (!isDarwin)". > > There are some places where I need help before saying the port is > complete. I attached the diff file as a reference > > 1) In order to generate a creqv instruction before a vararg call, I > created a new instruction in PPCInstrInfo.td: SETCR which > uses the new XForm_1_ext format. It does not use the XForm_1 format > because I wanted to give only one register as operand. > I'm not sure if this is the correct way to do this, bu...

...s to modify in >> >> lib/Target/PowerPC with a lot of "if (!isDarwin)". >> >> >> There are some places where I need help before saying the port is >> complete. I attached the diff file as a reference >> >> >> 1) In order to generate a creqv instruction before a vararg call, I >> created a new instruction in PPCInstrInfo.td: SETCR which >> >> uses the new XForm_1_ext format. It does not use the XForm_1 format >> because I wanted to give only one register as operand. >> >> I'm not sure if this i...

...est() ... declare void @llvm.ppc.mytest(...) nounwind //===--------------------===// then : llvm-as mycase.ll -o mycase.bc        llc -march=ppc32 mycase.bc -o mycase.s I get in mycase.s :      stwx 4, 5, 3  62         la 3, .str at l(8)  63         mytest <----my test instruction.  64         creqv 0, 0, 0  65         li 30, 0 BUT when I implement them to my target, llc error: llc: /backup/AndesCC/llvm/include/llvm/Support/Casting.h:199: typename llvm::cast_retty<To, From>::ret_type llvm::cast(const Y&) [with X = llvm::ConstantSDNode, Y = llvm::SDValue]: Assertion `isa<X>(Val...

Hi Hal, Yes, you could definitely expand them later. Custom inserters are effectively just a very early expand pseudo instruction. You can even expand them very late in the MC lowering (asmprinter) if you really need to. That could get tricky, as you'll effectively be fibbing to the register allocator. ARM uses quite a lot of late expanded pseudo-instructions, for example, though generally

...instead. 3. Please split up the patch into independent chunks for easier review. This will make it much more likely that your pieces will be applied in a timely fashion :). This will also let you get pieces in before the whole thing is "done". > 1) In order to generate a creqv instruction before a vararg call, I created a > new instruction in PPCInstrInfo.td: SETCR which > uses the new XForm_1_ext format. It does not use the XForm_1 format because I > wanted to give only one register as operand. > I'm not sure if this is the correct way to do this, but...