search for: isppc64

...ppc64 on a friend's machine). > incorporated evan's formatting suggestions. ;) > > will run another round of testing (llvm-test) on my powerpc g4/800 > when i get the okay to commit. testing on this machine takes forever > :(. More nitpicks: + if (!isVarArg && !isPPC64) { + // Non-varargs Altivec parameters go after all the non-Altivec + // parameters; handle those later so we know how much padding we need. + nAltivecParamsAtEnd++; + continue; + } else { + // Varargs and 64-bit Altivec parameters are padded to 16 byte b...

Hello Dale, this is an updated version of the tail call optimization patch for powerpc. could you have a look at it? i added code to support ppc64 (untested, will try to get access to ppc64 on a friend's machine). incorporated evan's formatting suggestions. ;) will run another round of testing (llvm-test) on my powerpc g4/800 when i get the okay to commit. testing on this machine takes

...sTy? You are using 'these'. I believe: the other functions e.g CalculateTailCallArgDest should not be moved to SelectionDAGISel because they involve target knowledge (where to place the argument) and would involve moving the whole argument lowering to SelectionDAGISel. > > if (isPPC64 && Arg.getValueType() == MVT::i32) { > // FIXME: Should this use ANY_EXTEND if neither sext nor zext? > @@ -1946,7 +2285,13 @@ SDOperand > PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, > if (GPR_idx != NumGPRs) { > RegsToPass.pu...

...use nested ?: expressions without parens, and please be careful about indentation. Please verify that mainline CVS has everything you think it should. The one hunk I didn't apply was this one: @@ -1392,12 +1418,13 @@ case MVT::f32: case MVT::f64: - if (isVarArg && isPPC64) { + if (isVarArg || isPPC64) { // Float varargs need to be promoted to double. if (Arg.getValueType() == MVT::f32) Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); This changes the darwin/ppc ABI. It's not clear to me that this was intended, so I just l...

...-relative relocations. While it might be good for LLD to support R_PPC_PLTREL24, in my opinion there still is no reason for LLVM to emit this in non-PIC mode. If my understanding is correct, I can submit a patch that will replace bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64; with bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64 && DAG.getTarget().getRelocationModel() == Reloc::PIC_; Vit -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature S...

Evan Cheng wrote: > I think the easiest thing for you to do is to define a separate CALL > instruction with a different set of Defs. This instruction should > only be selected when the predicate isMacho is true. Also update > PPCRegisterInfo.cpp getCalleeSavedRegs() to return a different list > when subtarget->isMachoABI() is true. > Alright, thx Evan, that's

...t; SelectionDAGISel. I am not sure. Just thinking aloud. It would be nice if all of the common code can be handled by SelectionDAGISel. For example, it seems possible for SDIsel to determine which operands can be overwritten and issued the copies there? > > >> >> if (isPPC64 && Arg.getValueType() == MVT::i32) { >> // FIXME: Should this use ANY_EXTEND if neither sext nor zext? >> @@ -1946,7 +2285,13 @@ SDOperand >> PPCTargetLowering::LowerCALL(SDOperand Op, SelectionDAG &DAG, >> if (GPR_idx != NumGPRs) { >>...

...ine CVS has > everything you think it should. > I just verified and launched some compilations. Everything seems OK. > The one hunk I didn't apply was this one: > > @@ -1392,12 +1418,13 @@ > case MVT::f32: > case MVT::f64: > - if (isVarArg && isPPC64) { > + if (isVarArg || isPPC64) { > // Float varargs need to be promoted to double. > if (Arg.getValueType() == MVT::f32) > Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); > > This changes the darwin/ppc ABI. It's not clear to me that th...

...;> While it might be good for LLD to support R_PPC_PLTREL24, in my opinion there still is no reason for LLVM to emit this in non-PIC mode. If my understanding is correct, I can submit a patch that will replace >> >> bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64; >> >> with >> >> bool UsePlt = !Local && Subtarget.isTargetELF() && !isPPC64 && >> DAG.getTarget().getRelocationModel() == Reloc::PIC_; >> >> Vit >> >> >> >> ______________________________...

.... Everything seems OK. Ok, I just broke ELF support to refix darwin, so please take a look again :) >> The one hunk I didn't apply was this one: >> >> @@ -1392,12 +1418,13 @@ >> case MVT::f32: >> case MVT::f64: >> - if (isVarArg && isPPC64) { >> + if (isVarArg || isPPC64) { >> // Float varargs need to be promoted to double. >> if (Arg.getValueType() == MVT::f32) >> Arg = DAG.getNode(ISD::FP_EXTEND, MVT::f64, Arg); >> >> This changes the darwin/ppc ABI. It's...

Hi all, I am currently working on AMDGPU inline assembly and encountered problem with naming clobber registers in asm constraints. It looks like by default LLVM tries to match register specified in constraint to register name of register definition in .td file but not to the AsmName for this register. For example if we have register definition: def MYReg0 : Register<"r0", 0>;

...thing like this: > > const uint32_t * > PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, > CallingConv::ID CC) const { > const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); > ... > return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask > : CSR_SVR464_RegMask) > : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask > : CSR_SVR432_RegMask); > } &g...

...thing like this: > > const uint32_t * > PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, > CallingConv::ID CC) const { > const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); > ... > return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask > : CSR_SVR464_RegMask) > : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask > : CSR_SVR432_RegMask); > } &g...

...ething like this: > > const uint32_t * > PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, > CallingConv::ID CC) const { > const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); > ... > return TM.isPPC64() ? (Subtarget.hasAltivec() ? > CSR_SVR464_Altivec_RegMask > : CSR_SVR464_RegMask) > : (Subtarget.hasAltivec() ? > CSR_SVR432_Altivec_RegMask > : CSR_SVR432_RegMask);...

...; > > > > > const PPCSubtarget &Subtarget = > > > > > MF.getSubtarget<PPCSubtarget>(); > > > > > > > > > > > > > > > ... > > > > > > > > > > > > > > > return TM.isPPC64() ? (Subtarget.hasAltivec() ? > > > > > CSR_SVR464_Altivec_RegMask > > > > > > > > > > > > > > > : CSR_SVR464_RegMask) > > > > > > > > > > > > > > > : (Subtarget.hasAltivec() ? CSR_SVR43...

...gt;> const uint32_t * >> PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, >> CallingConv::ID CC) const { >> const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); >> ... >> return TM.isPPC64() ? (Subtarget.hasAltivec() ? >> CSR_SVR464_Altivec_RegMask >> : CSR_SVR464_RegMask) >> : (Subtarget.hasAltivec() ? >> CSR_SVR432_Altivec_RegMask >> :...

*Vivek Pandya* On Wed, May 11, 2016 at 10:02 AM, vivek pandya <vivekvpandya at gmail.com> wrote: > > > *Vivek Pandya* > > > On Wed, May 11, 2016 at 9:43 AM, Mehdi Amini <mehdi.amini at apple.com> > wrote: > >> >> On May 10, 2016, at 6:06 PM, Hal Finkel <hfinkel at anl.gov> wrote: >> >> >> >>

...gt;> const uint32_t * >> PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, >> CallingConv::ID CC) const { >> const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); >> ... >> return TM.isPPC64() ? (Subtarget.hasAltivec() ? CSR_SVR464_Altivec_RegMask >> : CSR_SVR464_RegMask) >> : (Subtarget.hasAltivec() ? CSR_SVR432_Altivec_RegMask >> : CSR_SVR432_RegMask...

..._t * >>> PPCRegisterInfo::getCallPreservedMask(const MachineFunction &MF, >>> CallingConv::ID CC) const { >>> const PPCSubtarget &Subtarget = MF.getSubtarget<PPCSubtarget>(); >>> ... >>> return TM.isPPC64() ? (Subtarget.hasAltivec() ? >>> CSR_SVR464_Altivec_RegMask >>> : CSR_SVR464_RegMask) >>> : (Subtarget.hasAltivec() ? >>> CSR_SVR432_Altivec_RegMask >>>...

...; > > > > > MF.getSubtarget<PPCSubtarget>(); > > > > > > > > > > > > > > > > > > > > > ... > > > > > > > > > > > > > > > > > > > > > return TM.isPPC64() ? (Subtarget.hasAltivec() ? > > > > > > CSR_SVR464_Altivec_RegMask > > > > > > > > > > > > > > > > > > > > > : CSR_SVR464_RegMask) > > > > > > > > > > > > > > >...