llvm dev - Apr 2006 - [LLVMdev] floating point exception and SSE2 instructions

On Tue, 18 Apr 2006 23:27:39 -0700
Evan Cheng <evan.cheng at apple.com> wrote:
> Hi Simon,
> 
> The x86 backend does generate scalar SSE2 instructions. For your  
> example, it should emit something like:
Oh, how did you get this ?

[...]
> 
> There is nothing here that should cause an exception. Are you using a  
> release or cvs?
CVS.
>From what I remember, this is a bug in debian libc:
some floating point flags are set incorrectly causing SIGFPE.
Can't find the bug report ATM.

Thanks,

Simon.



-- 
Simon Burton, B.Sc.
Licensed PO Box 8066
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Australia
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http://arrowtheory.com

On Wed, 19 Apr 2006 19:28:34 +0100
Simon Burton <simon at arrowtheory.com> wrote:
> 
> >From what I remember, this is a bug in debian libc:
> some floating point flags are set incorrectly causing SIGFPE.
> Can't find the bug report ATM.
Oh, it just showed up on numpy-discussion:
http://sources.redhat.com/bugzilla/show_bug.cgi?id=10

"""
#include <fenv.h>
void feclearexcept(int ex)

This function should clear the specified exception status bits in the
FPU status register.
For CPUs with SSE support it should also clear the MXCSR status register
bits.

The problem is that feclearexcept() clears the status control bits also,
causing future floating-point errors to generate interrupts which will
lead to a SIGFPE signal which terminates the program (unless caught by a
SIGFPE handler).
"""

Is there a way I can disable SSE instruction generation in LLVM ?

Simon.


-- 
Simon Burton, B.Sc.
Licensed PO Box 8066
ANU Canberra 2601
Australia
Ph. 61 02 6249 6940
http://arrowtheory.com

On Thu, 20 Apr 2006, Simon Burton wrote:
>>> From what I remember, this is a bug in debian libc:
>> some floating point flags are set incorrectly causing SIGFPE.
>> Can't find the bug report ATM.
>
> Oh, it just showed up on numpy-discussion:
> http://sources.redhat.com/bugzilla/show_bug.cgi?id=10
>
> """
> #include <fenv.h>
> void feclearexcept(int ex)
>
> This function should clear the specified exception status bits in the 
> FPU status register. For CPUs with SSE support it should also clear the 
> MXCSR status register bits.
>
> The problem is that feclearexcept() clears the status control bits also,
> causing future floating-point errors to generate interrupts which will
> lead to a SIGFPE signal which terminates the program (unless caught by a
> SIGFPE handler).
> """
I don't see what this has to do with anything, but...
> Is there a way I can disable SSE instruction generation in LLVM ?
Yes.  Pass -mattr=-sse1,-sse2,-sse3 to lli or llc.

If you've linked the JIT into your app, you can specify this by calling 
cl::ParseCommandLineOptions on an static array, something like:

int argc;
char *Args[] = { "", "-mattr=-sse1,-sse2,-sse3", 0 };
cl::ParseCommandLineOptions(argc, Args, 0);

-Chris

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