search for: sse3

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Author: dmick Repository: /hg/zfs-crypto/gate Revision: 4559d499327b38dfc599c113d49e339f5c0308c3 Log message: 6327969 cpuid sse3 feature bit not noted on any AMD processor Files: update: usr/src/uts/i86pc/os/cpuid.c update: usr/src/uts/intel/sys/x86_archext.h

...evel-3.8.4-2.el6.i686.rpm 6baebbaf3580630b8f92e5b54b8c4b0fb687fbda291c26529e0bf58839986093 atlas-sse2-3.8.4-2.el6.i686.rpm 9783efbe359733bc5d28606e90d8755b9b97a85bcab56ecd233d0de381c8e566 atlas-sse2-devel-3.8.4-2.el6.i686.rpm 328b93da253eb866b060068444050b780182ce3ccadfed0858cd5486178ca28b atlas-sse3-3.8.4-2.el6.i686.rpm ad0effa876092aa6b50521b104d4fb8f2a269cbafba1f55b9d15096afb10911b atlas-sse-3.8.4-2.el6.i686.rpm c00a234640a31655c9066a2617910ddae6d5b68c9eb7037bcfa9e248acab6e2d atlas-sse3-devel-3.8.4-2.el6.i686.rpm 2bcc88f4036e870ecd4a6ba6c05cfe92a11d63a575a4b884af618f11da8d3246 atlas-sse-d...

..., goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, x86-64 ________________________________ From: Doerfert, Johannes <jdoerfert at anl.gov> Sent: Saturday, March 23, 2019 1:15 PM To: J S Cc: via llvm-dev Subject: Re:...

..., goldmont, goldmont-plus, tremont, nehalem, corei7, westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, znver2, x86-64 ________________________________ From: Doerfert, Johannes <jdoerfert at anl.gov> Sent: Saturday, March 23, 2019 1:15 PM To: J S Cc: via llvm-dev Subject: Re:...

...example, in X86InstrFormats.td: // SSE1 Instruction Templates: // // SSI - SSE1 instructions with XS prefix. class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>; // SSE3 Instruction Templates: // S3SI - SSE3 instructions with XSrefix. class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> pattern> : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE3]>; The only difference here is the parameter to Req...

...t file to a hard to read but > compact one. > It's also an entirely unnecessary feature: you can use multiple --check-prefix arguments on the test run to accomplish the same thing, and many tests do that today. (e.g. "FileCheck --check-prefix=CHECK --check-prefix=SSE --check-prefix=SSE3"). -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20160526/1683e704/attachment.html>

But then I should write // CHECK: something // SSE: something // SSE3: something With this feature it can be write // {{[A-Z0-9]+}} : something From: James Y Knight [mailto:jyknight at google.com] Sent: Thursday, May 26, 2016 5:53 PM To: Ehsan Amiri <ehsanamiri at gmail.com> Cc: Elena Lepilkina <Elena.Lepilkina at synopsys.com>; llvm-dev <llvm-dev at...

...-plus, tremont, nehalem, corei7, > westmere, sandybridge, corei7-avx, ivybridge, core-avx-i, haswell, > core-avx2, broadwell, skylake, skylake-avx512, skx, cascadelake, > cannonlake, icelake-client, icelake-server, knl, knm, k8, athlon64, > athlon-fx, opteron, k8-sse3, athlon64-sse3, opteron-sse3, amdfam10, > barcelona, btver1, btver2, bdver1, bdver2, bdver3, bdver4, znver1, > znver2, > x86-64 > > > ------------------------------ > *From:* Doerfert, Johannes <jdoerfert at anl.gov> > *Sent:* Saturday, March 23, 2019 1:15...

...argmemonly nounwind declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i32, i1) #5 attributes #0 = { noreturn "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="core2" "target-features"="+ssse3,+cx16,+fxsr,+mmx,+x87,+sse,+sse2,+sse3" } attributes #1 = { "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="core2" "target-features"="+ssse3,+cx16,+fxsr,+mmx,+x87,+sse,+sse2,+sse3" } attributes...

Hi Bruno, > Some comments: > > + // Try to synthesize horizontal adds from adds of shuffles. > + if (((Subtarget->hasSSE3()&& (VT == MVT::v4f32 || VT == MVT::v2f64)) || > + (Subtarget->hasAVX()&& (VT == MVT::v8f32 || VT == MVT::v4f64)))&& > + isHorizontalBinOp(LHS, RHS, true)) > > 1) You probably want to do something like: > > "bool HasHorizontalArith = Su...

...Instruction Templates: > // > // SSI - SSE1 instructions with XS prefix. > > class SSI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> > pattern> > > : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE1]>; > > // SSE3 Instruction Templates: > // S3SI - SSE3 instructions with XSrefix. > > class S3SI<bits<8> o, Format F, dag outs, dag ins, string asm, list<dag> > pattern> > > : I<o, F, outs, ins, asm, pattern>, XS, Requires<[HasSSE3]>; > > The only di...

...ve a Dell Precision M6300 In particular, I''m wondering if my graphics card and wired/wireless NIC are going to work? Vid card: Nvidia Quadro M1600 wired NIC: Broadcom NetXtreme gigabit wireless NIC: Intel 3945 ABG # uname -a SunOS appdev 5.11 snv_80 i86pc i386 i86xpv # isainfo -x amd64: ssse3 cx16 sse3 sse2 sse fxsr mmx cmov cx8 tsc fpu i386: ssse3 ahf cx16 sse3 sse2 sse fxsr mmx cmov cx8 tsc fpu # psrinfo -vp The physical processor has 2 virtual processors (0 1) x86 (GenuineIntel 6FA family 6 model 15 step 10 clock 2400 MHz) Intel(r) Core(tm)2 Duo CPU T7700 @ 2.40GHz T...

...acy cmpxchg16 cmpxchg8 cntxid dca de ds dscpl dtes64 est extapic f16c +ffxsr fma4 fpu fxsr htt hypervisor ia64 ibs lahfsahf lm lwp mca mce misalignsse +mmx mmxext monitor movbe msr mtrr nodeid nx osvw osxsave pae page1gb pat pbe +pclmulqdq pdcm pge popcnt pse pse36 psn rdtscp skinit smx ss sse sse2 sse3 +sse4.1 sse4.2 sse4a ssse3 svm svm_decode svm_lbrv svm_npt svm_nrips +svm_pausefilt svm_tscrate svm_vmcbclean syscall sysenter tbm tm tm2 topoext tsc +vme vmx wdt x2apic xop xsave xtpr + +Example to hide two features from the guest: ''tm'', which is bit #29 in EDX, and +''pn...

...uot;true" "no-frame-pointer-elim-non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="core2" "target-features"="+cx16,+sse,+sse2,+sse3,+ssse3" "unsafe-fp-math"="false" "use-soft-float"="false" } --- I could not figure out how to decorate my C code to emit the nocapture attribute, __attribute(( nocapture) is unknown. So I tried to modify the IR code by hand to read thusly: declare...

...wind > declare void @llvm.memset.p0i8.i64(i8* nocapture writeonly, i8, i64, i32, i1) #5 > > attributes #0 = { noreturn "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="core2" "target-features"="+ssse3,+cx16,+fxsr,+mmx,+x87,+sse,+sse2,+sse3" } > attributes #1 = { "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf" "target-cpu"="core2" "target-features"="+ssse3,+cx16,+fxsr,+mmx,+x87,+sse,+sse2,+sse3" } > a...

Hi Joe & Michael, In rev. 151382 you have changed the fptoui implementation of the x86 codegen for win32. Before the change fptoui was lowered to flds 16(%esp) fisttpll 8(%esp) movl 8(%esp), %eax After the change fptoui is lowered to flds 40(%esp) calll _ftol2 Please note that the assumption that _ftol2 doesn't modify ECX isn't true on sandybridge platform.

...s which will > lead to a SIGFPE signal which terminates the program (unless caught by a > SIGFPE handler). > """ I don't see what this has to do with anything, but... > Is there a way I can disable SSE instruction generation in LLVM ? Yes. Pass -mattr=-sse1,-sse2,-sse3 to lli or llc. If you've linked the JIT into your app, you can specify this by calling cl::ParseCommandLineOptions on an static array, something like: int argc; char *Args[] = { "", "-mattr=-sse1,-sse2,-sse3", 0 }; cl::ParseCommandLineOptions(argc, Args, 0); -Chris --...

...amd64 CPU: AMD Phenom(tm) 9750 Quad-Core Processor (2410.66-MHz K8-class CPU) Origin = "AuthenticAMD" Id = 0x100f23 Stepping = 3 Features=0x178bfbff<FPU,VME,DE,PSE,TSC,MSR,PAE,MCE,CX8,APIC,SEP,MTRR,PGE,MCA,CMOV,PAT,PSE36,CLFLUSH,MMX,FXSR,SSE,SSE2,HTT> Features2=0x802009<SSE3,MON,CX16,<b23>> AMD Features=0xee500800<SYSCALL,NX,MMX+,FFXSR,Page1GB,RDTSCP,LM,3DNow!+,3DNow!> AMD Features2=0x7ff<LAHF,CMP,SVM,ExtAPIC,CR8,<b5>,<b6>,<b7>,Prefetch,<b9>,<b10>> Cores per package: 4 usable memory = 8547172352 (8151 MB) avail m...

...39;t know what the best way to deal with this in LLVM would be, someone else may have a better idea. as for what targets support which operations, in the case of SSE, go check the Intel and AMD64 docs. it can be noted that most processors around now support SSE2, but not as many support newer (SSE3/SSSE3, SSE4, ...). note that Intel and AMD have had a split over the issue: Intel implements SSE3 and SSE4; AMD implements parts of SSE3 and SSE4, but not other parts; AMD is implementing SSE5, but it uses instructions which Intel does not use; ... so, SSE2 is fairly safe at this point, but much...