Xen devel - Jul 2013 - [PATCH] xen: extract register definitions from ns16550 into a separated header

Since both UART driver codes on Allwinner A31, OMAP5 and x86 would use
these definitions, we refactor the codes into a separated header to avoid
unnecessary duplication.

Signed-off-by: Chen Baozi <baozich@gmail.com>
---
 xen/drivers/char/ns16550.c     |  71 +---------------------------
 xen/include/xen/ns16550-uart.h | 104 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 105 insertions(+), 70 deletions(-)
 create mode 100644 xen/include/xen/ns16550-uart.h

diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
index e0c87bb..512054a 100644
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -19,6 +19,7 @@
 #include <xen/iocap.h>
 #include <xen/pci.h>
 #include <xen/pci_regs.h>
+#include <xen/ns16550-uart.h>
 #include <asm/io.h>
 #ifdef CONFIG_X86
 #include <asm/fixmap.h>
@@ -58,76 +59,6 @@ static struct ns16550 {
     u8 bar_idx;
 } ns16550_com[2] = { { 0 } };
 
-/* Register offsets */
-#define RBR             0x00    /* receive buffer       */
-#define THR             0x00    /* transmit holding     */
-#define IER             0x01    /* interrupt enable     */
-#define IIR             0x02    /* interrupt identity   */
-#define FCR             0x02    /* FIFO control         */
-#define LCR             0x03    /* line control         */
-#define MCR             0x04    /* Modem control        */
-#define LSR             0x05    /* line status          */
-#define MSR             0x06    /* Modem status         */
-#define DLL             0x00    /* divisor latch (ls) (DLAB=1) */
-#define DLM             0x01    /* divisor latch (ms) (DLAB=1) */
-
-/* Interrupt Enable Register */
-#define IER_ERDAI       0x01    /* rx data recv''d       */
-#define IER_ETHREI      0x02    /* tx reg. empty        */
-#define IER_ELSI        0x04    /* rx line status       */
-#define IER_EMSI        0x08    /* MODEM status         */
-
-/* Interrupt Identification Register */
-#define IIR_NOINT       0x01    /* no interrupt pending */
-#define IIR_IMASK       0x06    /* interrupt identity:  */
-#define IIR_LSI         0x06    /*  - rx line status    */
-#define IIR_RDAI        0x04    /*  - rx data recv''d    */
-#define IIR_THREI       0x02    /*  - tx reg. empty     */
-#define IIR_MSI         0x00    /*  - MODEM status      */
-
-/* FIFO Control Register */
-#define FCR_ENABLE      0x01    /* enable FIFO          */
-#define FCR_CLRX        0x02    /* clear Rx FIFO        */
-#define FCR_CLTX        0x04    /* clear Tx FIFO        */
-#define FCR_DMA         0x10    /* enter DMA mode       */
-#define FCR_TRG1        0x00    /* Rx FIFO trig lev 1   */
-#define FCR_TRG4        0x40    /* Rx FIFO trig lev 4   */
-#define FCR_TRG8        0x80    /* Rx FIFO trig lev 8   */
-#define FCR_TRG14       0xc0    /* Rx FIFO trig lev 14  */
-
-/* Line Control Register */
-#define LCR_DLAB        0x80    /* Divisor Latch Access */
-
-/* Modem Control Register */
-#define MCR_DTR         0x01    /* Data Terminal Ready  */
-#define MCR_RTS         0x02    /* Request to Send      */
-#define MCR_OUT2        0x08    /* OUT2: interrupt mask */
-#define MCR_LOOP        0x10    /* Enable loopback test mode */
-
-/* Line Status Register */
-#define LSR_DR          0x01    /* Data ready           */
-#define LSR_OE          0x02    /* Overrun              */
-#define LSR_PE          0x04    /* Parity error         */
-#define LSR_FE          0x08    /* Framing error        */
-#define LSR_BI          0x10    /* Break                */
-#define LSR_THRE        0x20    /* Xmit hold reg empty  */
-#define LSR_TEMT        0x40    /* Xmitter empty        */
-#define LSR_ERR         0x80    /* Error                */
-
-/* These parity settings can be ORed directly into the LCR. */
-#define PARITY_NONE     (0<<3)
-#define PARITY_ODD      (1<<3)
-#define PARITY_EVEN     (3<<3)
-#define PARITY_MARK     (5<<3)
-#define PARITY_SPACE    (7<<3)
-
-/* Frequency of external clock source. This definition assumes PC platform. */
-#define UART_CLOCK_HZ   1843200
-
-/* Resume retry settings */
-#define RESUME_DELAY    MILLISECS(10)
-#define RESUME_RETRIES  100
-
 static char ns_read_reg(struct ns16550 *uart, int reg)
 {
     if ( uart->remapped_io_base == NULL )
diff --git a/xen/include/xen/ns16550-uart.h b/xen/include/xen/ns16550-uart.h
new file mode 100644
index 0000000..ee6e3e7
--- /dev/null
+++ b/xen/include/xen/ns16550-uart.h
@@ -0,0 +1,104 @@
+/*
+ * xen/include/xen/ns16550-uart.h
+ *
+ * This header is extracted from driver/char/ns16550.c
+ *
+ * Common constant definition between early printk and the UART driver
+ * for the 16550-series UART
+ *
+ * Copyright (c) 2003-2005, K A Fraser
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __XEN_NS16550_H__
+#define __XEN_NS16550_H__
+
+/* Register offsets */
+#define RBR             0x00    /* receive buffer       */
+#define THR             0x00    /* transmit holding     */
+#define IER             0x01    /* interrupt enable     */
+#define IIR             0x02    /* interrupt identity   */
+#define FCR             0x02    /* FIFO control         */
+#define LCR             0x03    /* line control         */
+#define MCR             0x04    /* Modem control        */
+#define LSR             0x05    /* line status          */
+#define MSR             0x06    /* Modem status         */
+#define DLL             0x00    /* divisor latch (ls) (DLAB=1) */
+#define DLM             0x01    /* divisor latch (ms) (DLAB=1) */
+
+/* Interrupt Enable Register */
+#define IER_ERDAI       0x01    /* rx data recv''d       */
+#define IER_ETHREI      0x02    /* tx reg. empty        */
+#define IER_ELSI        0x04    /* rx line status       */
+#define IER_EMSI        0x08    /* MODEM status         */
+
+/* Interrupt Identification Register */
+#define IIR_NOINT       0x01    /* no interrupt pending */
+#define IIR_IMASK       0x06    /* interrupt identity:  */
+#define IIR_LSI         0x06    /*  - rx line status    */
+#define IIR_RDAI        0x04    /*  - rx data recv''d    */
+#define IIR_THREI       0x02    /*  - tx reg. empty     */
+#define IIR_MSI         0x00    /*  - MODEM status      */
+
+/* FIFO Control Register */
+#define FCR_ENABLE      0x01    /* enable FIFO          */
+#define FCR_CLRX        0x02    /* clear Rx FIFO        */
+#define FCR_CLTX        0x04    /* clear Tx FIFO        */
+#define FCR_DMA         0x10    /* enter DMA mode       */
+#define FCR_TRG1        0x00    /* Rx FIFO trig lev 1   */
+#define FCR_TRG4        0x40    /* Rx FIFO trig lev 4   */
+#define FCR_TRG8        0x80    /* Rx FIFO trig lev 8   */
+#define FCR_TRG14       0xc0    /* Rx FIFO trig lev 14  */
+
+/* Line Control Register */
+#define LCR_DLAB        0x80    /* Divisor Latch Access */
+
+/* Modem Control Register */
+#define MCR_DTR         0x01    /* Data Terminal Ready  */
+#define MCR_RTS         0x02    /* Request to Send      */
+#define MCR_OUT2        0x08    /* OUT2: interrupt mask */
+#define MCR_LOOP        0x10    /* Enable loopback test mode */
+
+/* Line Status Register */
+#define LSR_DR          0x01    /* Data ready           */
+#define LSR_OE          0x02    /* Overrun              */
+#define LSR_PE          0x04    /* Parity error         */
+#define LSR_FE          0x08    /* Framing error        */
+#define LSR_BI          0x10    /* Break                */
+#define LSR_THRE        0x20    /* Xmit hold reg empty  */
+#define LSR_TEMT        0x40    /* Xmitter empty        */
+#define LSR_ERR         0x80    /* Error                */
+
+/* These parity settings can be ORed directly into the LCR. */
+#define PARITY_NONE     (0<<3)
+#define PARITY_ODD      (1<<3)
+#define PARITY_EVEN     (3<<3)
+#define PARITY_MARK     (5<<3)
+#define PARITY_SPACE    (7<<3)
+
+/* Frequency of external clock source. This definition assumes PC platform. */
+#define UART_CLOCK_HZ   1843200
+
+/* Resume retry settings */
+#define RESUME_DELAY    MILLISECS(10)
+#define RESUME_RETRIES  100
+
+#endif /* __XEN_NS16550_H__ */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
-- 
1.8.1.4