This is to allow people to tweak their clocks at will. Marcin asked for
something like this to help him REing.
I was personnaly interested to see if openarena fps rate would scale with the
GPU clocks (it doesn't ... yet).
This patch will also allow overclockers to test their cards (On my NVS 140M:
Memory +66%, core: +66%, shader: +25%).
This patch introduces a few sysfs files:
- custom_*: Get/set the current clock/voltage value (kHz or *10mV)
Once you've set all the values you wanted to change, just echo
"custom" into performance_level.
WARNINGS:
1) Pay attention to your current temperature, my card's temperature rose by
9?C.
We'll need to use the thermal zones to be able to monitor that and downclock
the card automatically (if someone wants to help here, he would be welcome).
2) Changing clocks isn't safe at the moment, I'm working on this but the
reclocking process is really different accross the boards.
So far, nv84 and nv86 work perfectly (as in no flicker and being able to reclock
while playing games).
By the time I get this patch ready, please stop 3D applications, switch to a
tty, do the reclock and come back to X.
Signed-off-by: Martin Peres <martin.peres at ensi-bourges.fr>
---
drivers/gpu/drm/nouveau/nouveau_drv.h | 1 +
drivers/gpu/drm/nouveau/nouveau_pm.c | 207 ++++++++++++++++++++++++++++++++-
2 files changed, 207 insertions(+), 1 deletions(-)
diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h
b/drivers/gpu/drm/nouveau/nouveau_drv.h
index a52b1da..5928301 100644
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -463,6 +463,7 @@ struct nouveau_pm_engine {
struct nouveau_pm_threshold_temp threshold_temp;
struct nouveau_pm_level boot;
+ struct nouveau_pm_level custom;
struct nouveau_pm_level *cur;
struct device *hwmon;
diff --git a/drivers/gpu/drm/nouveau/nouveau_pm.c
b/drivers/gpu/drm/nouveau/nouveau_pm.c
index d938141..49d8a17 100644
--- a/drivers/gpu/drm/nouveau/nouveau_pm.c
+++ b/drivers/gpu/drm/nouveau/nouveau_pm.c
@@ -35,6 +35,10 @@
#include <linux/hwmon-sysfs.h>
static int
+nouveau_pm_perflvl_get(struct drm_device *dev,
+ struct nouveau_pm_level *perflvl);
+
+static int
nouveau_pm_clock_set(struct drm_device *dev, struct nouveau_pm_level *perflvl,
u8 id, u32 khz)
{
@@ -61,7 +65,7 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct
nouveau_pm_level *perflvl)
struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
int ret;
- if (perflvl == pm->cur)
+ if (perflvl != &pm->custom && perflvl == pm->cur)
return 0;
if (pm->voltage.supported && pm->voltage_set &&
perflvl->voltage) {
@@ -78,6 +82,10 @@ nouveau_pm_perflvl_set(struct drm_device *dev, struct
nouveau_pm_level *perflvl)
nouveau_pm_clock_set(dev, perflvl, PLL_UNK05, perflvl->unk05);
pm->cur = perflvl;
+
+ /* Copy the new profile to the custom profile */
+ nouveau_pm_perflvl_get(dev, &pm->custom);
+
return 0;
}
@@ -97,6 +105,8 @@ nouveau_pm_profile_set(struct drm_device *dev, const char
*profile)
if (!strncmp(profile, "boot", 4))
perflvl = &pm->boot;
+ else if (!strncmp(profile, "custom", 6))
+ perflvl = &pm->custom;
else {
int pl = simple_strtol(profile, NULL, 10);
int i;
@@ -179,6 +189,45 @@ nouveau_pm_perflvl_info(struct nouveau_pm_level *perflvl,
char *ptr, int len)
}
static ssize_t
+nouveau_set_custom_clock(struct device *d, u32 id,
+ const char *buf, size_t count)
+{
+ struct drm_device *dev = pci_get_drvdata(to_pci_dev(d));
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+ u32 *custom_clock;
+ void *pre_state;
+ long sysfs_value;
+
+ if (id == PLL_CORE)
+ custom_clock = &pm->custom.core;
+ else if(id == PLL_MEMORY)
+ custom_clock = &pm->custom.memory;
+ else if(id == PLL_SHADER)
+ custom_clock = &pm->custom.shader;
+ else if(id == PLL_UNK05)
+ custom_clock = &pm->custom.unk05;
+ else
+ return -EINVAL;
+
+ if (strict_strtol(buf, 10, &sysfs_value) == -EINVAL)
+ return -EINVAL;
+
+ if (sysfs_value < 5000)
+ return -EINVAL;
+
+ pre_state = pm->clock_pre(dev, &pm->custom, id, (u32) sysfs_value);
+ if (IS_ERR(pre_state))
+ return -ENOENT;
+ else
+ kfree(pre_state);
+
+ *custom_clock = (u32) sysfs_value;
+
+ return strlen(buf);
+}
+
+static ssize_t
nouveau_pm_get_perflvl_info(struct device *d,
struct device_attribute *a, char *buf)
{
@@ -208,6 +257,8 @@ nouveau_pm_get_perflvl(struct device *d, struct
device_attribute *a, char *buf)
snprintf(ptr, len, "setting: boot\n");
else if (pm->cur == &pm->boot)
snprintf(ptr, len, "setting: boot\nc: ");
+ else if (pm->cur == &pm->custom)
+ snprintf(ptr, len, "setting: custom\nclocks: ");
else
snprintf(ptr, len, "setting: static %d\nc: ", pm->cur->id);
ptr += strlen(buf);
@@ -235,6 +286,132 @@ nouveau_pm_set_perflvl(struct device *d, struct
device_attribute *a,
static DEVICE_ATTR(performance_level, S_IRUGO | S_IWUSR,
nouveau_pm_get_perflvl, nouveau_pm_set_perflvl);
+static ssize_t
+nouveau_pm_get_custom_core(struct device *d,
+ struct device_attribute *a, char *buf)
+{
+ struct drm_device *dev = pci_get_drvdata(to_pci_dev(d));
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+
+ snprintf(buf, PAGE_SIZE, "%d\n", pm->custom.core);
+ return strlen(buf);
+}
+
+static ssize_t
+nouveau_pm_set_custom_core(struct device *d, struct device_attribute *a,
+ const char *buf, size_t count)
+{
+ return nouveau_set_custom_clock(d, PLL_CORE, buf, count);
+}
+
+static DEVICE_ATTR(custom_core, S_IRUGO | S_IWUSR,
+ nouveau_pm_get_custom_core, nouveau_pm_set_custom_core);
+
+static ssize_t
+nouveau_pm_get_custom_memory(struct device *d,
+ struct device_attribute *a, char *buf)
+{
+ struct drm_device *dev = pci_get_drvdata(to_pci_dev(d));
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+
+ snprintf(buf, PAGE_SIZE, "%d\n", pm->custom.memory);
+ return strlen(buf);
+}
+
+static ssize_t
+nouveau_pm_set_custom_memory(struct device *d, struct device_attribute *a,
+ const char *buf, size_t count)
+{
+ return nouveau_set_custom_clock(d, PLL_MEMORY, buf, count);
+}
+
+static DEVICE_ATTR(custom_memory, S_IRUGO | S_IWUSR,
+ nouveau_pm_get_custom_memory, nouveau_pm_set_custom_memory);
+
+static ssize_t
+nouveau_pm_get_custom_shader(struct device *d,
+ struct device_attribute *a, char *buf)
+{
+ struct drm_device *dev = pci_get_drvdata(to_pci_dev(d));
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+
+ snprintf(buf, PAGE_SIZE, "%d\n", pm->custom.shader);
+ return strlen(buf);
+}
+
+static ssize_t
+nouveau_pm_set_custom_shader(struct device *d, struct device_attribute *a,
+ const char *buf, size_t count)
+{
+ return nouveau_set_custom_clock(d, PLL_SHADER, buf, count);
+}
+
+static DEVICE_ATTR(custom_shader, S_IRUGO | S_IWUSR,
+ nouveau_pm_get_custom_shader, nouveau_pm_set_custom_shader);
+
+static ssize_t
+nouveau_pm_get_custom_unk05(struct device *d,
+ struct device_attribute *a, char *buf)
+{
+ struct drm_device *dev = pci_get_drvdata(to_pci_dev(d));
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+ int len = PAGE_SIZE;
+ char *ptr = buf;
+
+ snprintf(ptr, len, "%d\n", pm->custom.unk05);
+ return strlen(buf);
+}
+
+static ssize_t
+nouveau_pm_set_custom_unk05(struct device *d, struct device_attribute *a,
+ const char *buf, size_t count)
+{
+ return nouveau_set_custom_clock(d, PLL_UNK05, buf, count);
+}
+
+static DEVICE_ATTR(custom_unk05, S_IRUGO | S_IWUSR,
+ nouveau_pm_get_custom_unk05, nouveau_pm_set_custom_unk05);
+
+static ssize_t
+nouveau_pm_get_custom_voltage(struct device *d,
+ struct device_attribute *a, char *buf)
+{
+ struct drm_device *dev = pci_get_drvdata(to_pci_dev(d));
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+
+ snprintf(buf, PAGE_SIZE, "%d\n", pm->custom.voltage);
+
+ return strlen(buf);
+}
+
+static ssize_t
+nouveau_pm_set_custom_voltage(struct device *d, struct device_attribute *a,
+ const char *buf, size_t count)
+{
+ struct drm_device *dev = pci_get_drvdata(to_pci_dev(d));
+ struct drm_nouveau_private *dev_priv = dev->dev_private;
+ struct nouveau_pm_engine *pm = &dev_priv->engine.pm;
+ long voltage_sysfs;
+
+ if (strict_strtol(buf, 10, &voltage_sysfs) == -EINVAL)
+ return -EINVAL;
+
+ if (nouveau_volt_vid_lookup(dev, voltage_sysfs) < 0)
+ return -ENOENT;
+
+ pm->custom.voltage = (u32) voltage_sysfs;
+ return strlen(buf);
+}
+
+static DEVICE_ATTR(custom_voltage, S_IRUGO | S_IWUSR,
+ nouveau_pm_get_custom_voltage,
+ nouveau_pm_set_custom_voltage);
+
static int
nouveau_sysfs_init(struct drm_device *dev)
{
@@ -266,6 +443,26 @@ nouveau_sysfs_init(struct drm_device *dev)
}
}
+ ret = device_create_file(d, &dev_attr_custom_core);
+ if (ret)
+ return ret;
+
+ ret = device_create_file(d, &dev_attr_custom_memory);
+ if (ret)
+ return ret;
+
+ ret = device_create_file(d, &dev_attr_custom_shader);
+ if (ret)
+ return ret;
+
+ ret = device_create_file(d, &dev_attr_custom_unk05);
+ if (ret)
+ return ret;
+
+ ret = device_create_file(d, &dev_attr_custom_voltage);
+ if (ret)
+ return ret;
+
return 0;
}
@@ -286,6 +483,11 @@ nouveau_sysfs_fini(struct drm_device *dev)
device_remove_file(d, &pl->dev_attr);
}
+ device_remove_file(d, &dev_attr_custom_core);
+ device_remove_file(d, &dev_attr_custom_memory);
+ device_remove_file(d, &dev_attr_custom_shader);
+ device_remove_file(d, &dev_attr_custom_unk05);
+ device_remove_file(d, &dev_attr_custom_voltage);
}
#ifdef CONFIG_HWMON
@@ -497,6 +699,9 @@ nouveau_pm_init(struct drm_device *dev)
NV_INFO(dev, "c: %s", info);
}
+ /* set custom clocks to the boot performance level */
+ nouveau_pm_perflvl_get(dev, &pm->custom);
+
/* switch performance levels now if requested */
if (nouveau_perflvl != NULL) {
ret = nouveau_pm_profile_set(dev, nouveau_perflvl);
--
1.7.3.2
--------------030803020201020400020704--