-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Big changes here are EXA and Xv support for R6xx/R7xx chips. Requires an updated drm. Other than that, mostly bug fixes. Adam Jackson (3): output: Allow for multiple DisplayPort outputs. Add some more cases to the DVI single-link checks. uniphy: start adding DisplayPort setup Alex Deucher (81): Initial R6xx/R7xx EXA and textured video support Allow rotation on r6xx/r7xx EXA: fix and re-enable Solid() on R7xx r6xx/r7xx EXA: cleanup overlapping copy R6xx/R7xx EXA: improve overlapping copy performance r6xx/r7xx EXA: fix corruption when doing sw access Revert "R6xx/R7xx EXA: improve overlapping copy performance" R6xx/R7xx EXA: add accelerated UTS/DFS hooks Revert "r6xx/r7xx EXA: Optimize overlapping copy" R6xx/R7xx EXA: fallback on overlapping blits for now R6xx/R7xx EXA: Fix typo in DFS R6xx/R7xx Xv: fix typos in cache flushing commands R6xx/R7xx UTS: move actual upload to separate function R6xx/R7xx Xv: implement native shader for planar formats R6xx/R7xx Xv: add accelerated uploads for planar formats R6xx/R7xx Xv: fix cache flush buffer size for planar R6xx/R7xx: Add checks to make sure we don't overrun VB space R6xx/R7xx Xv: Add native support for packed formats R6xx/R7xx Xv: add support for packed uploads adjust alignment R6xx/R7xx: Move engine idle to sync functions R6xx/R7xx: be more verbose about what function ran out of VB space R6xx/R7xx: handle running out of vertex buffer space R6xx/R7xx Xv: switch packed over to Yang's new shader code Revert "R6xx/R7xx: handle running out of vertex buffer space" R6xx/R7xx EXA: properly handle non repeat cases in the texture setup R6xx/R7xx EXA: handle running out of vertex space in the copy path R6xx/R7xx: switch to drm for wait for idle R6xx/R7xx EXA: switch to surface sync packet Bump version post release R6xx/R7xx: fixup accel paths R6xx/R7xx: reset 3D state after VT switch R6xx/R7xx EXA/Xv: properly deal with running out of vertex buffer space R6xx/R7xx Xv: fix some missing bits from last commit R6xx/R7xx: wait for MC idle when changing the MC Fix MC setup on systems with more than 512 MB of VRAM R6xx/R7xx: fix up a few more paths radeon: one more 32 -> 64 just to be safe Don't write new HDP location until we've written the new FB location RBBM_GUICNTL is pre-r6xx only R6xx/R7xx: add wait for idle MMIO path RS600: fix up MC setup radeon: re-enable load detection output attribute for TV/CV RS600: fix MC addr mask R6xx/R7xx EXA: Optimize temp surface for overlapping copies R6xx/R7xx EXA: init copy_area to NULL R6xx/R7xx EXA: same surface and same coords equals nop RS600: enable the DRI by default R6xx/R7xx: use shadowfb if DRI is disabled DCE3.2: fix up Save()/Restore() R300: Add AGP quirk Print a message when we have a shared DDC line R6xx/R7xx: switch emit functions to macros R6xx/R7xx: write vertexes directly to the IB R6xx/R7xx: code cleanups R6xx/R7xx Xv: combine packed and planar shaders R6xx/R7xx EXA: combine composite mask/non-mask VS R6xx/R7xx EXA: cleanup composite texture setup R6xx/r7xx: remove some unneeded code I missed in the last commit Rotation: don't rotate if acceleration is not active AVIVO: add aspect scaling mode radeon: adjust LVDS so that default modes get added Revert "radeon: adjust LVDS so that default modes get added" radeon: just add some common modes for LVDS ATOM: don't use fixed ref div for LVDS RN50: fix up cloning on servers R6xx/R7xx: disable XV_BICUBIC attribute R6xx/R7xx: wire up DMAForXv option like older asics radeon: add a few more default common modes for lvds AVIVO: fix panning R6xx/r7xx: clarify EXA message R4xx: add R4xxATOM option radeon: clean more thoroughly in RADEONFreeRec() RS600: fix page table size for rs600 as well R6xx/r7xx: clarify accel messages R6xx/R7xx: return in RADEONWaitForIdleMMIO() if accel is off R6xx/R7xx: fix up vline stuff along the lines of previous chips R6xx/R7xx: EXA VSync Option not supported yet radeon: add support for 30 bit LUTs radeon: man page updates bump for release Bryce Harrington (1): Quirk for RV280 on 82865G/PE/P DRAM Controller/Host-Hub Christian Koenig (1): R6xx/R7xx: move shaders to r600_shader.c and fixup Xv PS Cooper Yuan (1): radeon: save bios scratch registers in Preinit() Dave Airlie (3): r600: enable DRI by default r600: fix sizing of PCI GART table for r600 r600: reload shaders into VRAM on resume Mark van Doesburg (1): R6xx/R7xx EXA: use a temp surface for overlapping copy Michel D?nzer (6): Fix compile warning when building without EXA. Only call RADEONWaitForVLine if it might actually do anything useful. EXA: Pass pScrn and info into RadeonCompositeTile. EXA: Adapt to EXA changes in xserver Git. Revert "EXA: Adapt to EXA changes in xserver Git." EXA: Make sure Prepare/FinishAccess hooks can handle EXA_PREPARE_AUX* indices. Pierre Ossman (2): Fix bad range adjustment in VLINE code. Xv vsync support on r6xx/r7xx cards. Tormod Volden (3): Janitor: cosmetic clean-up of AGPMode quirk table M9+: Add AGP quirk for Sony Vaio RV350: Add AGPMode quirk for Thinkpad Yang Zhao (5): r6xx/r7xx EXA: Optimize overlapping copy R6xx/R7xx EXA: Optimize overlapping copy R6xx/R7xx Xv: Planar - Properly scale Y'CbCr values before converting to RGB R6xx/R7xx EXA: Further optimizations to overlapping copy R6xx/R7xx shader: Fix OFFSET_[XYZ] macro for TEX_DWORD2 to accept floats root (2): atom: Enable DisplayPort source to DVI/HDMI sink output: Filter out dual-link modes from DP->DVI connections ???(Yu-yeon Oh) (1): radeon_driver.c small memory bug git tag: xf86-video-ati-6.12.0 http://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-6.12.0.tar.bz2 MD5: 540b25842f8e09164cf4d2376995dc68 xf86-video-ati-6.12.0.tar.bz2 SHA1: 40d3303c9db718b1ca3ffbd16ead6b8fac28561f xf86-video-ati-6.12.0.tar.bz2 http://xorg.freedesktop.org/archive/individual/driver/xf86-video-ati-6.12.0.tar.gz MD5: 7acdd365f5de5ba4c6dc0c04ffd02a52 xf86-video-ati-6.12.0.tar.gz SHA1: 7cdb553a6eb931175cf2d8c299a4e5378b959d09 xf86-video-ati-6.12.0.tar.gz -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.6 (GNU/Linux) iD8DBQFJuu2Mm07k+YR03kARAh+yAJ4wObnD/LATnXQrG7af+b8/1WD3NACglE08 wem9Yq0c8WAF/eGOpiXhzgE=RqM1 -----END PGP SIGNATURE-----