From: Yang Zhang <yang.z.zhang@Intel.com> This series patches fix some issues which i encountered when boot L1 hyper-v. This patch fixed RHEL6 guest installation problem with L1 hyper-v: Nested VMX: update nested paging mode when vmswitch is in progress The two fixing SMP hyper-v boot issue: VMX,apicv: Set "NMI-window exiting" for NMI Nested VMX: Setup the virtual NMI exiting info: Yang Zhang (3): Nested VMX: update nested paging mode when vmswitch is in progress VMX,apicv: Set "NMI-window exiting" for NMI Nested VMX: Setup the virtual NMI exiting info xen/arch/x86/hvm/hvm.c | 4 ++-- xen/arch/x86/hvm/vmx/intr.c | 7 ++++--- xen/arch/x86/hvm/vmx/vvmx.c | 6 ++++++ 3 files changed, 12 insertions(+), 5 deletions(-)
Yang Zhang
2013-Dec-12 02:06 UTC
[PATCH 1/3] Nested VMX: update nested paging mode when vmswitch is in progress
From: Yang Zhang <yang.z.zhang@Intel.com>
virtual vmentry will change paging related stucture, so corrensponding
nested mode need to be updated which is missing currently.
Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
---
xen/arch/x86/hvm/hvm.c | 4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
This patch fixed RHEL6 guest installation problem with L1 hyper-v.
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c
index 69f7e74..1f62e00 100644
--- a/xen/arch/x86/hvm/hvm.c
+++ b/xen/arch/x86/hvm/hvm.c
@@ -1925,7 +1925,7 @@ int hvm_set_cr0(unsigned long value)
hvm_update_cr(v, 0, value);
if ( (value ^ old_value) & X86_CR0_PG ) {
- if ( !nestedhvm_vmswitch_in_progress(v) &&
nestedhvm_vcpu_in_guestmode(v) )
+ if ( nestedhvm_vcpu_in_guestmode(v) )
paging_update_nestedmode(v);
else
paging_update_paging_modes(v);
@@ -2014,7 +2014,7 @@ int hvm_set_cr4(unsigned long value)
(X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE | X86_CR4_SMEP)) ||
(!(value & X86_CR4_PCIDE) && (old_cr & X86_CR4_PCIDE))
)
{
- if ( !nestedhvm_vmswitch_in_progress(v) &&
nestedhvm_vcpu_in_guestmode(v) )
+ if ( nestedhvm_vcpu_in_guestmode(v) )
paging_update_nestedmode(v);
else
paging_update_paging_modes(v);
--
1.7.1
From: Yang Zhang <yang.z.zhang@Intel.com>
Enable NMI-window exiting if interrupt is blocked by NMI under apicv enabled
platform.
Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
---
xen/arch/x86/hvm/vmx/intr.c | 7 ++++---
1 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/intr.c b/xen/arch/x86/hvm/vmx/intr.c
index 7757910..8507432 100644
--- a/xen/arch/x86/hvm/vmx/intr.c
+++ b/xen/arch/x86/hvm/vmx/intr.c
@@ -252,10 +252,11 @@ void vmx_intr_assist(void)
intblk = hvm_interrupt_blocked(v, intack);
if ( cpu_has_vmx_virtual_intr_delivery )
{
- /* Set "Interrupt-window exiting" for ExtINT */
+ /* Set "Interrupt-window exiting" for ExtINT and NMI. */
if ( (intblk != hvm_intblk_none) &&
- ( (intack.source == hvm_intsrc_pic) ||
- ( intack.source == hvm_intsrc_vector) ) )
+ (intack.source == hvm_intsrc_pic ||
+ intack.source == hvm_intsrc_vector ||
+ intack.source == hvm_intsrc_nmi) )
{
enable_intr_window(v, intack);
goto out;
--
1.7.1
Yang Zhang
2013-Dec-12 02:06 UTC
[PATCH 3/3] Nested VMX: Setup the virtual NMI exiting info
From: Yang Zhang <yang.z.zhang@Intel.com>
When inject a virtual nmi exit to L1, hypervisor need to set the
virtual vmcs with right vaule which is missing in current Xen.
Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
---
xen/arch/x86/hvm/vmx/vvmx.c | 6 ++++++
1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/xen/arch/x86/hvm/vmx/vvmx.c b/xen/arch/x86/hvm/vmx/vvmx.c
index 0daad79..41db52b 100644
--- a/xen/arch/x86/hvm/vmx/vvmx.c
+++ b/xen/arch/x86/hvm/vmx/vvmx.c
@@ -1293,6 +1293,12 @@ static void sync_exception_state(struct vcpu *v)
nvmx->intr.error_code);
break;
case X86_EVENTTYPE_NMI:
+ __set_vvmcs(nvcpu->nv_vvmcx, VM_EXIT_REASON,
+ EXIT_REASON_EXCEPTION_NMI);
+ __set_vvmcs(nvcpu->nv_vvmcx, EXIT_QUALIFICATION, 0);
+ __set_vvmcs(nvcpu->nv_vvmcx, VM_EXIT_INTR_INFO,
+ nvmx->intr.intr_info);
+ break;
default:
gdprintk(XENLOG_ERR, "Exception state %lx not handled\n",
nvmx->intr.intr_info);
--
1.7.1
Egger, Christoph
2013-Dec-12 11:04 UTC
Re: [PATCH 1/3] Nested VMX: update nested paging mode when vmswitch is in progress
On 12.12.13 03:06, Yang Zhang wrote:> From: Yang Zhang <yang.z.zhang@Intel.com> > > virtual vmentry will change paging related stucture, so corrensponding > nested mode need to be updated which is missing currently. > > Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>I weakly remember the "!nestedhvm_vmswitch_in_progress" is needed to avoid a nested pagefault loop on AMD. I do not remember the actual reproduction case. Unfortunately, I do not have a setup to verify. Christoph> --- > xen/arch/x86/hvm/hvm.c | 4 ++-- > 1 files changed, 2 insertions(+), 2 deletions(-) > > This patch fixed RHEL6 guest installation problem with L1 hyper-v. > > diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c > index 69f7e74..1f62e00 100644 > --- a/xen/arch/x86/hvm/hvm.c > +++ b/xen/arch/x86/hvm/hvm.c > @@ -1925,7 +1925,7 @@ int hvm_set_cr0(unsigned long value) > hvm_update_cr(v, 0, value); > > if ( (value ^ old_value) & X86_CR0_PG ) { > - if ( !nestedhvm_vmswitch_in_progress(v) && nestedhvm_vcpu_in_guestmode(v) ) > + if ( nestedhvm_vcpu_in_guestmode(v) ) > paging_update_nestedmode(v); > else > paging_update_paging_modes(v); > @@ -2014,7 +2014,7 @@ int hvm_set_cr4(unsigned long value) > (X86_CR4_PSE | X86_CR4_PGE | X86_CR4_PAE | X86_CR4_SMEP)) || > (!(value & X86_CR4_PCIDE) && (old_cr & X86_CR4_PCIDE)) ) > { > - if ( !nestedhvm_vmswitch_in_progress(v) && nestedhvm_vcpu_in_guestmode(v) ) > + if ( nestedhvm_vcpu_in_guestmode(v) ) > paging_update_nestedmode(v); > else > paging_update_paging_modes(v); >
Zhang, Yang Z
2013-Dec-13 03:30 UTC
Re: [PATCH 1/3] Nested VMX: update nested paging mode when vmswitch is in progress
Egger, Christoph wrote on 2013-12-12:> On 12.12.13 03:06, Yang Zhang wrote: >> From: Yang Zhang <yang.z.zhang@Intel.com> >> >> virtual vmentry will change paging related stucture, so corrensponding >> nested mode need to be updated which is missing currently. >> >> Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com> > > I weakly remember the "!nestedhvm_vmswitch_in_progress" is needed > to avoid a nested pagefault loop on AMD. I do not remember the > actual reproduction case. Unfortunately, I do not have a setup > to verify.So you mean if CR0.PG bit is changed during vmentry, there is no need to update nested paging mode on AMD? Consider that, if the nested VCPU is scheduled from ETP to shadow and you don''t update the nested paging mode, then it will cause problem, and vice versa. Best regards, Yang