Andrew Cooper
2013-Aug-28 10:05 UTC
[PATCH] x86/boot: Use mov to cr0 in preference to lmsw
lmsw is for compability for 286 processors only, and any more modern
processors are recomended to use mov to cr0. Xen has never been capable of
booting on a 286, given its multiboot entry.
Furthermore, this avoids needless playing with the CD, NW and AM bits. These
do get explicitly chosen slightly later on boot.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
CC: Keir Fraser <keir@xen.org>
CC: Jan Beulich <JBeulich@suse.com>
---
xen/arch/x86/boot/trampoline.S | 12 ++++++------
xen/arch/x86/boot/wakeup.S | 5 +++--
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/xen/arch/x86/boot/trampoline.S b/xen/arch/x86/boot/trampoline.S
index f84ce2a..89e292a 100644
--- a/xen/arch/x86/boot/trampoline.S
+++ b/xen/arch/x86/boot/trampoline.S
@@ -28,9 +28,9 @@ trampoline_realmode_entry:
lidt bootsym(idt_48)
lgdt bootsym(gdt_48)
mov $1,%bl # EBX != 0 indicates we are an AP
- xor %ax, %ax
- inc %ax
- lmsw %ax # CR0.PE = 1 (enter protected mode)
+ mov %cr0,%eax
+ or $X86_CR0_PE,%al
+ mov %eax,%cr0 # CR0.PE = 1 (enter protected mode)
ljmpl $BOOT_CS32,$bootsym_rel(trampoline_protmode_entry,6)
idt_48: .word 0, 0, 0 # base = limit = 0
@@ -182,9 +182,9 @@ trampoline_boot_cpu_entry:
lgdt bootsym(gdt_48)
/* Enter protected mode, and flush insn queue. */
- xor %ax,%ax
- inc %ax
- lmsw %ax # CR0.PE = 1 (enter protected mode)
+ mov %cr0,%eax
+ or $X86_CR0_PE,%al
+ mov %eax,%cr0 # CR0.PE = 1 (enter protected mode)
/* Load proper protected-mode values into all segment registers. */
ljmpl $BOOT_CS32,$bootsym_rel(1f,6)
diff --git a/xen/arch/x86/boot/wakeup.S b/xen/arch/x86/boot/wakeup.S
index b1d4787..2b54219 100644
--- a/xen/arch/x86/boot/wakeup.S
+++ b/xen/arch/x86/boot/wakeup.S
@@ -46,8 +46,9 @@ ENTRY(wakeup_start)
lidt %fs:bootsym(idt_48)
lgdt %fs:bootsym(gdt_48)
- movw $1, %ax
- lmsw %ax # Turn on CR0.PE
+ mov %cr0,%eax
+ or $X86_CR0_PE,%al
+ mov %eax,%cr0 # Turn on CR0.PE
ljmpl $BOOT_CS32, $bootsym_rel(wakeup_32, 6)
/* This code uses an extended set of video mode numbers. These include:
--
1.7.10.4
Jan Beulich
2013-Aug-28 10:22 UTC
Re: [PATCH] x86/boot: Use mov to cr0 in preference to lmsw
>>> On 28.08.13 at 12:05, Andrew Cooper <andrew.cooper3@citrix.com> wrote: > lmsw is for compability for 286 processors only, and any more modern > processors are recomended to use mov to cr0. Xen has never been capable of > booting on a 286, given its multiboot entry.I don''t really mind this part (albeit it results in growth of the trampoline code), but ...> Furthermore, this avoids needless playing with the CD, NW and AM bits. > These do get explicitly chosen slightly later on boot.... I clearly don''t understand what you''re referring to here: These bits don''t get modified by LMSW. Jan
Andrew Cooper
2013-Aug-28 10:33 UTC
Re: [PATCH] x86/boot: Use mov to cr0 in preference to lmsw
On 28/08/13 11:22, Jan Beulich wrote:>>>> On 28.08.13 at 12:05, Andrew Cooper <andrew.cooper3@citrix.com> wrote: >> lmsw is for compability for 286 processors only, and any more modern >> processors are recomended to use mov to cr0. Xen has never been capable of >> booting on a 286, given its multiboot entry. > I don''t really mind this part (albeit it results in growth of the > trampoline code), but ... > >> Furthermore, this avoids needless playing with the CD, NW and AM bits. >> These do get explicitly chosen slightly later on boot. > ... I clearly don''t understand what you''re referring to here: These > bits don''t get modified by LMSW. > > Jan >D''oh - yes. I intended the MP, EM and TS bits. (I scanned the wrong direction through the written description of the cr0 bits). The I shall send v2 which corrects the description - it is a bit too misleading as it currently stands.
Andrew Cooper
2013-Aug-28 10:36 UTC
[Patch v2] x86/boot: Use mov to cr0 in preference to lmsw
lmsw is for compability for 286 processors only, and any more modern
processors are recomended to use mov to cr0. Xen has never been capable of
booting on a 286, given its multiboot entry.
Furthermore, this avoids needless playing with the MP, EM and TS bits. These
do get explicitly chosen slightly later on boot.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
CC: Keir Fraser <keir@xen.org>
CC: Jan Beulich <JBeulich@suse.com>
---
Correct description of affected bits. The sentiment was still correct.
---
xen/arch/x86/boot/trampoline.S | 12 ++++++------
xen/arch/x86/boot/wakeup.S | 5 +++--
2 files changed, 9 insertions(+), 8 deletions(-)
diff --git a/xen/arch/x86/boot/trampoline.S b/xen/arch/x86/boot/trampoline.S
index f84ce2a..89e292a 100644
--- a/xen/arch/x86/boot/trampoline.S
+++ b/xen/arch/x86/boot/trampoline.S
@@ -28,9 +28,9 @@ trampoline_realmode_entry:
lidt bootsym(idt_48)
lgdt bootsym(gdt_48)
mov $1,%bl # EBX != 0 indicates we are an AP
- xor %ax, %ax
- inc %ax
- lmsw %ax # CR0.PE = 1 (enter protected mode)
+ mov %cr0,%eax
+ or $X86_CR0_PE,%al
+ mov %eax,%cr0 # CR0.PE = 1 (enter protected mode)
ljmpl $BOOT_CS32,$bootsym_rel(trampoline_protmode_entry,6)
idt_48: .word 0, 0, 0 # base = limit = 0
@@ -182,9 +182,9 @@ trampoline_boot_cpu_entry:
lgdt bootsym(gdt_48)
/* Enter protected mode, and flush insn queue. */
- xor %ax,%ax
- inc %ax
- lmsw %ax # CR0.PE = 1 (enter protected mode)
+ mov %cr0,%eax
+ or $X86_CR0_PE,%al
+ mov %eax,%cr0 # CR0.PE = 1 (enter protected mode)
/* Load proper protected-mode values into all segment registers. */
ljmpl $BOOT_CS32,$bootsym_rel(1f,6)
diff --git a/xen/arch/x86/boot/wakeup.S b/xen/arch/x86/boot/wakeup.S
index b1d4787..2b54219 100644
--- a/xen/arch/x86/boot/wakeup.S
+++ b/xen/arch/x86/boot/wakeup.S
@@ -46,8 +46,9 @@ ENTRY(wakeup_start)
lidt %fs:bootsym(idt_48)
lgdt %fs:bootsym(gdt_48)
- movw $1, %ax
- lmsw %ax # Turn on CR0.PE
+ mov %cr0,%eax
+ or $X86_CR0_PE,%al
+ mov %eax,%cr0 # Turn on CR0.PE
ljmpl $BOOT_CS32, $bootsym_rel(wakeup_32, 6)
/* This code uses an extended set of video mode numbers. These include:
--
1.7.10.4
Keir Fraser
2013-Aug-28 12:54 UTC
Re: [Patch v2] x86/boot: Use mov to cr0 in preference to lmsw
On 28/08/2013 11:36, "Andrew Cooper" <andrew.cooper3@citrix.com> wrote:> lmsw is for compability for 286 processors only, and any more modern > processors are recomended to use mov to cr0. Xen has never been capable of > booting on a 286, given its multiboot entry. > > Furthermore, this avoids needless playing with the MP, EM and TS bits. These > do get explicitly chosen slightly later on boot. > > Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> > CC: Keir Fraser <keir@xen.org> > CC: Jan Beulich <JBeulich@suse.com>I don''t know. This seems quite pointless.