Chen Baozi
2013-Aug-07 14:18 UTC
[PATCH v3 0/5] Add UART support and arch timer initialization for OMAP5
Since OMAP UART has a few distinct features than common 8250 UART, I
re-implemented its driver rather than porting it based on ns16550.c.
There are mainly two big differences between the implementations. First,
OMAP UART introduces the concept of register access mode, which divides
the register map into seperated space. Switching the access mode is then
necessary when configuring it. Second, THRE interrupt needs to be disable
after finished transmission and enabled once transmission started. This
is because the semantic of THRE interrupt differs from common 8250 in
TI''s
implementation, which would be generated if TX FIFO below trigger level
and cannot be cleared by simply write to THR once.
Besides UART driver, arch timer initialization for OMAP5432 platform
is also done in this patch series.
v3 <- v2:
- [3/5] Use bool_t as the return type of dt_property_read_u32.
- [3/5] Use sizeof(*out_value) instead of hardcoded value in
dt_property_read_u32.
- [3/5] Fix some coding-style problems and some typos.
v2 <- v1:
- [2/5] Add early printk support for sun6i.
- [3/5] Introduce dt_property_read_u32() helper to get clock-frequency.
- [3/5] Use ioreadl/iowritel instead of uart->regs[...] in OMAP UART driver.
- [3/5] Change do-while structure to while in OMAP UART interrupt handler.
- [3/5] Use hardcoded value when setting up OMAP UART.
- [3/5] Won''t enable IRQ if setup failed in init_postirq().
- [3/5] Fix coding-style problems and some typos.
- [3/5] Remove unnecessary define.
- [4/5] Remove the macros that would be used in future.
- [5/5] Use dt_property_read_u32() helper to get clock-frequency.
- [5/5] Remove unused define.
Chen Baozi (5):
xen: rename ns16550-uart.h to 8250-uart.h and fix some typos
xen/arm: add 8250 compatible UART support for early_printk
xen/arm: Add the new OMAP UART driver.
xen/arm: Introduce platform recognition codes for the OMAP5
xen/arm: Add OMAP5 architected timer initialization codes.
config/arm32.mk | 1 +
docs/misc/arm/early-printk.txt | 2 +
xen/arch/arm/Rules.mk | 8 +
xen/arch/arm/arm32/debug-8250.inc | 41 +++
xen/arch/arm/platforms/Makefile | 1 +
xen/arch/arm/platforms/omap5.c | 113 ++++++++
xen/arch/arm/time.c | 7 +-
xen/common/device_tree.c | 15 +
xen/drivers/char/Makefile | 1 +
xen/drivers/char/ns16550.c | 2 +-
xen/drivers/char/omap-uart.c | 352 ++++++++++++++++++++++++
xen/include/asm-arm/platforms/omap5.h | 25 ++
xen/include/xen/{ns16550-uart.h => 8250-uart.h} | 80 +++++-
xen/include/xen/device_tree.h | 6 +
14 files changed, 640 insertions(+), 14 deletions(-)
create mode 100644 xen/arch/arm/arm32/debug-8250.inc
create mode 100644 xen/arch/arm/platforms/omap5.c
create mode 100644 xen/drivers/char/omap-uart.c
create mode 100644 xen/include/asm-arm/platforms/omap5.h
rename xen/include/xen/{ns16550-uart.h => 8250-uart.h} (60%)
--
1.8.1.4
Chen Baozi
2013-Aug-07 14:18 UTC
[PATCH v3 1/5] xen: rename ns16550-uart.h to 8250-uart.h and fix some typos
Since UARTs on OMAP5 & Allwinner''s SoC are not ns16550 but only
8250
compatible, rename ns16550-uart.h to 8250-uart.h, which is a more pervasive
name. At the same time, fix some typos, which have redundance UART_
prefixes in some macros.
Signed-off-by: Chen Baozi <baozich@gmail.com>
Acked-by: Julien Grall <julien.grall@linaro.org>
---
xen/drivers/char/ns16550.c | 2 +-
xen/include/xen/{ns16550-uart.h => 8250-uart.h} | 18 +++++++++---------
2 files changed, 10 insertions(+), 10 deletions(-)
rename xen/include/xen/{ns16550-uart.h => 8250-uart.h} (89%)
diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
index e085a64..6082c85 100644
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -19,7 +19,7 @@
#include <xen/iocap.h>
#include <xen/pci.h>
#include <xen/pci_regs.h>
-#include <xen/ns16550-uart.h>
+#include <xen/8250-uart.h>
#include <asm/io.h>
#ifdef CONFIG_X86
#include <asm/fixmap.h>
diff --git a/xen/include/xen/ns16550-uart.h b/xen/include/xen/8250-uart.h
similarity index 89%
rename from xen/include/xen/ns16550-uart.h
rename to xen/include/xen/8250-uart.h
index 232cef9..7287364 100644
--- a/xen/include/xen/ns16550-uart.h
+++ b/xen/include/xen/8250-uart.h
@@ -1,5 +1,5 @@
/*
- * xen/include/xen/ns16550-uart.h
+ * xen/include/xen/8250-uart.h
*
* This header is extracted from driver/char/ns16550.c
*
@@ -19,8 +19,8 @@
* GNU General Public License for more details.
*/
-#ifndef __XEN_NS16550_UART_H__
-#define __XEN_NS16550_UART_H__
+#ifndef __XEN_8250_UART_H__
+#define __XEN_8250_UART_H__
/* Register offsets */
#define UART_RBR 0x00 /* receive buffer */
@@ -43,11 +43,11 @@
/* Interrupt Identificatiegister */
#define UART_IIR_NOINT 0x01 /* no interrupt pending */
-#define UART_UART_IIR_IMA 0x06 /* interrupt identity: */
-#define UART_UART_IIR_LSI 0x06 /* - rx line status */
-#define UART_UART_IIR_RDA 0x04 /* - rx data recv''d */
-#define UART_UART_IIR_THR 0x02 /* - tx reg. empty */
-#define UART_UART_IIR_MSI 0x00 /* - MODEM status */
+#define UART_IIR_IMA 0x06 /* interrupt identity: */
+#define UART_IIR_LSI 0x06 /* - rx line status */
+#define UART_IIR_RDA 0x04 /* - rx data recv''d */
+#define UART_IIR_THR 0x02 /* - tx reg. empty */
+#define UART_IIR_MSI 0x00 /* - MODEM status */
/* FIFO Control Register */
#define UART_FCR_ENABLE 0x01 /* enable FIFO */
@@ -92,7 +92,7 @@
#define RESUME_DELAY MILLISECS(10)
#define RESUME_RETRIES 100
-#endif /* __XEN_NS16550_UART_H__ */
+#endif /* __XEN_8250_UART_H__ */
/*
* Local variables:
--
1.8.1.4
Chen Baozi
2013-Aug-07 14:18 UTC
[PATCH v3 2/5] xen/arm: add 8250 compatible UART support for early_printk
Both OMAP5 and sun6i SoCs share this UART driver for early_printk. Signed-off-by: Chen Baozi <baozich@gmail.com> --- docs/misc/arm/early-printk.txt | 2 ++ xen/arch/arm/Rules.mk | 8 ++++++++ xen/arch/arm/arm32/debug-8250.inc | 41 +++++++++++++++++++++++++++++++++++++++ xen/include/xen/8250-uart.h | 4 ++++ 4 files changed, 55 insertions(+) create mode 100644 xen/arch/arm/arm32/debug-8250.inc diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt index fbc3208..f24c6c0 100644 --- a/docs/misc/arm/early-printk.txt +++ b/docs/misc/arm/early-printk.txt @@ -13,6 +13,8 @@ where mach is the name of the machine: - exynos5250: printk with the second UART - midway: printk with the pl011 on Calxeda Midway processors - fastmodel: printk on ARM Fastmodel software emulators + - omap5432: printk with UART3 on TI OMAP5432 processors + - sun6i: printk with 8250 on Allwinner A31 processors The base address and baud rate is hardcoded in xen/arch/arm/Rules.mk, see there when adding support for new machines. diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk index a18e7fd..7f11e5c 100644 --- a/xen/arch/arm/Rules.mk +++ b/xen/arch/arm/Rules.mk @@ -64,6 +64,14 @@ EARLY_PRINTK_INC := pl011 EARLY_PRINTK_BAUD := 115200 EARLY_UART_BASE_ADDRESS := 0xfff36000 endif +ifeq ($(CONFIG_EARLY_PRINTK), omap5432) +EARLY_PRINTK_INC := 8250 +EARLY_UART_BASE_ADDRESS := 0x48020000 +endif +ifeq ($(CONFIG_EARLY_PRINTK), sun6i) +EARLY_PRINTK_INC := 8250 +EARLY_UART_BASE_ADDRESS := 0x01c28000 +endif ifneq ($(EARLY_PRINTK_INC),) EARLY_PRINTK := y diff --git a/xen/arch/arm/arm32/debug-8250.inc b/xen/arch/arm/arm32/debug-8250.inc new file mode 100644 index 0000000..c0f4803 --- /dev/null +++ b/xen/arch/arm/arm32/debug-8250.inc @@ -0,0 +1,41 @@ +/* + * xen/arch/arm/arm32/debug-8250.inc + * + * 8250 specific debug code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <xen/8250-uart.h> + +/* 8250 UART wait UART to be ready to transmit + * rb: register which contains the UART base address + * rc: scratch register */ +.macro early_uart_ready rb rc +1: + ldr \rc, [\rb, #(UART_LSR << REG_SHIFT)] /* Read LSR */ + tst \rc, #UART_LSR_THRE /* Check Xmit holding register flag */ + beq 1b /* Wait for the UART to be ready */ +.endm + +/* 8250 UART transmit character + * rb: register which contains the UART base address + * rt: register which contains the character to transmit */ +.macro early_uart_transmit rb rt + str \rt, [\rb, #UART_THR] /* Write Transmit buffer */ +.endm + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h index 7287364..33daa6d 100644 --- a/xen/include/xen/8250-uart.h +++ b/xen/include/xen/8250-uart.h @@ -22,6 +22,10 @@ #ifndef __XEN_8250_UART_H__ #define __XEN_8250_UART_H__ +#ifdef CONFIG_ARM +#define REG_SHIFT 2 +#endif + /* Register offsets */ #define UART_RBR 0x00 /* receive buffer */ #define UART_THR 0x00 /* transmit holding */ -- 1.8.1.4
TI OMAP UART introduces some features such as register access modes, which
makes its configuration and interrupt handling differs from 8250 compatible
UART. Thus, we seperate this driver from ns16550''s implementation.
Signed-off-by: Chen Baozi <baozich@gmail.com>
---
config/arm32.mk | 1 +
xen/common/device_tree.c | 15 ++
xen/drivers/char/Makefile | 1 +
xen/drivers/char/omap-uart.c | 352 ++++++++++++++++++++++++++++++++++++++++++
xen/include/xen/8250-uart.h | 58 ++++++-
xen/include/xen/device_tree.h | 6 +
6 files changed, 430 insertions(+), 3 deletions(-)
create mode 100644 xen/drivers/char/omap-uart.c
diff --git a/config/arm32.mk b/config/arm32.mk
index 8e21158..76e229d 100644
--- a/config/arm32.mk
+++ b/config/arm32.mk
@@ -11,6 +11,7 @@ CFLAGS += -marm
HAS_PL011 := y
HAS_EXYNOS4210 := y
+HAS_OMAP := y
# Use only if calling $(LD) directly.
LDFLAGS_DIRECT += -EL
diff --git a/xen/common/device_tree.c b/xen/common/device_tree.c
index 84d704d..a4701eb 100644
--- a/xen/common/device_tree.c
+++ b/xen/common/device_tree.c
@@ -574,6 +574,21 @@ const void *dt_get_property(const struct dt_device_node
*np,
return pp ? pp->value : NULL;
}
+bool_t dt_property_read_u32(const struct dt_device_node *np,
+ const char *name, u32 *out_value)
+{
+ u32 len;
+ const __be32 *val;
+
+ val = dt_get_property(np, name, &len);
+ if ( !val || len > sizeof(*out_value) )
+ return 0;
+
+ *out_value = be32_to_cpup(val);
+
+ return 1;
+}
+
bool_t dt_device_is_compatible(const struct dt_device_node *device,
const char *compat)
{
diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile
index 37543f0..911b788 100644
--- a/xen/drivers/char/Makefile
+++ b/xen/drivers/char/Makefile
@@ -2,6 +2,7 @@ obj-y += console.o
obj-$(HAS_NS16550) += ns16550.o
obj-$(HAS_PL011) += pl011.o
obj-$(HAS_EXYNOS4210) += exynos4210-uart.o
+obj-$(HAS_OMAP) += omap-uart.o
obj-$(HAS_EHCI) += ehci-dbgp.o
obj-$(CONFIG_ARM) += dt-uart.o
obj-y += serial.o
diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c
new file mode 100644
index 0000000..9c2e9a5
--- /dev/null
+++ b/xen/drivers/char/omap-uart.c
@@ -0,0 +1,352 @@
+/*
+ * omap-uart.c
+ * Based on drivers/char/ns16550.c
+ *
+ * Driver for OMAP-UART controller
+ *
+ * Copyright (C) 2013, Chen Baozi <baozich@gmail.com>
+ *
+ * Note: This driver is made separate from 16550-series UART driver as
+ * omap platform has some specific configurations
+ */
+
+#include <xen/config.h>
+#include <xen/console.h>
+#include <xen/serial.h>
+#include <xen/init.h>
+#include <xen/irq.h>
+#include <asm/early_printk.h>
+#include <xen/device_tree.h>
+#include <asm/device.h>
+#include <xen/errno.h>
+#include <xen/mm.h>
+#include <xen/vmap.h>
+#include <xen/8250-uart.h>
+
+#define omap_read(uart, off) ioreadl((uart)->regs +
(off<<REG_SHIFT))
+#define omap_write(uart, off, val) iowritel((uart)->regs +
(off<<REG_SHIFT), (val))
+
+static struct omap_uart {
+ u32 baud, clock_hz, data_bits, parity, stop_bits, fifo_size;
+ struct dt_irq irq;
+ void __iomem *regs;
+ struct irqaction irqaction;
+} omap_com = {0};
+
+static void omap_uart_interrupt(int irq, void *data, struct cpu_user_regs
*regs)
+{
+ struct serial_port *port = data;
+ struct omap_uart *uart = port->uart;
+ u32 lsr;
+
+ while ( !(omap_read(uart, UART_IIR) & UART_IIR_NOINT) )
+ {
+ lsr = omap_read(uart, UART_LSR) & 0xff;
+ if ( lsr & UART_LSR_THRE )
+ serial_tx_interrupt(port, regs);
+ if ( lsr & UART_LSR_DR )
+ serial_rx_interrupt(port, regs);
+
+ if ( port->txbufc == port->txbufp )
+ omap_write(uart, UART_IER, UART_IER_ERDAI|UART_IER_ELSI);
+ };
+}
+
+static void baud_protocol_setup(struct omap_uart *uart)
+{
+ u32 dll, dlh, efr;
+ unsigned int divisor;
+
+ divisor = uart->clock_hz / (uart->baud << 4);
+ dll = divisor & 0xff;
+ dlh = divisor >> 8;
+
+ /*
+ * Switch to register configuration mode B to access the UART_OMAP_EFR
+ * register.
+ */
+ omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_B);
+ /*
+ * Enable access to the UART_IER[7:4] bit field.
+ */
+ efr = omap_read(uart, UART_OMAP_EFR);
+ omap_write(uart, UART_OMAP_EFR, efr|UART_OMAP_EFR_ECB);
+ /*
+ * Switch to register operation mode to access the UART_IER register.
+ */
+ omap_write(uart, UART_LCR, 0);
+ /*
+ * Clear the UART_IER register (set the UART_IER[4] SLEEP_MODE bit
+ * to 0 to change the UART_DLL and UART_DLM register). Set the
+ * UART_IER register value to 0x0000.
+ */
+ omap_write(uart, UART_IER, 0);
+ /*
+ * Switch to register configuartion mode B to access the UART_DLL and
+ * UART_DLM registers.
+ */
+ omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_B);
+ /*
+ * Load divisor value.
+ */
+ omap_write(uart, UART_DLL, dll);
+ omap_write(uart, UART_DLM, dlh);
+ /*
+ * Restore the UART_OMAP_EFR
+ */
+ omap_write(uart, UART_OMAP_EFR, efr);
+ /*
+ * Load the new protocol formatting (parity, stop-bit, character length)
+ * and switch to register operational mode.
+ */
+ omap_write(uart, UART_LCR, (uart->data_bits - 5) |
+ ((uart->stop_bits - 1) << 2) | uart->parity);
+}
+
+static void fifo_setup(struct omap_uart *uart)
+{
+ u32 lcr, efr, mcr;
+ /*
+ * Switch to register configuration mode B to access the UART_OMAP_EFR
+ * register.
+ */
+ lcr = omap_read(uart, UART_LCR);
+ omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_B);
+ /*
+ * Enable register submode TCR_TLR to access the UART_OMAP_TLR register.
+ */
+ efr = omap_read(uart, UART_OMAP_EFR);
+ omap_write(uart, UART_OMAP_EFR, efr|UART_OMAP_EFR_ECB);
+ /*
+ * Switch to register configuration mode A to access the UART_MCR
+ * register.
+ */
+ omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_A);
+ /*
+ * Enable register submode TCR_TLR to access the UART_OMAP_TLR register
+ */
+ mcr = omap_read(uart, UART_MCR);
+ omap_write(uart, UART_MCR, mcr|UART_MCR_TCRTLR);
+ /*
+ * Enable the FIFO; load the new FIFO trigger and the new DMA mode.
+ */
+ omap_write(uart, UART_FCR, UART_FCR_R_TRIG_01|
+ UART_FCR_T_TRIG_10|UART_FCR_ENABLE);
+ /*
+ * Switch to register configuration mode B to access the UART_EFR
+ * register.
+ */
+ omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_B);
+ /*
+ * Load the new FIFO triggers and the new DMA mode bit.
+ */
+ omap_write(uart, UART_OMAP_SCR, OMAP_UART_SCR_RX_TRIG_GRANU1_MASK);
+ /*
+ * Restore the UART_OMAP_EFR[4] value.
+ */
+ omap_write(uart, UART_OMAP_EFR, efr);
+ /*
+ * Switch to register configuration mode A to access the UART_MCR
+ * register.
+ */
+ omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_A);
+ /*
+ * Restore UART_MCR[6] value.
+ */
+ omap_write(uart, UART_MCR, mcr);
+ /*
+ * Restore UART_LCR value.
+ */
+ omap_write(uart, UART_LCR, lcr);
+
+ uart->fifo_size = 64;
+}
+
+static void __init omap_uart_init_preirq(struct serial_port *port)
+{
+ struct omap_uart *uart = port->uart;
+
+ /*
+ * Clear the FIFO buffers.
+ */
+ omap_write(uart, UART_FCR, UART_FCR_ENABLE);
+ omap_write(uart, UART_FCR, UART_FCR_ENABLE|UART_FCR_CLRX|UART_FCR_CLTX);
+ omap_write(uart, UART_FCR, 0);
+
+ /*
+ * The TRM says the mode should be disabled while UART_DLL and UART_DHL
+ * are being changed so we disable before setup, then enable.
+ */
+ omap_write(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
+
+ /* Baud rate & protocol format setup */
+ baud_protocol_setup(uart);
+
+ /* FIFO setup */
+ fifo_setup(uart);
+
+ /* No flow control */
+ omap_write(uart, UART_MCR, UART_MCR_DTR|UART_MCR_RTS);
+
+ omap_write(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE);
+}
+
+static void __init omap_uart_init_postirq(struct serial_port *port)
+{
+ struct omap_uart *uart = port->uart;
+
+ uart->irqaction.handler = omap_uart_interrupt;
+ uart->irqaction.name = "omap_uart";
+ uart->irqaction.dev_id = port;
+
+ if ( setup_dt_irq(&uart->irq, &uart->irqaction) != 0 )
+ {
+ dprintk(XENLOG_ERR, "Failed to allocated omap_uart IRQ %d\n",
+ uart->irq.irq);
+ return;
+ }
+
+ /* Enable interrupts */
+ omap_write(uart, UART_IER, UART_IER_ERDAI|UART_IER_ETHREI|UART_IER_ELSI);
+}
+
+static void omap_uart_suspend(struct serial_port *port)
+{
+ BUG();
+}
+
+static void omap_uart_resume(struct serial_port *port)
+{
+ BUG();
+}
+
+static unsigned int omap_uart_tx_ready(struct serial_port *port)
+{
+ struct omap_uart *uart = port->uart;
+
+ omap_write(uart, UART_IER, UART_IER_ERDAI|UART_IER_ETHREI|UART_IER_ELSI);
+
+ return omap_read(uart, UART_LSR) & UART_LSR_THRE ? uart->fifo_size :
0;
+}
+
+static void omap_uart_putc(struct serial_port *port, char c)
+{
+ struct omap_uart *uart = port->uart;
+
+ omap_write(uart, UART_THR, (uint32_t)(unsigned char)c);
+}
+
+static int omap_uart_getc(struct serial_port *port, char *pc)
+{
+ struct omap_uart *uart = port->uart;
+
+ if ( !(omap_read(uart, UART_LSR) & UART_LSR_DR) )
+ return 0;
+
+ *pc = omap_read(uart, UART_RBR) & 0xff;
+ return 1;
+}
+
+static int __init omap_uart_irq(struct serial_port *port)
+{
+ struct omap_uart *uart = port->uart;
+
+ return ((uart->irq.irq > 0) ? uart->irq.irq : -1);
+}
+
+static const struct dt_irq __init *omap_uart_dt_irq(struct serial_port *port)
+{
+ struct omap_uart *uart = port->uart;
+
+ return &uart->irq;
+}
+
+static struct uart_driver __read_mostly omap_uart_driver = {
+ .init_preirq = omap_uart_init_preirq,
+ .init_postirq = omap_uart_init_postirq,
+ .endboot = NULL,
+ .suspend = omap_uart_suspend,
+ .resume = omap_uart_resume,
+ .tx_ready = omap_uart_tx_ready,
+ .putc = omap_uart_putc,
+ .getc = omap_uart_getc,
+ .irq = omap_uart_irq,
+ .dt_irq_get = omap_uart_dt_irq,
+};
+
+static int __init omap_uart_init(struct dt_device_node *dev,
+ const void *data)
+{
+ const char *config = data;
+ struct omap_uart *uart;
+ u32 clkspec;
+ int res;
+ u64 addr, size;
+
+ if ( strcmp(config, "") )
+ early_printk("WARNING: UART configuration is not
supported\n");
+
+ uart = &omap_com;
+
+ res = dt_property_read_u32(dev, "clock-frequency", &clkspec);
+ if ( !res )
+ {
+ early_printk("omap-uart: Unable to retrieve the clock
frequency\n");
+ return -EINVAL;
+ }
+
+ uart->clock_hz = clkspec;
+ uart->baud = 115200;
+ uart->data_bits = 8;
+ uart->parity = UART_PARITY_NONE;
+ uart->stop_bits = 1;
+
+ res = dt_device_get_address(dev, 0, &addr, &size);
+ if ( res )
+ {
+ early_printk("omap-uart: Unable to retrieve the base"
+ " address of the UART\n");
+ return res;
+ }
+
+ uart->regs = ioremap_attr(addr, size, PAGE_HYPERVISOR_NOCACHE);
+ if ( !uart->regs )
+ {
+ early_printk("omap-uart: Unable to map the UART memory\n");
+ return -ENOMEM;
+ }
+
+ res = dt_device_get_irq(dev, 0, &uart->irq);
+ if ( res )
+ {
+ early_printk("omap-uart: Unable to retrieve the IRQ\n");
+ return res;
+ }
+
+ /* Register with generic serial driver */
+ serial_register_uart(SERHND_DTUART, &omap_uart_driver, uart);
+
+ dt_device_set_used_by(dev, DOMID_XEN);
+
+ return 0;
+}
+
+static const char const *omap_uart_dt_compat[] __initdata +{
+ "ti,omap4-uart",
+ NULL
+};
+
+DT_DEVICE_START(omap_uart, "OMAP UART", DEVICE_SERIAL)
+ .compatible = omap_uart_dt_compat,
+ .init = omap_uart_init,
+DT_DEVICE_END
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h
index 33daa6d..697cac1 100644
--- a/xen/include/xen/8250-uart.h
+++ b/xen/include/xen/8250-uart.h
@@ -58,19 +58,51 @@
#define UART_FCR_CLRX 0x02 /* clear Rx FIFO */
#define UART_FCR_CLTX 0x04 /* clear Tx FIFO */
#define UART_FCR_DMA 0x10 /* enter DMA mode */
+
#define UART_FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */
#define UART_FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */
#define UART_FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */
#define UART_FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */
+/*
+ * Note: The FIFO trigger levels are chip specific:
+ * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
+ * PC16550D: 1 4 8 14 xx xx xx xx
+ * TI16C550A: 1 4 8 14 xx xx xx xx
+ * TI16C550C: 1 4 8 14 xx xx xx xx
+ * ST16C550: 1 4 8 14 xx xx xx xx
+ * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
+ * NS16C552: 1 4 8 14 xx xx xx xx
+ * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
+ * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
+ * TI16C752: 8 16 56 60 8 16 32 56
+ * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA
+ */
+#define UART_FCR_R_TRIG_00 0x00
+#define UART_FCR_R_TRIG_01 0x40
+#define UART_FCR_R_TRIG_10 0x80
+#define UART_FCR_R_TRIG_11 0xc0
+#define UART_FCR_T_TRIG_00 0x00
+#define UART_FCR_T_TRIG_01 0x10
+#define UART_FCR_T_TRIG_10 0x20
+#define UART_FCR_T_TRIG_11 0x30
+
/* Line Control Register */
#define UART_LCR_DLAB 0x80 /* Divisor Latch Access */
+/*
+ * Access to some registers depends on register access / configuration
+ * mode.
+ */
+#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configuration mode A */
+#define UART_LCR_CONF_MODE_B 0xBF /* Configuration mode B */
+
/* Modem Control Register */
-#define UART_MCR_DTR 0x01 /* Data Terminal Ready */
-#define UART_MCR_RTS 0x02 /* Request to Send */
-#define UART_MCR_OUT2 0x08 /* OUT2: interrupt mask */
+#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_OUT2 0x08 /* Out2 complement */
+#define UART_MCR_RTS 0x02 /* RTS complement */
+#define UART_MCR_DTR 0x01 /* DTR complement */
/* Line Status Register */
#define UART_LSR_DR 0x01 /* Data ready */
@@ -96,6 +128,26 @@
#define RESUME_DELAY MILLISECS(10)
#define RESUME_RETRIES 100
+/* Enhanced feature register */
+#define UART_OMAP_EFR 0x02
+
+#define UART_OMAP_EFR_ECB 0x10 /* Enhanced control bit */
+
+/* Mode definition register 1 */
+#define UART_OMAP_MDR1 0x08
+
+/*
+ * These are the definitions for the MDR1 register
+ */
+#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
+#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
+
+/* Supplementary control register */
+#define UART_OMAP_SCR 0x10
+
+/* SCR register bitmasks */
+#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
+
#endif /* __XEN_8250_UART_H__ */
/*
diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h
index 5a2a5c6..d4d2b29 100644
--- a/xen/include/xen/device_tree.h
+++ b/xen/include/xen/device_tree.h
@@ -300,6 +300,12 @@ const void *dt_get_property(const struct dt_device_node
*np,
const char *name, u32 *lenp);
/**
+ * dt_property_read_u32 - Helper to read a u32 property.
+ */
+bool_t dt_property_read_u32(const struct dt_device_node *np,
+ const char *name, u32 *out_value);
+
+/**
* Checks if the given "compat" string matches one of the strings in
* the device''s "compatible" property
*/
--
1.8.1.4
Chen Baozi
2013-Aug-07 14:18 UTC
[PATCH v3 4/5] xen/arm: Introduce platform recognition codes for the OMAP5
Signed-off-by: Chen Baozi <baozich@gmail.com>
---
xen/arch/arm/platforms/Makefile | 1 +
xen/arch/arm/platforms/omap5.c | 41 +++++++++++++++++++++++++++++++++++
xen/include/asm-arm/platforms/omap5.h | 13 +++++++++++
3 files changed, 55 insertions(+)
create mode 100644 xen/arch/arm/platforms/omap5.c
create mode 100644 xen/include/asm-arm/platforms/omap5.h
diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile
index ff2b65b..90ddcb1 100644
--- a/xen/arch/arm/platforms/Makefile
+++ b/xen/arch/arm/platforms/Makefile
@@ -1,2 +1,3 @@
obj-y += vexpress.o
obj-y += exynos5.o
+obj-y += omap5.o
diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c
new file mode 100644
index 0000000..084e211
--- /dev/null
+++ b/xen/arch/arm/platforms/omap5.c
@@ -0,0 +1,41 @@
+/*
+ * xen/arch/arm/platforma/omap5.c
+ *
+ * OMAP5 specific settings
+ *
+ * Chen Baozi <baozich@gmail.com>
+ * Copyright (c) 2013
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributted in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Gerneral Public License for more details.
+ */
+
+#include <xen/config.h>
+#include <asm/platform.h>
+#include <asm/platforms/omap5.h>
+
+static const char const *omap5_dt_compat[] __initdata +{
+ "ti,omap5",
+ NULL
+};
+
+PLATFORM_START(omap5, "TI OMAP5")
+ .compatible = omap5_dt_compat,
+PLATFORM_END
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/platforms/omap5.h
b/xen/include/asm-arm/platforms/omap5.h
new file mode 100644
index 0000000..ff07d95
--- /dev/null
+++ b/xen/include/asm-arm/platforms/omap5.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_ARM_PLATFORMS_OMAP5_H
+#define __ASM_ASM_PLATFORMS_OMAP5_H
+
+#endif /* __ASM_ARM_PLATFORMS_OMAP5_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
1.8.1.4
Chen Baozi
2013-Aug-07 14:18 UTC
[PATCH v3 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
Signed-off-by: Chen Baozi <baozich@gmail.com>
---
xen/arch/arm/platforms/omap5.c | 72 +++++++++++++++++++++++++++++++++++
xen/arch/arm/time.c | 7 +++-
xen/include/asm-arm/platforms/omap5.h | 12 ++++++
3 files changed, 90 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c
index 084e211..4791366 100644
--- a/xen/arch/arm/platforms/omap5.c
+++ b/xen/arch/arm/platforms/omap5.c
@@ -20,6 +20,77 @@
#include <xen/config.h>
#include <asm/platform.h>
#include <asm/platforms/omap5.h>
+#include <xen/mm.h>
+#include <xen/vmap.h>
+
+static uint16_t num_den[8][2] = {
+ { 0, 0 }, /* not used */
+ { 26 * 64, 26 * 125 }, /* 12.0 Mhz */
+ { 2 * 768, 2 * 1625 }, /* 13.0 Mhz */
+ { 0, 0 }, /* not used */
+ { 130 * 8, 130 * 25 }, /* 19.2 Mhz */
+ { 2 * 384, 2 * 1625 }, /* 26.0 Mhz */
+ { 3 * 256, 3 * 1125 }, /* 27.0 Mhz */
+ { 130 * 4, 130 * 25 }, /* 38.4 Mhz */
+};
+
+/*
+ * The realtime counter also called master counter, is a free-running
+ * counter, which is related to real time. It produces the count used
+ * by the CPU local timer peripherals in teh MPU cluster. The timer counts
+ * at a rate of 6.144 MHz. Because the device operates on different clocks
+ * in different power modes, the master counter shifts operation between
+ * clocks, adjusting the increment per clock in hardware accordingly to
+ * maintain a constant count rate.
+ */
+static int omap5_init_time(void)
+{
+ void __iomem *ckgen_prm_base;
+ void __iomem *rt_ct_base;
+ unsigned int sys_clksel;
+ unsigned int num, den, frac1, frac2;
+
+ ckgen_prm_base = ioremap_attr(OMAP5_CKGEN_PRM_BASE,
+ 0x20, PAGE_HYPERVISOR_NOCACHE);
+ if (!ckgen_prm_base) {
+ dprintk(XENLOG_ERR, "%s: PRM_BASE ioremap failed\n",
__func__);
+ return -ENOMEM;
+ }
+
+ sys_clksel = ioreadl(ckgen_prm_base + OMAP5_CM_CLKSEL_SYS) &
+ ~SYS_CLKSEL_MASK;
+
+ iounmap(ckgen_prm_base);
+
+ rt_ct_base = ioremap_attr(REALTIME_COUNTER_BASE,
+ 0x20, PAGE_HYPERVISOR_NOCACHE);
+ if (!rt_ct_base) {
+ dprintk(XENLOG_ERR, "%s: REALTIME_COUNTER_BASE ioremap
failed\n", __func__);
+ return -ENOMEM;
+ }
+
+ frac1 = ioreadl(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET);
+ num = frac1 & ~NUMERATOR_DENUMERATOR_MASK;
+ if (num_den[sys_clksel][0] != num) {
+ frac1 &= NUMERATOR_DENUMERATOR_MASK;
+ frac1 |= num_den[sys_clksel][0];
+ }
+
+ frac2 = ioreadl(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+ den = frac2 & ~NUMERATOR_DENUMERATOR_MASK;
+ if (num_den[sys_clksel][1] != num) {
+ frac2 &= NUMERATOR_DENUMERATOR_MASK;
+ frac2 |= num_den[sys_clksel][1];
+ }
+
+ iowritel(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET, frac1);
+ iowritel(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET,
+ frac2 | PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD);
+
+ iounmap(rt_ct_base);
+
+ return 0;
+}
static const char const *omap5_dt_compat[] __initdata {
@@ -29,6 +100,7 @@ static const char const *omap5_dt_compat[] __initdata
PLATFORM_START(omap5, "TI OMAP5")
.compatible = omap5_dt_compat,
+ .init_time = omap5_init_time,
PLATFORM_END
/*
diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c
index 4ed7882..104aefc 100644
--- a/xen/arch/arm/time.c
+++ b/xen/arch/arm/time.c
@@ -104,6 +104,7 @@ int __init init_xen_time(void)
struct dt_device_node *dev;
int res;
unsigned int i;
+ u32 rate;
dev = dt_find_compatible_node(NULL, NULL, "arm,armv7-timer");
if ( !dev )
@@ -134,7 +135,11 @@ int __init init_xen_time(void)
if ( !cpu_has_gentimer )
panic("CPU does not support the Generic Timer v1
interface.\n");
- cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000;
+ res = dt_property_read_u32(dev, "clock-frequency", &rate);
+ if ( res )
+ cpu_khz = rate / 1000;
+ else
+ cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000;
boot_count = READ_SYSREG64(CNTPCT_EL0);
printk("Using generic timer at %lu KHz\n", cpu_khz);
diff --git a/xen/include/asm-arm/platforms/omap5.h
b/xen/include/asm-arm/platforms/omap5.h
index ff07d95..c657bae 100644
--- a/xen/include/asm-arm/platforms/omap5.h
+++ b/xen/include/asm-arm/platforms/omap5.h
@@ -1,6 +1,18 @@
#ifndef __ASM_ARM_PLATFORMS_OMAP5_H
#define __ASM_ASM_PLATFORMS_OMAP5_H
+#define REALTIME_COUNTER_BASE 0x48243200
+#define INCREMENTER_NUMERATOR_OFFSET 0x10
+#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
+#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
+#define PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD 0x00010000
+
+#define OMAP5_L4_WKUP 0x4AE00000
+#define OMAP5_PRM_BASE (OMAP5_L4_WKUP + 0x6000)
+#define OMAP5_CKGEN_PRM_BASE (OMAP5_PRM_BASE + 0x100)
+#define OMAP5_CM_CLKSEL_SYS 0x10
+#define SYS_CLKSEL_MASK 0xfffffff8
+
#endif /* __ASM_ARM_PLATFORMS_OMAP5_H */
/*
--
1.8.1.4
Keir Fraser
2013-Aug-07 16:53 UTC
Re: [PATCH v3 1/5] xen: rename ns16550-uart.h to 8250-uart.h and fix some typos
On 07/08/2013 15:18, "Chen Baozi" <baozich@gmail.com> wrote:> Since UARTs on OMAP5 & Allwinner''s SoC are not ns16550 but only 8250 > compatible, rename ns16550-uart.h to 8250-uart.h, which is a more pervasive > name. At the same time, fix some typos, which have redundance UART_ > prefixes in some macros. > > Signed-off-by: Chen Baozi <baozich@gmail.com> > Acked-by: Julien Grall <julien.grall@linaro.org>Acked-by: Keir Fraser <keir@xen.org>
Julien Grall
2013-Aug-07 16:59 UTC
Re: [PATCH v3 4/5] xen/arm: Introduce platform recognition codes for the OMAP5
This patch contains nearly nothing. I think you can merge with patch #5. On 08/07/2013 03:18 PM, Chen Baozi wrote:> Signed-off-by: Chen Baozi <baozich@gmail.com> > --- > xen/arch/arm/platforms/Makefile | 1 + > xen/arch/arm/platforms/omap5.c | 41 +++++++++++++++++++++++++++++++++++ > xen/include/asm-arm/platforms/omap5.h | 13 +++++++++++ > 3 files changed, 55 insertions(+) > create mode 100644 xen/arch/arm/platforms/omap5.c > create mode 100644 xen/include/asm-arm/platforms/omap5.h > > diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile > index ff2b65b..90ddcb1 100644 > --- a/xen/arch/arm/platforms/Makefile > +++ b/xen/arch/arm/platforms/Makefile > @@ -1,2 +1,3 @@ > obj-y += vexpress.o > obj-y += exynos5.o > +obj-y += omap5.o > diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c > new file mode 100644 > index 0000000..084e211 > --- /dev/null > +++ b/xen/arch/arm/platforms/omap5.c > @@ -0,0 +1,41 @@ > +/* > + * xen/arch/arm/platforma/omap5.c > + * > + * OMAP5 specific settings > + * > + * Chen Baozi <baozich@gmail.com> > + * Copyright (c) 2013 > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributted in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU Gerneral Public License for more details. > + */ > + > +#include <xen/config.h> > +#include <asm/platform.h> > +#include <asm/platforms/omap5.h> > + > +static const char const *omap5_dt_compat[] __initdata > +{ > + "ti,omap5", > + NULL > +}; > + > +PLATFORM_START(omap5, "TI OMAP5") > + .compatible = omap5_dt_compat, > +PLATFORM_END > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/include/asm-arm/platforms/omap5.h b/xen/include/asm-arm/platforms/omap5.h > new file mode 100644 > index 0000000..ff07d95 > --- /dev/null > +++ b/xen/include/asm-arm/platforms/omap5.h > @@ -0,0 +1,13 @@ > +#ifndef __ASM_ARM_PLATFORMS_OMAP5_H > +#define __ASM_ASM_PLATFORMS_OMAP5_H > + > +#endif /* __ASM_ARM_PLATFORMS_OMAP5_H */ > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ >Cheers, -- Julien
Julien Grall
2013-Aug-07 17:05 UTC
Re: [PATCH v3 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
On 08/07/2013 03:18 PM, Chen Baozi wrote:> Signed-off-by: Chen Baozi <baozich@gmail.com> > --- > xen/arch/arm/platforms/omap5.c | 72 +++++++++++++++++++++++++++++++++++ > xen/arch/arm/time.c | 7 +++- > xen/include/asm-arm/platforms/omap5.h | 12 ++++++ > 3 files changed, 90 insertions(+), 1 deletion(-) > > diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c > index 084e211..4791366 100644 > --- a/xen/arch/arm/platforms/omap5.c > +++ b/xen/arch/arm/platforms/omap5.c > @@ -20,6 +20,77 @@ > #include <xen/config.h> > #include <asm/platform.h> > #include <asm/platforms/omap5.h> > +#include <xen/mm.h> > +#include <xen/vmap.h> > + > +static uint16_t num_den[8][2] = { > + { 0, 0 }, /* not used */ > + { 26 * 64, 26 * 125 }, /* 12.0 Mhz */ > + { 2 * 768, 2 * 1625 }, /* 13.0 Mhz */ > + { 0, 0 }, /* not used */ > + { 130 * 8, 130 * 25 }, /* 19.2 Mhz */ > + { 2 * 384, 2 * 1625 }, /* 26.0 Mhz */ > + { 3 * 256, 3 * 1125 }, /* 27.0 Mhz */ > + { 130 * 4, 130 * 25 }, /* 38.4 Mhz */ > +}; > + > +/* > + * The realtime counter also called master counter, is a free-running > + * counter, which is related to real time. It produces the count used > + * by the CPU local timer peripherals in teh MPU cluster. The timer counts > + * at a rate of 6.144 MHz. Because the device operates on different clocks > + * in different power modes, the master counter shifts operation between > + * clocks, adjusting the increment per clock in hardware accordingly to > + * maintain a constant count rate. > + */ > +static int omap5_init_time(void) > +{ > + void __iomem *ckgen_prm_base; > + void __iomem *rt_ct_base; > + unsigned int sys_clksel; > + unsigned int num, den, frac1, frac2; > + > + ckgen_prm_base = ioremap_attr(OMAP5_CKGEN_PRM_BASE, > + 0x20, PAGE_HYPERVISOR_NOCACHE); > + if (!ckgen_prm_base) {Coding style. if ( .. ) {> + dprintk(XENLOG_ERR, "%s: PRM_BASE ioremap failed\n", __func__); > + return -ENOMEM; > + } > + > + sys_clksel = ioreadl(ckgen_prm_base + OMAP5_CM_CLKSEL_SYS) & > + ~SYS_CLKSEL_MASK; > + > + iounmap(ckgen_prm_base); > + > + rt_ct_base = ioremap_attr(REALTIME_COUNTER_BASE, > + 0x20, PAGE_HYPERVISOR_NOCACHE); > + if (!rt_ct_base) {Same here.> + dprintk(XENLOG_ERR, "%s: REALTIME_COUNTER_BASE ioremap failed\n", __func__); > + return -ENOMEM; > + } > + > + frac1 = ioreadl(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET); > + num = frac1 & ~NUMERATOR_DENUMERATOR_MASK; > + if (num_den[sys_clksel][0] != num) {Same here.> + frac1 &= NUMERATOR_DENUMERATOR_MASK; > + frac1 |= num_den[sys_clksel][0]; > + } > + > + frac2 = ioreadl(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); > + den = frac2 & ~NUMERATOR_DENUMERATOR_MASK; > + if (num_den[sys_clksel][1] != num) {Same here.> + frac2 &= NUMERATOR_DENUMERATOR_MASK; > + frac2 |= num_den[sys_clksel][1]; > + } > + > + iowritel(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET, frac1); > + iowritel(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET, > + frac2 | PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD); > + > + iounmap(rt_ct_base); > + > + return 0; > +} > > static const char const *omap5_dt_compat[] __initdata > { > @@ -29,6 +100,7 @@ static const char const *omap5_dt_compat[] __initdata > > PLATFORM_START(omap5, "TI OMAP5") > .compatible = omap5_dt_compat, > + .init_time = omap5_init_time, > PLATFORM_END > > /* > diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c > index 4ed7882..104aefc 100644 > --- a/xen/arch/arm/time.c > +++ b/xen/arch/arm/time.c > @@ -104,6 +104,7 @@ int __init init_xen_time(void) > struct dt_device_node *dev; > int res; > unsigned int i; > + u32 rate; > > dev = dt_find_compatible_node(NULL, NULL, "arm,armv7-timer"); > if ( !dev ) > @@ -134,7 +135,11 @@ int __init init_xen_time(void) > if ( !cpu_has_gentimer ) > panic("CPU does not support the Generic Timer v1 interface.\n"); > > - cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; > + res = dt_property_read_u32(dev, "clock-frequency", &rate); > + if ( res ) > + cpu_khz = rate / 1000; > + else > + cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; > > boot_count = READ_SYSREG64(CNTPCT_EL0); > printk("Using generic timer at %lu KHz\n", cpu_khz); > diff --git a/xen/include/asm-arm/platforms/omap5.h b/xen/include/asm-arm/platforms/omap5.h > index ff07d95..c657bae 100644 > --- a/xen/include/asm-arm/platforms/omap5.h > +++ b/xen/include/asm-arm/platforms/omap5.h > @@ -1,6 +1,18 @@ > #ifndef __ASM_ARM_PLATFORMS_OMAP5_H > #define __ASM_ASM_PLATFORMS_OMAP5_H > > +#define REALTIME_COUNTER_BASE 0x48243200 > +#define INCREMENTER_NUMERATOR_OFFSET 0x10 > +#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 > +#define NUMERATOR_DENUMERATOR_MASK 0xfffff000 > +#define PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD 0x00010000 > + > +#define OMAP5_L4_WKUP 0x4AE00000 > +#define OMAP5_PRM_BASE (OMAP5_L4_WKUP + 0x6000) > +#define OMAP5_CKGEN_PRM_BASE (OMAP5_PRM_BASE + 0x100) > +#define OMAP5_CM_CLKSEL_SYS 0x10 > +#define SYS_CLKSEL_MASK 0xfffffff8 > + > #endif /* __ASM_ARM_PLATFORMS_OMAP5_H */ > > /* >-- Julien Grall
Julien Grall
2013-Aug-07 17:12 UTC
Re: [PATCH v3 3/5] xen/arm: Add the new OMAP UART driver.
On 08/07/2013 03:18 PM, Chen Baozi wrote:> TI OMAP UART introduces some features such as register access modes, which > makes its configuration and interrupt handling differs from 8250 compatible > UART. Thus, we seperate this driver from ns16550''s implementation. > > Signed-off-by: Chen Baozi <baozich@gmail.com> > --- > config/arm32.mk | 1 + > xen/common/device_tree.c | 15 ++ > xen/drivers/char/Makefile | 1 + > xen/drivers/char/omap-uart.c | 352 ++++++++++++++++++++++++++++++++++++++++++ > xen/include/xen/8250-uart.h | 58 ++++++- > xen/include/xen/device_tree.h | 6 + > 6 files changed, 430 insertions(+), 3 deletions(-) > create mode 100644 xen/drivers/char/omap-uart.c > > diff --git a/config/arm32.mk b/config/arm32.mk > index 8e21158..76e229d 100644 > --- a/config/arm32.mk > +++ b/config/arm32.mk > @@ -11,6 +11,7 @@ CFLAGS += -marm > > HAS_PL011 := y > HAS_EXYNOS4210 := y > +HAS_OMAP := y > > # Use only if calling $(LD) directly. > LDFLAGS_DIRECT += -EL > diff --git a/xen/common/device_tree.c b/xen/common/device_tree.c > index 84d704d..a4701eb 100644 > --- a/xen/common/device_tree.c > +++ b/xen/common/device_tree.c > @@ -574,6 +574,21 @@ const void *dt_get_property(const struct dt_device_node *np, > return pp ? pp->value : NULL; > } > > +bool_t dt_property_read_u32(const struct dt_device_node *np, > + const char *name, u32 *out_value) > +{ > + u32 len; > + const __be32 *val; > + > + val = dt_get_property(np, name, &len); > + if ( !val || len > sizeof(*out_value) ) > + return 0; > + > + *out_value = be32_to_cpup(val); > + > + return 1; > +} > + > bool_t dt_device_is_compatible(const struct dt_device_node *device, > const char *compat) > { > diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile > index 37543f0..911b788 100644 > --- a/xen/drivers/char/Makefile > +++ b/xen/drivers/char/Makefile > @@ -2,6 +2,7 @@ obj-y += console.o > obj-$(HAS_NS16550) += ns16550.o > obj-$(HAS_PL011) += pl011.o > obj-$(HAS_EXYNOS4210) += exynos4210-uart.o > +obj-$(HAS_OMAP) += omap-uart.o > obj-$(HAS_EHCI) += ehci-dbgp.o > obj-$(CONFIG_ARM) += dt-uart.o > obj-y += serial.o > diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c > new file mode 100644 > index 0000000..9c2e9a5 > --- /dev/null > +++ b/xen/drivers/char/omap-uart.c > @@ -0,0 +1,352 @@ > +/* > + * omap-uart.c > + * Based on drivers/char/ns16550.c > + * > + * Driver for OMAP-UART controller > + * > + * Copyright (C) 2013, Chen Baozi <baozich@gmail.com> > + * > + * Note: This driver is made separate from 16550-series UART driver as > + * omap platform has some specific configurations > + */ > + > +#include <xen/config.h> > +#include <xen/console.h> > +#include <xen/serial.h> > +#include <xen/init.h> > +#include <xen/irq.h> > +#include <asm/early_printk.h> > +#include <xen/device_tree.h> > +#include <asm/device.h> > +#include <xen/errno.h> > +#include <xen/mm.h> > +#include <xen/vmap.h> > +#include <xen/8250-uart.h> > + > +#define omap_read(uart, off) ioreadl((uart)->regs + (off<<REG_SHIFT)) > +#define omap_write(uart, off, val) iowritel((uart)->regs + (off<<REG_SHIFT), (val)) > + > +static struct omap_uart { > + u32 baud, clock_hz, data_bits, parity, stop_bits, fifo_size; > + struct dt_irq irq; > + void __iomem *regs; > + struct irqaction irqaction; > +} omap_com = {0}; > + > +static void omap_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs) > +{ > + struct serial_port *port = data; > + struct omap_uart *uart = port->uart; > + u32 lsr; > + > + while ( !(omap_read(uart, UART_IIR) & UART_IIR_NOINT) ) > + { > + lsr = omap_read(uart, UART_LSR) & 0xff; > + if ( lsr & UART_LSR_THRE ) > + serial_tx_interrupt(port, regs); > + if ( lsr & UART_LSR_DR ) > + serial_rx_interrupt(port, regs); > + > + if ( port->txbufc == port->txbufp ) > + omap_write(uart, UART_IER, UART_IER_ERDAI|UART_IER_ELSI); > + }; > +} > + > +static void baud_protocol_setup(struct omap_uart *uart) > +{ > + u32 dll, dlh, efr; > + unsigned int divisor; > + > + divisor = uart->clock_hz / (uart->baud << 4); > + dll = divisor & 0xff; > + dlh = divisor >> 8; > + > + /* > + * Switch to register configuration mode B to access the UART_OMAP_EFR > + * register. > + */ > + omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_B); > + /* > + * Enable access to the UART_IER[7:4] bit field. > + */ > + efr = omap_read(uart, UART_OMAP_EFR); > + omap_write(uart, UART_OMAP_EFR, efr|UART_OMAP_EFR_ECB); > + /* > + * Switch to register operation mode to access the UART_IER register. > + */ > + omap_write(uart, UART_LCR, 0); > + /* > + * Clear the UART_IER register (set the UART_IER[4] SLEEP_MODE bit > + * to 0 to change the UART_DLL and UART_DLM register). Set the > + * UART_IER register value to 0x0000. > + */ > + omap_write(uart, UART_IER, 0); > + /* > + * Switch to register configuartion mode B to access the UART_DLL and > + * UART_DLM registers. > + */ > + omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_B); > + /* > + * Load divisor value. > + */ > + omap_write(uart, UART_DLL, dll); > + omap_write(uart, UART_DLM, dlh); > + /* > + * Restore the UART_OMAP_EFR > + */ > + omap_write(uart, UART_OMAP_EFR, efr); > + /* > + * Load the new protocol formatting (parity, stop-bit, character length) > + * and switch to register operational mode. > + */ > + omap_write(uart, UART_LCR, (uart->data_bits - 5) | > + ((uart->stop_bits - 1) << 2) | uart->parity); > +} > + > +static void fifo_setup(struct omap_uart *uart) > +{ > + u32 lcr, efr, mcr; > + /* > + * Switch to register configuration mode B to access the UART_OMAP_EFR > + * register. > + */ > + lcr = omap_read(uart, UART_LCR); > + omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_B); > + /* > + * Enable register submode TCR_TLR to access the UART_OMAP_TLR register. > + */ > + efr = omap_read(uart, UART_OMAP_EFR); > + omap_write(uart, UART_OMAP_EFR, efr|UART_OMAP_EFR_ECB); > + /* > + * Switch to register configuration mode A to access the UART_MCR > + * register. > + */ > + omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_A); > + /* > + * Enable register submode TCR_TLR to access the UART_OMAP_TLR register > + */ > + mcr = omap_read(uart, UART_MCR); > + omap_write(uart, UART_MCR, mcr|UART_MCR_TCRTLR); > + /* > + * Enable the FIFO; load the new FIFO trigger and the new DMA mode. > + */ > + omap_write(uart, UART_FCR, UART_FCR_R_TRIG_01| > + UART_FCR_T_TRIG_10|UART_FCR_ENABLE); > + /* > + * Switch to register configuration mode B to access the UART_EFR > + * register. > + */ > + omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_B); > + /* > + * Load the new FIFO triggers and the new DMA mode bit. > + */ > + omap_write(uart, UART_OMAP_SCR, OMAP_UART_SCR_RX_TRIG_GRANU1_MASK); > + /* > + * Restore the UART_OMAP_EFR[4] value. > + */ > + omap_write(uart, UART_OMAP_EFR, efr); > + /* > + * Switch to register configuration mode A to access the UART_MCR > + * register. > + */ > + omap_write(uart, UART_LCR, UART_LCR_CONF_MODE_A); > + /* > + * Restore UART_MCR[6] value. > + */ > + omap_write(uart, UART_MCR, mcr); > + /* > + * Restore UART_LCR value. > + */ > + omap_write(uart, UART_LCR, lcr); > + > + uart->fifo_size = 64; > +} > + > +static void __init omap_uart_init_preirq(struct serial_port *port) > +{ > + struct omap_uart *uart = port->uart; > + > + /* > + * Clear the FIFO buffers. > + */ > + omap_write(uart, UART_FCR, UART_FCR_ENABLE); > + omap_write(uart, UART_FCR, UART_FCR_ENABLE|UART_FCR_CLRX|UART_FCR_CLTX); > + omap_write(uart, UART_FCR, 0); > + > + /* > + * The TRM says the mode should be disabled while UART_DLL and UART_DHL > + * are being changed so we disable before setup, then enable. > + */ > + omap_write(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE); > + > + /* Baud rate & protocol format setup */ > + baud_protocol_setup(uart); > + > + /* FIFO setup */ > + fifo_setup(uart); > + > + /* No flow control */ > + omap_write(uart, UART_MCR, UART_MCR_DTR|UART_MCR_RTS); > + > + omap_write(uart, UART_OMAP_MDR1, UART_OMAP_MDR1_16X_MODE); > +} > + > +static void __init omap_uart_init_postirq(struct serial_port *port) > +{ > + struct omap_uart *uart = port->uart; > + > + uart->irqaction.handler = omap_uart_interrupt; > + uart->irqaction.name = "omap_uart"; > + uart->irqaction.dev_id = port; > + > + if ( setup_dt_irq(&uart->irq, &uart->irqaction) != 0 ) > + { > + dprintk(XENLOG_ERR, "Failed to allocated omap_uart IRQ %d\n", > + uart->irq.irq); > + return; > + } > + > + /* Enable interrupts */ > + omap_write(uart, UART_IER, UART_IER_ERDAI|UART_IER_ETHREI|UART_IER_ELSI); > +} > + > +static void omap_uart_suspend(struct serial_port *port) > +{ > + BUG(); > +} > + > +static void omap_uart_resume(struct serial_port *port) > +{ > + BUG(); > +} > + > +static unsigned int omap_uart_tx_ready(struct serial_port *port) > +{ > + struct omap_uart *uart = port->uart; > + > + omap_write(uart, UART_IER, UART_IER_ERDAI|UART_IER_ETHREI|UART_IER_ELSI); > + > + return omap_read(uart, UART_LSR) & UART_LSR_THRE ? uart->fifo_size : 0; > +} > + > +static void omap_uart_putc(struct serial_port *port, char c) > +{ > + struct omap_uart *uart = port->uart; > + > + omap_write(uart, UART_THR, (uint32_t)(unsigned char)c); > +} > + > +static int omap_uart_getc(struct serial_port *port, char *pc) > +{ > + struct omap_uart *uart = port->uart; > + > + if ( !(omap_read(uart, UART_LSR) & UART_LSR_DR) ) > + return 0; > + > + *pc = omap_read(uart, UART_RBR) & 0xff; > + return 1; > +} > + > +static int __init omap_uart_irq(struct serial_port *port) > +{ > + struct omap_uart *uart = port->uart; > + > + return ((uart->irq.irq > 0) ? uart->irq.irq : -1); > +} > + > +static const struct dt_irq __init *omap_uart_dt_irq(struct serial_port *port) > +{ > + struct omap_uart *uart = port->uart; > + > + return &uart->irq; > +} > + > +static struct uart_driver __read_mostly omap_uart_driver = { > + .init_preirq = omap_uart_init_preirq, > + .init_postirq = omap_uart_init_postirq, > + .endboot = NULL, > + .suspend = omap_uart_suspend, > + .resume = omap_uart_resume, > + .tx_ready = omap_uart_tx_ready, > + .putc = omap_uart_putc, > + .getc = omap_uart_getc, > + .irq = omap_uart_irq, > + .dt_irq_get = omap_uart_dt_irq, > +}; > + > +static int __init omap_uart_init(struct dt_device_node *dev, > + const void *data) > +{ > + const char *config = data; > + struct omap_uart *uart; > + u32 clkspec; > + int res; > + u64 addr, size; > + > + if ( strcmp(config, "") ) > + early_printk("WARNING: UART configuration is not supported\n"); > + > + uart = &omap_com; > + > + res = dt_property_read_u32(dev, "clock-frequency", &clkspec); > + if ( !res ) > + { > + early_printk("omap-uart: Unable to retrieve the clock frequency\n"); > + return -EINVAL; > + } > + > + uart->clock_hz = clkspec; > + uart->baud = 115200; > + uart->data_bits = 8; > + uart->parity = UART_PARITY_NONE; > + uart->stop_bits = 1; > + > + res = dt_device_get_address(dev, 0, &addr, &size); > + if ( res ) > + { > + early_printk("omap-uart: Unable to retrieve the base" > + " address of the UART\n"); > + return res; > + } > + > + uart->regs = ioremap_attr(addr, size, PAGE_HYPERVISOR_NOCACHE); > + if ( !uart->regs ) > + { > + early_printk("omap-uart: Unable to map the UART memory\n"); > + return -ENOMEM; > + } > + > + res = dt_device_get_irq(dev, 0, &uart->irq); > + if ( res ) > + { > + early_printk("omap-uart: Unable to retrieve the IRQ\n"); > + return res; > + } > + > + /* Register with generic serial driver */ > + serial_register_uart(SERHND_DTUART, &omap_uart_driver, uart); > + > + dt_device_set_used_by(dev, DOMID_XEN); > + > + return 0; > +} > + > +static const char const *omap_uart_dt_compat[] __initdata > +{ > + "ti,omap4-uart", > + NULL > +}; > + > +DT_DEVICE_START(omap_uart, "OMAP UART", DEVICE_SERIAL) > + .compatible = omap_uart_dt_compat, > + .init = omap_uart_init, > +DT_DEVICE_END > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h > index 33daa6d..697cac1 100644 > --- a/xen/include/xen/8250-uart.h > +++ b/xen/include/xen/8250-uart.h > @@ -58,19 +58,51 @@ > #define UART_FCR_CLRX 0x02 /* clear Rx FIFO */ > #define UART_FCR_CLTX 0x04 /* clear Tx FIFO */ > #define UART_FCR_DMA 0x10 /* enter DMA mode */ > +Spurious line.> #define UART_FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */ > #define UART_FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */ > #define UART_FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */ > #define UART_FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */ > > +/* > + * Note: The FIFO trigger levels are chip specific: > + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 > + * PC16550D: 1 4 8 14 xx xx xx xx > + * TI16C550A: 1 4 8 14 xx xx xx xx > + * TI16C550C: 1 4 8 14 xx xx xx xx > + * ST16C550: 1 4 8 14 xx xx xx xx > + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 > + * NS16C552: 1 4 8 14 xx xx xx xx > + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 > + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 > + * TI16C752: 8 16 56 60 8 16 32 56 > + * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA > + */ > +#define UART_FCR_R_TRIG_00 0x00 > +#define UART_FCR_R_TRIG_01 0x40 > +#define UART_FCR_R_TRIG_10 0x80 > +#define UART_FCR_R_TRIG_11 0xc0 > +#define UART_FCR_T_TRIG_00 0x00 > +#define UART_FCR_T_TRIG_01 0x10 > +#define UART_FCR_T_TRIG_10 0x20 > +#define UART_FCR_T_TRIG_11 0x30 > + > /* Line Control Register */ > #define UART_LCR_DLAB 0x80 /* Divisor Latch Access */ > > +/* > + * Access to some registers depends on register access / configuration > + * mode. > + */ > +#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configuration mode A */ > +#define UART_LCR_CONF_MODE_B 0xBF /* Configuration mode B */ > + > /* Modem Control Register */ > -#define UART_MCR_DTR 0x01 /* Data Terminal Ready */ > -#define UART_MCR_RTS 0x02 /* Request to Send */ > -#define UART_MCR_OUT2 0x08 /* OUT2: interrupt mask */ > +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ > #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ > +#define UART_MCR_OUT2 0x08 /* Out2 complement */ > +#define UART_MCR_RTS 0x02 /* RTS complement */ > +#define UART_MCR_DTR 0x01 /* DTR complement */Could you keep the real meaning of DTR and RTS? It''s clearer.> > /* Line Status Register */ > #define UART_LSR_DR 0x01 /* Data ready */ > @@ -96,6 +128,26 @@ > #define RESUME_DELAY MILLISECS(10) > #define RESUME_RETRIES 100 > > +/* Enhanced feature register */ > +#define UART_OMAP_EFR 0x02 > + > +#define UART_OMAP_EFR_ECB 0x10 /* Enhanced control bit */ > + > +/* Mode definition register 1 */ > +#define UART_OMAP_MDR1 0x08 > + > +/* > + * These are the definitions for the MDR1 register > + */ > +#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ > +#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ > + > +/* Supplementary control register */ > +#define UART_OMAP_SCR 0x10 > + > +/* SCR register bitmasks */ > +#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) > + > #endif /* __XEN_8250_UART_H__ */ > > /* > diff --git a/xen/include/xen/device_tree.h b/xen/include/xen/device_tree.h > index 5a2a5c6..d4d2b29 100644 > --- a/xen/include/xen/device_tree.h > +++ b/xen/include/xen/device_tree.h > @@ -300,6 +300,12 @@ const void *dt_get_property(const struct dt_device_node *np, > const char *name, u32 *lenp); > > /** > + * dt_property_read_u32 - Helper to read a u32 property.Could you add a bit more of documentation (arguments, return value...)?> + */ > +bool_t dt_property_read_u32(const struct dt_device_node *np, > + const char *name, u32 *out_value); > + > +/** > * Checks if the given "compat" string matches one of the strings in > * the device''s "compatible" property > */ >-- Julien Grall
Andrii Anisov
2013-Aug-08 08:31 UTC
Re: [PATCH v3 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
> > diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c > index 4ed7882..104aefc 100644 > --- a/xen/arch/arm/time.c > +++ b/xen/arch/arm/time.c > @@ -104,6 +104,7 @@ int __init init_xen_time(void) > struct dt_device_node *dev; > int res; > unsigned int i; > + u32 rate; > > dev = dt_find_compatible_node(NULL, NULL, "arm,armv7-timer"); > if ( !dev ) > @@ -134,7 +135,11 @@ int __init init_xen_time(void) > if ( !cpu_has_gentimer ) > panic("CPU does not support the Generic Timer v1 interface.\n"); > > - cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; > + res = dt_property_read_u32(dev, "clock-frequency", &rate); > + if ( res ) > + cpu_khz = rate / 1000; > + else > + cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; > > boot_count = READ_SYSREG64(CNTPCT_EL0); > printk("Using generic timer at %lu KHz\n", cpu_khz); >I would suggest to extract this into a separate patch. This chunk is a generic improvement to add support of dt specified clock freq, while all the rest is a platform specific. *Sincerely,* *Andrii Anisov.* _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
Chen Baozi
2013-Aug-08 08:58 UTC
Re: [PATCH v3 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
On Aug 8, 2013, at 4:31 PM, Andrii Anisov <andrii.anisov@globallogic.com> wrote:> diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c > index 4ed7882..104aefc 100644 > --- a/xen/arch/arm/time.c > +++ b/xen/arch/arm/time.c > @@ -104,6 +104,7 @@ int __init init_xen_time(void) > struct dt_device_node *dev; > int res; > unsigned int i; > + u32 rate; > > dev = dt_find_compatible_node(NULL, NULL, "arm,armv7-timer"); > if ( !dev ) > @@ -134,7 +135,11 @@ int __init init_xen_time(void) > if ( !cpu_has_gentimer ) > panic("CPU does not support the Generic Timer v1 interface.\n"); > > - cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; > + res = dt_property_read_u32(dev, "clock-frequency", &rate); > + if ( res ) > + cpu_khz = rate / 1000; > + else > + cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; > > boot_count = READ_SYSREG64(CNTPCT_EL0); > printk("Using generic timer at %lu KHz\n", cpu_khz); > > I would suggest to extract this into a separate patch. This chunk is a generic improvement to add support of dt specified clock freq, while all the rest is a platform specific.I''m OK with it. What''s your opinion, Julien? Cheers, Baozi
Julien Grall
2013-Aug-08 10:12 UTC
Re: [PATCH v3 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
On 08/08/2013 09:58 AM, Chen Baozi wrote:> > On Aug 8, 2013, at 4:31 PM, Andrii Anisov <andrii.anisov@globallogic.com> wrote: > >> diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c >> index 4ed7882..104aefc 100644 >> --- a/xen/arch/arm/time.c >> +++ b/xen/arch/arm/time.c >> @@ -104,6 +104,7 @@ int __init init_xen_time(void) >> struct dt_device_node *dev; >> int res; >> unsigned int i; >> + u32 rate; >> >> dev = dt_find_compatible_node(NULL, NULL, "arm,armv7-timer"); >> if ( !dev ) >> @@ -134,7 +135,11 @@ int __init init_xen_time(void) >> if ( !cpu_has_gentimer ) >> panic("CPU does not support the Generic Timer v1 interface.\n"); >> >> - cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; >> + res = dt_property_read_u32(dev, "clock-frequency", &rate); >> + if ( res ) >> + cpu_khz = rate / 1000; >> + else >> + cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; >> >> boot_count = READ_SYSREG64(CNTPCT_EL0); >> printk("Using generic timer at %lu KHz\n", cpu_khz); >> >> I would suggest to extract this into a separate patch. This chunk is a generic improvement to add support of dt specified clock freq, while all the rest is a platform specific. > > I''m OK with it. What''s your opinion, Julien?I''m OK with Andrii. It''s better to have only one functionality per patch. Cheers, -- Julien Grall