Xen devel - Aug 2013 - [PATCH] Nested VMX: Flush TLBs and Caches if paging mode changed

From: Yang Zhang <yang.z.zhang@Intel.com>

According to SDM, if paging mode is changed, then whole TLBs and caches will
be flushed. This is missed in nested handle logic. Also this fixed the issue
that 64 bits windows cannot boot up on top of L1 kvm.

Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
---
 xen/arch/x86/mm/paging.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c
index cd08b2a..4ba7669 100644
--- a/xen/arch/x86/mm/paging.c
+++ b/xen/arch/x86/mm/paging.c
@@ -709,6 +709,7 @@ void paging_update_nestedmode(struct vcpu *v)
     else
         /* TODO: shadow-on-shadow */
         v->arch.paging.nestedmode = NULL;
+    hvm_asid_flush_vcpu(v);
 }
 
 void paging_write_p2m_entry(struct p2m_domain *p2m, unsigned long gfn,
-- 
1.7.1

On 06/08/2013 15:08, "Yang Zhang" <yang.z.zhang@intel.com>
wrote:
> From: Yang Zhang <yang.z.zhang@Intel.com>
> 
> According to SDM, if paging mode is changed, then whole TLBs and caches
will
> be flushed. This is missed in nested handle logic. Also this fixed the
issue
> that 64 bits windows cannot boot up on top of L1 kvm.
> 
> Signed-off-by: Yang Zhang <yang.z.zhang@Intel.com>
Acked-by: Keir Fraser <keir@xen.org>
> ---
>  xen/arch/x86/mm/paging.c |    1 +
>  1 files changed, 1 insertions(+), 0 deletions(-)
> 
> diff --git a/xen/arch/x86/mm/paging.c b/xen/arch/x86/mm/paging.c
> index cd08b2a..4ba7669 100644
> --- a/xen/arch/x86/mm/paging.c
> +++ b/xen/arch/x86/mm/paging.c
> @@ -709,6 +709,7 @@ void paging_update_nestedmode(struct vcpu *v)
>      else
>          /* TODO: shadow-on-shadow */
>          v->arch.paging.nestedmode = NULL;
> +    hvm_asid_flush_vcpu(v);
>  }
>  
>  void paging_write_p2m_entry(struct p2m_domain *p2m, unsigned long gfn,