Chen Baozi
2013-Aug-05 11:49 UTC
[PATCH 0/5] Add UART support and arch timer initialization for OMAP5
Since OMAP UART has a few distinct features than common 8250 UART, I
re-implemented its driver rather than porting it based on ns16550.c.
There are mainly two big differences between the implementations. First,
OMAP UART introduces the concept of register access mode, which divides
the register map into seperated space. Switching the access mode is then
necessary when configuring it. Second, THRE interrupt needs to be disable
after finished transmission and enabled once transmission started. This
is because the semantic of THRE interrupt differs from common 8250 in
TI''s
implementation, which would be generated if TX FIFO below trigger level
and cannot be cleared by simply write to THR once.
Besides UART driver, arch timer initialization for OMAP5432 platform
is also done in this patch series.
Chen Baozi (5):
xen: rename ns16550-uart.h to 8250-uart.h and fix some typos
xen/arm: add OMAP5432 UART support for early_printk
xen/arm: Add the new OMAP UART driver.
xen/arm: Introduce platform recognition codes for the OMAP5
xen/arm: Add OMAP5 architected timer initialization codes.
config/arm32.mk | 1 +
docs/misc/arm/early-printk.txt | 1 +
xen/arch/arm/Rules.mk | 4 +
xen/arch/arm/arm32/debug-8250.inc | 41 +++
xen/arch/arm/platforms/Makefile | 1 +
xen/arch/arm/platforms/omap5.c | 113 ++++++++
xen/arch/arm/time.c | 7 +-
xen/drivers/char/Makefile | 1 +
xen/drivers/char/ns16550.c | 2 +-
xen/drivers/char/omap-uart.c | 358 ++++++++++++++++++++++++
xen/include/asm-arm/platforms/omap5.h | 38 +++
xen/include/xen/{ns16550-uart.h => 8250-uart.h} | 98 ++++++-
12 files changed, 651 insertions(+), 14 deletions(-)
create mode 100644 xen/arch/arm/arm32/debug-8250.inc
create mode 100644 xen/arch/arm/platforms/omap5.c
create mode 100644 xen/drivers/char/omap-uart.c
create mode 100644 xen/include/asm-arm/platforms/omap5.h
rename xen/include/xen/{ns16550-uart.h => 8250-uart.h} (52%)
--
1.8.1.4
Chen Baozi
2013-Aug-05 11:49 UTC
[PATCH 0/5] Add UART support and arch timer initialization for OMAP5
Since OMAP UART has a few distinct features than common 8250 UART,
Chen Baozi (5):
xen: rename ns16550-uart.h to 8250-uart.h and fix some typos
xen/arm: add OMAP5432 UART support for early_printk
xen/arm: Add the new OMAP UART driver.
xen/arm: Introduce platform recognition codes for the OMAP5
xen/arm: Add OMAP5 architected timer initialization codes.
config/arm32.mk | 1 +
docs/misc/arm/early-printk.txt | 1 +
xen/arch/arm/Rules.mk | 4 +
xen/arch/arm/arm32/debug-8250.inc | 41 +++
xen/arch/arm/platforms/Makefile | 1 +
xen/arch/arm/platforms/omap5.c | 113 ++++++++
xen/arch/arm/time.c | 7 +-
xen/drivers/char/Makefile | 1 +
xen/drivers/char/ns16550.c | 2 +-
xen/drivers/char/omap-uart.c | 358 ++++++++++++++++++++++++
xen/include/asm-arm/platforms/omap5.h | 38 +++
xen/include/xen/{ns16550-uart.h => 8250-uart.h} | 98 ++++++-
12 files changed, 651 insertions(+), 14 deletions(-)
create mode 100644 xen/arch/arm/arm32/debug-8250.inc
create mode 100644 xen/arch/arm/platforms/omap5.c
create mode 100644 xen/drivers/char/omap-uart.c
create mode 100644 xen/include/asm-arm/platforms/omap5.h
rename xen/include/xen/{ns16550-uart.h => 8250-uart.h} (52%)
--
1.8.1.4
Chen Baozi
2013-Aug-05 11:49 UTC
[PATCH 1/5] xen: rename ns16550-uart.h to 8250-uart.h and fix some typos
Since UARTs on OMAP5 & Allwinner''s SoC are not ns16550 but only
8250
compatible, rename ns16550-uart.h to 8250-uart.h, which is a more pervasive
name. At the same time, fix some typos, which have redundance UART_
prefixes in some macros.
Signed-off-by: Chen Baozi <baozich@gmail.com>
---
xen/drivers/char/ns16550.c | 2 +-
xen/include/xen/{ns16550-uart.h => 8250-uart.h} | 18 +++++++++---------
2 files changed, 10 insertions(+), 10 deletions(-)
rename xen/include/xen/{ns16550-uart.h => 8250-uart.h} (89%)
diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
index e085a64..6082c85 100644
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -19,7 +19,7 @@
#include <xen/iocap.h>
#include <xen/pci.h>
#include <xen/pci_regs.h>
-#include <xen/ns16550-uart.h>
+#include <xen/8250-uart.h>
#include <asm/io.h>
#ifdef CONFIG_X86
#include <asm/fixmap.h>
diff --git a/xen/include/xen/ns16550-uart.h b/xen/include/xen/8250-uart.h
similarity index 89%
rename from xen/include/xen/ns16550-uart.h
rename to xen/include/xen/8250-uart.h
index 232cef9..7287364 100644
--- a/xen/include/xen/ns16550-uart.h
+++ b/xen/include/xen/8250-uart.h
@@ -1,5 +1,5 @@
/*
- * xen/include/xen/ns16550-uart.h
+ * xen/include/xen/8250-uart.h
*
* This header is extracted from driver/char/ns16550.c
*
@@ -19,8 +19,8 @@
* GNU General Public License for more details.
*/
-#ifndef __XEN_NS16550_UART_H__
-#define __XEN_NS16550_UART_H__
+#ifndef __XEN_8250_UART_H__
+#define __XEN_8250_UART_H__
/* Register offsets */
#define UART_RBR 0x00 /* receive buffer */
@@ -43,11 +43,11 @@
/* Interrupt Identificatiegister */
#define UART_IIR_NOINT 0x01 /* no interrupt pending */
-#define UART_UART_IIR_IMA 0x06 /* interrupt identity: */
-#define UART_UART_IIR_LSI 0x06 /* - rx line status */
-#define UART_UART_IIR_RDA 0x04 /* - rx data recv''d */
-#define UART_UART_IIR_THR 0x02 /* - tx reg. empty */
-#define UART_UART_IIR_MSI 0x00 /* - MODEM status */
+#define UART_IIR_IMA 0x06 /* interrupt identity: */
+#define UART_IIR_LSI 0x06 /* - rx line status */
+#define UART_IIR_RDA 0x04 /* - rx data recv''d */
+#define UART_IIR_THR 0x02 /* - tx reg. empty */
+#define UART_IIR_MSI 0x00 /* - MODEM status */
/* FIFO Control Register */
#define UART_FCR_ENABLE 0x01 /* enable FIFO */
@@ -92,7 +92,7 @@
#define RESUME_DELAY MILLISECS(10)
#define RESUME_RETRIES 100
-#endif /* __XEN_NS16550_UART_H__ */
+#endif /* __XEN_8250_UART_H__ */
/*
* Local variables:
--
1.8.1.4
Chen Baozi
2013-Aug-05 11:49 UTC
[PATCH 2/5] xen/arm: add OMAP5432 UART support for early_printk
Signed-off-by: Chen Baozi <baozich@gmail.com> --- docs/misc/arm/early-printk.txt | 1 + xen/arch/arm/Rules.mk | 4 ++++ xen/arch/arm/arm32/debug-8250.inc | 41 +++++++++++++++++++++++++++++++++++++++ xen/include/xen/8250-uart.h | 6 ++++++ 4 files changed, 52 insertions(+) create mode 100644 xen/arch/arm/arm32/debug-8250.inc diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt index fbc3208..874488f 100644 --- a/docs/misc/arm/early-printk.txt +++ b/docs/misc/arm/early-printk.txt @@ -13,6 +13,7 @@ where mach is the name of the machine: - exynos5250: printk with the second UART - midway: printk with the pl011 on Calxeda Midway processors - fastmodel: printk on ARM Fastmodel software emulators + - omap5432: printk with UART3 on TI OMAP5432 processors The base address and baud rate is hardcoded in xen/arch/arm/Rules.mk, see there when adding support for new machines. diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk index a18e7fd..346c824 100644 --- a/xen/arch/arm/Rules.mk +++ b/xen/arch/arm/Rules.mk @@ -64,6 +64,10 @@ EARLY_PRINTK_INC := pl011 EARLY_PRINTK_BAUD := 115200 EARLY_UART_BASE_ADDRESS := 0xfff36000 endif +ifeq ($(CONFIG_EARLY_PRINTK), omap5432) +EARLY_PRINTK_INC := 8250 +EARLY_UART_BASE_ADDRESS := 0x48020000 +endif ifneq ($(EARLY_PRINTK_INC),) EARLY_PRINTK := y diff --git a/xen/arch/arm/arm32/debug-8250.inc b/xen/arch/arm/arm32/debug-8250.inc new file mode 100644 index 0000000..955d90c --- /dev/null +++ b/xen/arch/arm/arm32/debug-8250.inc @@ -0,0 +1,41 @@ +/* + * xen/arch/arm/arm32/debug-8250.inc + * + * 8250 specific debug code + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <xen/8250-uart.h> + +/* OMAP UART wait UART to be ready to transmit + * rb: register which contains the UART base address + * rc: scratch register */ +.macro early_uart_ready rb rc +1: + ldr \rc, [\rb, #(UART_LSR << REG_SHIFT)] /* Read LSR */ + tst \rc, #UART_LSR_THRE /* Check Xmit holding register flag */ + beq 1b /* Wait for the UART to be ready */ +.endm + +/* OMAP UART transmit character + * rb: register which contains the UART base address + * rt: register which contains the character to transmit */ +.macro early_uart_transmit rb rt + str \rt, [\rb, #UART_THR] /* Write Transmit buffer */ +.endm + +/* + * Local variables: + * mode: ASM + * indent-tabs-mode: nil + * End: + */ diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h index 7287364..0e6c6bd 100644 --- a/xen/include/xen/8250-uart.h +++ b/xen/include/xen/8250-uart.h @@ -22,6 +22,12 @@ #ifndef __XEN_8250_UART_H__ #define __XEN_8250_UART_H__ +#ifdef CONFIG_ARM +#define REG_SHIFT 2 +#else +#define REG_SHIFT 0 +#endif + /* Register offsets */ #define UART_RBR 0x00 /* receive buffer */ #define UART_THR 0x00 /* transmit holding */ -- 1.8.1.4
TI OMAP UART introduces some features such as register access modes, which
makes its configuration and interrupt handling differs from 8250 compatible
UART. Thus, we seperate this driver from ns16550''s implementation.
Signed-off-by: Chen Baozi <baozich@gmail.com>
---
config/arm32.mk | 1 +
xen/drivers/char/Makefile | 1 +
xen/drivers/char/omap-uart.c | 358 +++++++++++++++++++++++++++++++++++++++++++
xen/include/xen/8250-uart.h | 74 ++++++++-
4 files changed, 431 insertions(+), 3 deletions(-)
create mode 100644 xen/drivers/char/omap-uart.c
diff --git a/config/arm32.mk b/config/arm32.mk
index 8e21158..76e229d 100644
--- a/config/arm32.mk
+++ b/config/arm32.mk
@@ -11,6 +11,7 @@ CFLAGS += -marm
HAS_PL011 := y
HAS_EXYNOS4210 := y
+HAS_OMAP := y
# Use only if calling $(LD) directly.
LDFLAGS_DIRECT += -EL
diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile
index 37543f0..911b788 100644
--- a/xen/drivers/char/Makefile
+++ b/xen/drivers/char/Makefile
@@ -2,6 +2,7 @@ obj-y += console.o
obj-$(HAS_NS16550) += ns16550.o
obj-$(HAS_PL011) += pl011.o
obj-$(HAS_EXYNOS4210) += exynos4210-uart.o
+obj-$(HAS_OMAP) += omap-uart.o
obj-$(HAS_EHCI) += ehci-dbgp.o
obj-$(CONFIG_ARM) += dt-uart.o
obj-y += serial.o
diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c
new file mode 100644
index 0000000..a8cbcc7
--- /dev/null
+++ b/xen/drivers/char/omap-uart.c
@@ -0,0 +1,358 @@
+/*
+ * omap-uart.c
+ * Based on drivers/char/ns16550.c
+ *
+ * Driver for OMAP-UART contorller
+ *
+ * Copyright (C) 2012, Chen Baozi <baozich@gmail.com>
+ *
+ * Note: This driver is made separate from 16550-series UART driver as
+ * omap platform has some specific configurations
+ */
+
+#include <xen/config.h>
+#include <xen/console.h>
+#include <xen/serial.h>
+#include <xen/init.h>
+#include <xen/irq.h>
+#include <asm/early_printk.h>
+#include <xen/device_tree.h>
+#include <asm/device.h>
+#include <xen/errno.h>
+#include <xen/mm.h>
+#include <xen/vmap.h>
+#include <xen/8250-uart.h>
+
+static struct omap_uart {
+ u32 baud, clock_hz, data_bits, parity, stop_bits, fifo_size;
+ struct dt_irq irq;
+ volatile uint32_t *regs;
+ struct irqaction irqaction;
+
+ u32 dll;
+ u32 ier;
+ u32 dlh;
+ u32 fcr;
+ u32 efr;
+ u32 lcr;
+ u32 mcr;
+ u32 mdr1;
+ u32 scr;
+
+} omap_com = {0};
+
+static void omap_uart_interrupt(int irq, void *data, struct cpu_user_regs
*regs)
+{
+ struct serial_port *port = data;
+ struct omap_uart *uart = port->uart;
+ u32 lsr;
+
+ do
+ {
+ lsr = uart->regs[UART_LSR] & 0xff;
+ if (lsr & UART_LSR_THRE)
+ serial_tx_interrupt(port, regs);
+ if (lsr & UART_LSR_DR)
+ serial_rx_interrupt(port, regs);
+
+ if ( port->txbufc == port->txbufp ) {
+ uart->regs[UART_IER] = UART_IER_ERDAI | UART_IER_ELSI;
+ }
+ } while (!(uart->regs[UART_IIR] & UART_IIR_NOINT));
+
+
+}
+
+static void baud_protocol_setup(struct omap_uart *uart)
+{
+ /*
+ * Switch to register configuration mode B to access the UART_OMAP_EFR
+ * register.
+ */
+ uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B;
+ /*
+ * Enable access to the UART_IER[7:4] bit field.
+ */
+ uart->efr = uart->regs[UART_OMAP_EFR];
+ uart->regs[UART_OMAP_EFR] = uart->efr | UART_OMAP_EFR_ECB;
+ /*
+ * Switch to register operation mode to access the UART_IER register.
+ */
+ uart->regs[UART_LCR] = 0x0;
+ /*
+ * Clear the UART_IER register (set the UART_IER[4] SLEEP_MODE bit
+ * to 0 to change the UART_DLL and UART_DLM register). Set the
+ * UART_IER register value to 0x0000.
+ */
+ uart->regs[UART_IER] = 0x0;
+ /*
+ * Switch to register configuartion mode B to access the UART_DLL and
+ * UART_DLM registers.
+ */
+ uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B;
+ /*
+ * Load divisor value.
+ */
+ uart->regs[UART_DLL] = uart->dll;
+ uart->regs[UART_DLM] = uart->dlh;
+ /*
+ * Restore the UART_OMAP_EFR
+ */
+ uart->regs[UART_OMAP_EFR] = uart->efr;
+ /*
+ * Load the new protocol formatting (parity, stop-bit, character length)
+ * and switch to register operational mode.
+ */
+ uart->regs[UART_LCR] = uart->lcr;
+}
+
+static void fifo_setup(struct omap_uart *uart)
+{
+ /*
+ * Switch to register configuration mode B to access the UART_OMAP_EFR
+ * register.
+ */
+ uart->lcr = uart->regs[UART_LCR];
+ uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B;
+ /*
+ * Enable register submode TCR_TLR to access the UART_OMAP_TLR register.
+ */
+ uart->efr = uart->regs[UART_OMAP_EFR];
+ uart->regs[UART_OMAP_EFR] = uart->efr | UART_OMAP_EFR_ECB;
+ /*
+ * Switch to register configuration mode A to access the UART_MCR
+ * register.
+ */
+ uart->regs[UART_LCR] = UART_LCR_CONF_MODE_A;
+ /*
+ * Enable register submode TCR_TLR to access the UART_OMAP_TLR register
+ */
+ uart->mcr = uart->regs[UART_MCR];
+ uart->regs[UART_MCR] = uart->mcr | UART_MCR_TCRTLR;
+ /*
+ * Enable the FIFO; load the new FIFO trigger and the new DMA mode.
+ */
+ uart->regs[UART_FCR] = uart->fcr;
+ /*
+ * Switch to register configuration mode B to access the UART_EFR
+ * register.
+ */
+ uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B;
+ /*
+ * Load the new FIFO triggers and the new DMA mode bit.
+ */
+ uart->regs[UART_OMAP_SCR] = uart->scr;
+ /*
+ * Restore the UART_OMAP_EFR[4] value.
+ */
+ uart->regs[UART_OMAP_EFR] = uart->efr;
+ /*
+ * Switch to register configuration mode A to access the UART_MCR
+ * register.
+ */
+ uart->regs[UART_LCR] = UART_LCR_CONF_MODE_A;
+ /*
+ * Restore UART_MCR[6] value.
+ */
+ uart->regs[UART_MCR] = uart->mcr;
+ /*
+ * Restore UART_LCR value.
+ */
+ uart->regs[UART_LCR] = uart->lcr;
+}
+
+static void __init omap_uart_init_preirq(struct serial_port *port)
+{
+ struct omap_uart *uart = port->uart;
+ unsigned int divisor;
+
+ /*
+ * Clear the FIFO buffers.
+ */
+ uart->regs[UART_FCR] = UART_FCR_ENABLE;
+ uart->regs[UART_FCR] = UART_FCR_ENABLE | UART_FCR_CLRX | UART_FCR_CLTX;
+ uart->regs[UART_FCR] = 0;
+
+ /*
+ * Calculate desired value.
+ */
+ divisor = uart->clock_hz / (uart->baud << 4);
+ uart->dll = divisor & 0xff;
+ uart->dlh = divisor >> 8;
+ uart->lcr = (uart->data_bits - 5) | ((uart->stop_bits - 1)
<< 2) | uart->parity;
+ uart->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_10 | UART_FCR_ENABLE;
+ uart->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
+ uart->ier = UART_IER_ERDAI | UART_IER_ETHREI | UART_IER_ELSI;
+
+ /*
+ * The TRM says the mode should be disabled while UART_DLL and UART_DHL
+ * are being changed so we disable before setup, then enable.
+ */
+ uart->regs[UART_OMAP_MDR1] = UART_OMAP_MDR1_DISABLE;
+
+ /* Baud rate & protocol format setup */
+ baud_protocol_setup(uart);
+
+ /* FIFO setup */
+ fifo_setup(uart);
+
+ /* No flow control */
+ uart->regs[UART_MCR] = UART_MCR_DTR | UART_MCR_RTS;
+
+ uart->regs[UART_OMAP_MDR1] = UART_OMAP_MDR1_16X_MODE;
+
+ uart->fifo_size = 64;
+}
+
+static void __init omap_uart_init_postirq(struct serial_port *port)
+{
+ struct omap_uart *uart = port->uart;
+
+ uart->irqaction.handler = omap_uart_interrupt;
+ uart->irqaction.name = "omap_uart";
+ uart->irqaction.dev_id = port;
+
+ if (setup_dt_irq(&uart->irq, &uart->irqaction) != 0)
+ dprintk(XENLOG_ERR, "Failed to allocated omap_uart IRQ %d\n",
+ uart->irq.irq);
+
+ /* Enable interrupts */
+ uart->regs[UART_IER] = uart->ier;
+}
+
+static void omap_uart_suspend(struct serial_port *port)
+{
+ BUG();
+}
+
+static void omap_uart_resume(struct serial_port *port)
+{
+ BUG();
+}
+
+static unsigned int omap_uart_tx_ready(struct serial_port *port)
+{
+ struct omap_uart *uart = port->uart;
+
+ uart->regs[UART_IER] = uart->ier;
+
+ return uart->regs[UART_LSR] & UART_LSR_THRE ? uart->fifo_size :
0;
+}
+
+static void omap_uart_putc(struct serial_port *port, char c)
+{
+ struct omap_uart *uart = port->uart;
+
+ uart->regs[UART_THR] = (uint32_t)(unsigned char) c;
+}
+
+static int omap_uart_getc(struct serial_port *port, char *pc)
+{
+ struct omap_uart *uart = port->uart;
+
+ if (!(uart->regs[UART_LSR] & UART_LSR_DR))
+ return 0;
+
+ *pc = uart->regs[UART_RBR] & 0xff;
+ return 1;
+}
+
+static int __init omap_uart_irq(struct serial_port *port)
+{
+ struct omap_uart *uart = port->uart;
+
+ return ((uart->irq.irq > 0) ? uart->irq.irq : -1);
+}
+
+static const struct dt_irq __init *omap_uart_dt_irq(struct serial_port *port)
+{
+ struct omap_uart *uart = port->uart;
+
+ return &uart->irq;
+}
+
+static struct uart_driver __read_mostly omap_uart_driver = {
+ .init_preirq = omap_uart_init_preirq,
+ .init_postirq = omap_uart_init_postirq,
+ .endboot = NULL,
+ .suspend = omap_uart_suspend,
+ .resume = omap_uart_resume,
+ .tx_ready = omap_uart_tx_ready,
+ .putc = omap_uart_putc,
+ .getc = omap_uart_getc,
+ .irq = omap_uart_irq,
+ .dt_irq_get = omap_uart_dt_irq,
+};
+
+static int __init omap_uart_init(struct dt_device_node *dev,
+ const void *data)
+{
+ const char *config = data;
+ struct omap_uart *uart;
+ const __be32 *clkspec;
+ int res;
+ u64 addr, size;
+
+ if (strcmp(config, ""))
+ early_printk("WARNING: UART configuration is not
supported\n");
+
+ uart = &omap_com;
+
+ clkspec = dt_get_property(dev, "clock-frequency", NULL);
+ if (clkspec == NULL) {
+ early_printk("omap-uart: Unable to retrieve the clock
frequency\n");
+ return -EINVAL;
+ }
+
+ uart->clock_hz = be32_to_cpup(clkspec);
+ uart->baud = 115200;
+ uart->data_bits = 8;
+ uart->parity = UART_PARITY_NONE;
+ uart->stop_bits = 1;
+
+ res = dt_device_get_address(dev, 0, &addr, &size);
+ if (res) {
+ early_printk("omap-uart: Unable to retrieve the base"
+ " address of the UART\n");
+ return res;
+ }
+
+ uart->regs = ioremap_attr(addr, size, PAGE_HYPERVISOR_NOCACHE);
+ if (!uart->regs) {
+ early_printk("omap-uart: Unable to map the UART memory\n");
+ return -ENOMEM;
+ }
+
+ res = dt_device_get_irq(dev, 0, &uart->irq);
+ if (res) {
+ early_printk("omap-uart: Unable to retrieve the IRQ\n");
+ return res;
+ }
+
+ /* Register with generic serial driver */
+ serial_register_uart(SERHND_DTUART, &omap_uart_driver, uart);
+
+ dt_device_set_used_by(dev, DOMID_XEN);
+
+ return 0;
+}
+
+static const char const *omap_uart_dt_compat[] __initdata +{
+ "ti,omap4-uart",
+ NULL
+};
+
+DT_DEVICE_START(omap_uart, "OMAP UART", DEVICE_SERIAL)
+ .compatible = omap_uart_dt_compat,
+ .init = omap_uart_init,
+DT_DEVICE_END
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h
index 0e6c6bd..a75f36a 100644
--- a/xen/include/xen/8250-uart.h
+++ b/xen/include/xen/8250-uart.h
@@ -60,19 +60,55 @@
#define UART_FCR_CLRX 0x02 /* clear Rx FIFO */
#define UART_FCR_CLTX 0x04 /* clear Tx FIFO */
#define UART_FCR_DMA 0x10 /* enter DMA mode */
+
#define UART_FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */
#define UART_FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */
#define UART_FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */
#define UART_FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */
+/*
+ * Note: The FIFO trigger levels are chip specific:
+ * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11
+ * PC16550D: 1 4 8 14 xx xx xx xx
+ * TI16C550A: 1 4 8 14 xx xx xx xx
+ * TI16C550C: 1 4 8 14 xx xx xx xx
+ * ST16C550: 1 4 8 14 xx xx xx xx
+ * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2
+ * NS16C552: 1 4 8 14 xx xx xx xx
+ * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654
+ * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750
+ * TI16C752: 8 16 56 60 8 16 32 56
+ * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA
+ */
+#define UART_FCR_R_TRIG_00 0x00
+#define UART_FCR_R_TRIG_01 0x40
+#define UART_FCR_R_TRIG_10 0x80
+#define UART_FCR_R_TRIG_11 0xc0
+#define UART_FCR_T_TRIG_00 0x00
+#define UART_FCR_T_TRIG_01 0x10
+#define UART_FCR_T_TRIG_10 0x20
+#define UART_FCR_T_TRIG_11 0x30
+
/* Line Control Register */
#define UART_LCR_DLAB 0x80 /* Divisor Latch Access */
+/*
+ * Access to some registers depends on register access / configuration
+ * mode.
+ */
+#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */
+#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */
+
/* Modem Control Register */
-#define UART_MCR_DTR 0x01 /* Data Terminal Ready */
-#define UART_MCR_RTS 0x02 /* Request to Send */
-#define UART_MCR_OUT2 0x08 /* OUT2: interrupt mask */
+#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */
+#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */
+#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */
+#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750)
*/
#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
+#define UART_MCR_OUT2 0x08 /* Out2 complement */
+#define UART_MCR_OUT1 0x04 /* Out1 complement */
+#define UART_MCR_RTS 0x02 /* RTS complement */
+#define UART_MCR_DTR 0x01 /* DTR complement */
/* Line Status Register */
#define UART_LSR_DR 0x01 /* Data ready */
@@ -98,6 +134,38 @@
#define RESUME_DELAY MILLISECS(10)
#define RESUME_RETRIES 100
+/* Enhanced feature register */
+#define UART_OMAP_EFR 0x02
+
+#define UART_OMAP_EFR_CTS 0x80 /* CTS flow control */
+#define UART_OMAP_EFR_RTS 0x40 /* RTS flow control */
+#define UART_OMAP_EFR_SCD 0x20 /* Special character detect */
+#define UART_OMAP_EFR_ECB 0x10 /* Enhanced control bit */
+
+/* Mode definition register 1 */
+#define UART_OMAP_MDR1 0x08
+
+/*
+ * These are the definitions for the MDR1 register
+ */
+#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */
+#define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */
+#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */
+#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */
+#define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */
+#define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */
+#define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */
+#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */
+
+/* Supplementary control register */
+#define UART_OMAP_SCR 0x10
+
+/* SCR register bitmasks */
+#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
+#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
+#define OMAP_UART_SCR_TX_EMPTY (1 << 3)
+
+
#endif /* __XEN_8250_UART_H__ */
/*
--
1.8.1.4
Chen Baozi
2013-Aug-05 11:49 UTC
[PATCH 4/5] xen/arm: Introduce platform recognition codes for the OMAP5
Signed-off-by: Chen Baozi <baozich@gmail.com>
---
xen/arch/arm/platforms/Makefile | 1 +
xen/arch/arm/platforms/omap5.c | 41 +++++++++++++++++++++++++++++++++++
xen/include/asm-arm/platforms/omap5.h | 23 ++++++++++++++++++++
3 files changed, 65 insertions(+)
create mode 100644 xen/arch/arm/platforms/omap5.c
create mode 100644 xen/include/asm-arm/platforms/omap5.h
diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile
index ff2b65b..90ddcb1 100644
--- a/xen/arch/arm/platforms/Makefile
+++ b/xen/arch/arm/platforms/Makefile
@@ -1,2 +1,3 @@
obj-y += vexpress.o
obj-y += exynos5.o
+obj-y += omap5.o
diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c
new file mode 100644
index 0000000..eecf35b
--- /dev/null
+++ b/xen/arch/arm/platforms/omap5.c
@@ -0,0 +1,41 @@
+/*
+ * xen/arch/arm/platforma/omap5.c
+ *
+ * OMAP5 specific settings
+ *
+ * Chen Baozi <baozich@gmail.com>
+ * Copyright (c) 2013
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributted in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU Gerneral Public License for more details.
+ */
+
+#include <xen/config.h>
+#include <asm/platforms/omap5.h>
+#include <asm/platform.h>
+
+static const char const *omap5_dt_compat[] __initdata +{
+ "ti,omap5",
+ NULL
+};
+
+PLATFORM_START(omap5, "TI OMAP5")
+ .compatible = omap5_dt_compat,
+PLATFORM_END
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/platforms/omap5.h
b/xen/include/asm-arm/platforms/omap5.h
new file mode 100644
index 0000000..fa825b7
--- /dev/null
+++ b/xen/include/asm-arm/platforms/omap5.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_ARM_PLATFORMS_OMAP5_H
+#define __ASM_ASM_PLATFORMS_OMAP5_H
+
+/* Constants below is only used in assembly because the DTS is not yet parsed
*/
+#ifdef __ASSEMBLY__
+
+/* GIC Base Address */
+#define OMAP5_GIC_BASE_ADDRESS 0x48210000
+
+/* OMAP5432 uEVM machine ID */
+#define MACH_TYPE_UEVM 3777
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_PLATFORMS_OMAP5_H */
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
--
1.8.1.4
Chen Baozi
2013-Aug-05 11:49 UTC
[PATCH 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
Signed-off-by: Chen Baozi <baozich@gmail.com>
---
xen/arch/arm/platforms/omap5.c | 72 +++++++++++++++++++++++++++++++++++
xen/arch/arm/time.c | 7 +++-
xen/include/asm-arm/platforms/omap5.h | 15 ++++++++
3 files changed, 93 insertions(+), 1 deletion(-)
diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c
index eecf35b..568b53d 100644
--- a/xen/arch/arm/platforms/omap5.c
+++ b/xen/arch/arm/platforms/omap5.c
@@ -20,6 +20,77 @@
#include <xen/config.h>
#include <asm/platforms/omap5.h>
#include <asm/platform.h>
+#include <xen/mm.h>
+#include <xen/vmap.h>
+
+static uint16_t num_den[8][2] = {
+ { 0, 0 }, /* not used */
+ { 26 * 64, 26 * 125 }, /* 12.0 Mhz */
+ { 2 * 768, 2 * 1625 }, /* 13.0 Mhz */
+ { 0, 0 }, /* not used */
+ { 130 * 8, 130 * 25 }, /* 19.2 Mhz */
+ { 2 * 384, 2 * 1625 }, /* 26.0 Mhz */
+ { 3 * 256, 3 * 1125 }, /* 27.0 Mhz */
+ { 130 * 4, 130 * 25 }, /* 38.4 Mhz */
+};
+
+/*
+ * The realtime counter also called master counter, is a free-running
+ * counter, which is related to real time. It produces the count used
+ * by the CPU local timer peripherals in teh MPU cluster. The timer counts
+ * at a rate of 6.144 MHz. Because the device operates on different clocks
+ * in different power modes, the master counter shifts operation between
+ * clocks, adjusting the increment per clock in hardware accordingly to
+ * maintain a constant count rate.
+ */
+static int omap5_init_time(void)
+{
+ void __iomem *ckgen_prm_base;
+ void __iomem *rt_ct_base;
+ unsigned int sys_clksel;
+ unsigned int num, den, frac1, frac2;
+
+ ckgen_prm_base = ioremap_attr(OMAP5_CKGEN_PRM_BASE,
+ 0x20, PAGE_HYPERVISOR_NOCACHE);
+ if (!ckgen_prm_base) {
+ dprintk(XENLOG_ERR, "%s: PRM_BASE ioremap failed\n",
__func__);
+ return -ENOMEM;
+ }
+
+ sys_clksel = ioreadl(ckgen_prm_base + OMAP5_CM_CLKSEL_SYS) &
+ ~SYS_CLKSEL_MASK;
+
+ iounmap(ckgen_prm_base);
+
+ rt_ct_base = ioremap_attr(REALTIME_COUNTER_BASE,
+ 0x20, PAGE_HYPERVISOR_NOCACHE);
+ if (!rt_ct_base) {
+ dprintk(XENLOG_ERR, "%s: REALTIME_COUNTER_BASE ioremap
failed\n", __func__);
+ return -ENOMEM;
+ }
+
+ frac1 = ioreadl(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET);
+ num = frac1 & ~NUMERATOR_DENUMERATOR_MASK;
+ if (num_den[sys_clksel][0] != num) {
+ frac1 &= NUMERATOR_DENUMERATOR_MASK;
+ frac1 |= num_den[sys_clksel][0];
+ }
+
+ frac2 = ioreadl(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET);
+ den = frac2 & ~NUMERATOR_DENUMERATOR_MASK;
+ if (num_den[sys_clksel][1] != num) {
+ frac2 &= NUMERATOR_DENUMERATOR_MASK;
+ frac2 |= num_den[sys_clksel][1];
+ }
+
+ iowritel(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET, frac1);
+ iowritel(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET,
+ frac2 | PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD);
+
+ iounmap(rt_ct_base);
+
+ return 0;
+}
static const char const *omap5_dt_compat[] __initdata {
@@ -29,6 +100,7 @@ static const char const *omap5_dt_compat[] __initdata
PLATFORM_START(omap5, "TI OMAP5")
.compatible = omap5_dt_compat,
+ .init_time = omap5_init_time,
PLATFORM_END
/*
diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c
index 4ed7882..6ca030a 100644
--- a/xen/arch/arm/time.c
+++ b/xen/arch/arm/time.c
@@ -104,6 +104,7 @@ int __init init_xen_time(void)
struct dt_device_node *dev;
int res;
unsigned int i;
+ const __be32 *rate;
dev = dt_find_compatible_node(NULL, NULL, "arm,armv7-timer");
if ( !dev )
@@ -134,7 +135,11 @@ int __init init_xen_time(void)
if ( !cpu_has_gentimer )
panic("CPU does not support the Generic Timer v1
interface.\n");
- cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000;
+ rate = dt_get_property(dev, "clock-frequency", NULL);
+ if (rate)
+ cpu_khz = be32_to_cpup(rate) / 1000;
+ else
+ cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000;
boot_count = READ_SYSREG64(CNTPCT_EL0);
printk("Using generic timer at %lu KHz\n", cpu_khz);
diff --git a/xen/include/asm-arm/platforms/omap5.h
b/xen/include/asm-arm/platforms/omap5.h
index fa825b7..41d178e 100644
--- a/xen/include/asm-arm/platforms/omap5.h
+++ b/xen/include/asm-arm/platforms/omap5.h
@@ -1,6 +1,21 @@
#ifndef __ASM_ARM_PLATFORMS_OMAP5_H
#define __ASM_ASM_PLATFORMS_OMAP5_H
+#define REALTIME_COUNTER_BASE 0x48243200
+#define INCREMENTER_NUMERATOR_OFFSET 0x10
+#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14
+#define NUMERATOR_DENUMERATOR_MASK 0xfffff000
+#define PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD 0x00010000
+
+#define OMAP5_L4_WKUP 0x4AE00000
+#define OMAP5_PRM_BASE (OMAP5_L4_WKUP + 0x6000)
+#define OMAP5_CKGEN_PRM_BASE (OMAP5_PRM_BASE + 0x100)
+#define OMAP5_CM_CLKSEL_SYS 0x10
+#define SYS_CLKSEL_MASK 0xfffffff8
+
+/* Timer''s frequency */
+#define OMAP5_TIMER_FREQUENCY 6144000 /* 6.144 Mhz*/
+
/* Constants below is only used in assembly because the DTS is not yet parsed
*/
#ifdef __ASSEMBLY__
--
1.8.1.4
On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote:> TI OMAP UART introduces some features such as register access modes, which > makes its configuration and interrupt handling differs from 8250 compatible > UART. Thus, we seperate this driver from ns16550''s implementation.On your previous version of this patch series you use a modified ns16550, why didn''t you continue in the same way?> Signed-off-by: Chen Baozi <baozich@gmail.com> > --- > config/arm32.mk | 1 + > xen/drivers/char/Makefile | 1 + > xen/drivers/char/omap-uart.c | 358 +++++++++++++++++++++++++++++++++++++++++++ > xen/include/xen/8250-uart.h | 74 ++++++++- > 4 files changed, 431 insertions(+), 3 deletions(-) > create mode 100644 xen/drivers/char/omap-uart.c > > diff --git a/config/arm32.mk b/config/arm32.mk > index 8e21158..76e229d 100644 > --- a/config/arm32.mk > +++ b/config/arm32.mk > @@ -11,6 +11,7 @@ CFLAGS += -marm > > HAS_PL011 := y > HAS_EXYNOS4210 := y > +HAS_OMAP := y > > # Use only if calling $(LD) directly. > LDFLAGS_DIRECT += -EL > diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile > index 37543f0..911b788 100644 > --- a/xen/drivers/char/Makefile > +++ b/xen/drivers/char/Makefile > @@ -2,6 +2,7 @@ obj-y += console.o > obj-$(HAS_NS16550) += ns16550.o > obj-$(HAS_PL011) += pl011.o > obj-$(HAS_EXYNOS4210) += exynos4210-uart.o > +obj-$(HAS_OMAP) += omap-uart.o > obj-$(HAS_EHCI) += ehci-dbgp.o > obj-$(CONFIG_ARM) += dt-uart.o > obj-y += serial.o > diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c > new file mode 100644 > index 0000000..a8cbcc7 > --- /dev/null > +++ b/xen/drivers/char/omap-uart.c > @@ -0,0 +1,358 @@ > +/* > + * omap-uart.c > + * Based on drivers/char/ns16550.c > + * > + * Driver for OMAP-UART contorller > + * > + * Copyright (C) 2012, Chen Baozi <baozich@gmail.com> > + * > + * Note: This driver is made separate from 16550-series UART driver as > + * omap platform has some specific configurations > + */ > + > +#include <xen/config.h> > +#include <xen/console.h> > +#include <xen/serial.h> > +#include <xen/init.h> > +#include <xen/irq.h> > +#include <asm/early_printk.h> > +#include <xen/device_tree.h> > +#include <asm/device.h> > +#include <xen/errno.h> > +#include <xen/mm.h> > +#include <xen/vmap.h> > +#include <xen/8250-uart.h> > + > +static struct omap_uart { > + u32 baud, clock_hz, data_bits, parity, stop_bits, fifo_size; > + struct dt_irq irq; > + volatile uint32_t *regs; > + struct irqaction irqaction; > + > + u32 dll; > + u32 ier; > + u32 dlh; > + u32 fcr; > + u32 efr; > + u32 lcr; > + u32 mcr; > + u32 mdr1; > + u32 scr; > + > +} omap_com = {0}; > + > +static void omap_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs) > +{ > + struct serial_port *port = data; > + struct omap_uart *uart = port->uart; > + u32 lsr; > + > + do > + {Why do you change the while by a do-while?> + lsr = uart->regs[UART_LSR] & 0xff;Please use ioread{l,w,...} instead of uart->regs[...]. Same for everywhere in you driver.> + if (lsr & UART_LSR_THRE) > + serial_tx_interrupt(port, regs); > + if (lsr & UART_LSR_DR) > + serial_rx_interrupt(port, regs); > + > + if ( port->txbufc == port->txbufp ) {Unnecessary bracket.> + uart->regs[UART_IER] = UART_IER_ERDAI | UART_IER_ELSI; > + } > + } while (!(uart->regs[UART_IIR] & UART_IIR_NOINT)); > + > + > +} > + > +static void baud_protocol_setup(struct omap_uart *uart) > +{ > + /* > + * Switch to register configuration mode B to access the UART_OMAP_EFR > + * register. > + */ > + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B; > + /* > + * Enable access to the UART_IER[7:4] bit field. > + */ > + uart->efr = uart->regs[UART_OMAP_EFR]; > + uart->regs[UART_OMAP_EFR] = uart->efr | UART_OMAP_EFR_ECB; > + /* > + * Switch to register operation mode to access the UART_IER register. > + */ > + uart->regs[UART_LCR] = 0x0; > + /* > + * Clear the UART_IER register (set the UART_IER[4] SLEEP_MODE bit > + * to 0 to change the UART_DLL and UART_DLM register). Set the > + * UART_IER register value to 0x0000. > + */ > + uart->regs[UART_IER] = 0x0; > + /* > + * Switch to register configuartion mode B to access the UART_DLL and > + * UART_DLM registers. > + */ > + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B; > + /* > + * Load divisor value. > + */ > + uart->regs[UART_DLL] = uart->dll; > + uart->regs[UART_DLM] = uart->dlh; > + /* > + * Restore the UART_OMAP_EFR > + */ > + uart->regs[UART_OMAP_EFR] = uart->efr; > + /* > + * Load the new protocol formatting (parity, stop-bit, character length) > + * and switch to register operational mode. > + */ > + uart->regs[UART_LCR] = uart->lcr; > +} > + > +static void fifo_setup(struct omap_uart *uart) > +{ > + /* > + * Switch to register configuration mode B to access the UART_OMAP_EFR > + * register. > + */ > + uart->lcr = uart->regs[UART_LCR]; > + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B; > + /* > + * Enable register submode TCR_TLR to access the UART_OMAP_TLR register. > + */ > + uart->efr = uart->regs[UART_OMAP_EFR]; > + uart->regs[UART_OMAP_EFR] = uart->efr | UART_OMAP_EFR_ECB; > + /* > + * Switch to register configuration mode A to access the UART_MCR > + * register. > + */ > + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_A; > + /* > + * Enable register submode TCR_TLR to access the UART_OMAP_TLR register > + */ > + uart->mcr = uart->regs[UART_MCR]; > + uart->regs[UART_MCR] = uart->mcr | UART_MCR_TCRTLR; > + /* > + * Enable the FIFO; load the new FIFO trigger and the new DMA mode. > + */ > + uart->regs[UART_FCR] = uart->fcr; > + /* > + * Switch to register configuration mode B to access the UART_EFR > + * register. > + */ > + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B; > + /* > + * Load the new FIFO triggers and the new DMA mode bit. > + */ > + uart->regs[UART_OMAP_SCR] = uart->scr; > + /* > + * Restore the UART_OMAP_EFR[4] value. > + */ > + uart->regs[UART_OMAP_EFR] = uart->efr; > + /* > + * Switch to register configuration mode A to access the UART_MCR > + * register. > + */ > + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_A; > + /* > + * Restore UART_MCR[6] value. > + */ > + uart->regs[UART_MCR] = uart->mcr; > + /* > + * Restore UART_LCR value. > + */ > + uart->regs[UART_LCR] = uart->lcr; > +} > + > +static void __init omap_uart_init_preirq(struct serial_port *port) > +{ > + struct omap_uart *uart = port->uart; > + unsigned int divisor; > + > + /* > + * Clear the FIFO buffers. > + */ > + uart->regs[UART_FCR] = UART_FCR_ENABLE; > + uart->regs[UART_FCR] = UART_FCR_ENABLE | UART_FCR_CLRX | UART_FCR_CLTX; > + uart->regs[UART_FCR] = 0; > + > + /* > + * Calculate desired value. > + */ > + divisor = uart->clock_hz / (uart->baud << 4); > + uart->dll = divisor & 0xff; > + uart->dlh = divisor >> 8; > + uart->lcr = (uart->data_bits - 5) | ((uart->stop_bits - 1) << 2) | uart->parity; > + uart->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_10 | UART_FCR_ENABLE; > + uart->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; > + uart->ier = UART_IER_ERDAI | UART_IER_ETHREI | UART_IER_ELSI;You are wasting space just to store hardcoded value (for fcr, scr, ier). You should use macro.> + > + /* > + * The TRM says the mode should be disabled while UART_DLL and UART_DHL > + * are being changed so we disable before setup, then enable. > + */ > + uart->regs[UART_OMAP_MDR1] = UART_OMAP_MDR1_DISABLE; > + > + /* Baud rate & protocol format setup */ > + baud_protocol_setup(uart); > + > + /* FIFO setup */ > + fifo_setup(uart); > + > + /* No flow control */ > + uart->regs[UART_MCR] = UART_MCR_DTR | UART_MCR_RTS; > + > + uart->regs[UART_OMAP_MDR1] = UART_OMAP_MDR1_16X_MODE; > + > + uart->fifo_size = 64; > +} > + > +static void __init omap_uart_init_postirq(struct serial_port *port) > +{ > + struct omap_uart *uart = port->uart; > + > + uart->irqaction.handler = omap_uart_interrupt; > + uart->irqaction.name = "omap_uart"; > + uart->irqaction.dev_id = port; > + > + if (setup_dt_irq(&uart->irq, &uart->irqaction) != 0)Missing space for the if. if ( a ) ...> + dprintk(XENLOG_ERR, "Failed to allocated omap_uart IRQ %d\n", > + uart->irq.irq); > + > + /* Enable interrupts */ > + uart->regs[UART_IER] = uart->ier;Don''t enable IRQ if setup has failed.> +} > + > +static void omap_uart_suspend(struct serial_port *port) > +{ > + BUG(); > +} > + > +static void omap_uart_resume(struct serial_port *port) > +{ > + BUG(); > +} > + > +static unsigned int omap_uart_tx_ready(struct serial_port *port) > +{ > + struct omap_uart *uart = port->uart; > + > + uart->regs[UART_IER] = uart->ier; > + > + return uart->regs[UART_LSR] & UART_LSR_THRE ? uart->fifo_size : 0; > +} > + > +static void omap_uart_putc(struct serial_port *port, char c) > +{ > + struct omap_uart *uart = port->uart; > + > + uart->regs[UART_THR] = (uint32_t)(unsigned char) c; > +} > + > +static int omap_uart_getc(struct serial_port *port, char *pc) > +{ > + struct omap_uart *uart = port->uart; > + > + if (!(uart->regs[UART_LSR] & UART_LSR_DR))Missing space for the if.> + return 0; > + > + *pc = uart->regs[UART_RBR] & 0xff; > + return 1; > +} > + > +static int __init omap_uart_irq(struct serial_port *port) > +{ > + struct omap_uart *uart = port->uart; > + > + return ((uart->irq.irq > 0) ? uart->irq.irq : -1); > +} > + > +static const struct dt_irq __init *omap_uart_dt_irq(struct serial_port *port) > +{ > + struct omap_uart *uart = port->uart; > + > + return &uart->irq; > +} > + > +static struct uart_driver __read_mostly omap_uart_driver = { > + .init_preirq = omap_uart_init_preirq, > + .init_postirq = omap_uart_init_postirq, > + .endboot = NULL, > + .suspend = omap_uart_suspend, > + .resume = omap_uart_resume, > + .tx_ready = omap_uart_tx_ready, > + .putc = omap_uart_putc, > + .getc = omap_uart_getc, > + .irq = omap_uart_irq, > + .dt_irq_get = omap_uart_dt_irq, > +}; > + > +static int __init omap_uart_init(struct dt_device_node *dev, > + const void *data) > +{ > + const char *config = data; > + struct omap_uart *uart; > + const __be32 *clkspec; > + int res; > + u64 addr, size; > + > + if (strcmp(config, "")) > + early_printk("WARNING: UART configuration is not supported\n"); > + > + uart = &omap_com; > + > + clkspec = dt_get_property(dev, "clock-frequency", NULL); > + if (clkspec == NULL) { > + early_printk("omap-uart: Unable to retrieve the clock frequency\n"); > + return -EINVAL; > + } > + > + uart->clock_hz = be32_to_cpup(clkspec); > + uart->baud = 115200; > + uart->data_bits = 8; > + uart->parity = UART_PARITY_NONE; > + uart->stop_bits = 1; > + > + res = dt_device_get_address(dev, 0, &addr, &size); > + if (res) {The bracket needs to be on a new line.> + early_printk("omap-uart: Unable to retrieve the base" > + " address of the UART\n"); > + return res; > + } > + > + uart->regs = ioremap_attr(addr, size, PAGE_HYPERVISOR_NOCACHE); > + if (!uart->regs) {Missing space and bracket in newline.> + early_printk("omap-uart: Unable to map the UART memory\n"); > + return -ENOMEM; > + } > + > + res = dt_device_get_irq(dev, 0, &uart->irq); > + if (res) {Same here.> + early_printk("omap-uart: Unable to retrieve the IRQ\n"); > + return res; > + } > + > + /* Register with generic serial driver */ > + serial_register_uart(SERHND_DTUART, &omap_uart_driver, uart); > + > + dt_device_set_used_by(dev, DOMID_XEN); > + > + return 0; > +} > + > +static const char const *omap_uart_dt_compat[] __initdata > +{ > + "ti,omap4-uart", > + NULL > +}; > + > +DT_DEVICE_START(omap_uart, "OMAP UART", DEVICE_SERIAL) > + .compatible = omap_uart_dt_compat, > + .init = omap_uart_init, > +DT_DEVICE_END > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h > index 0e6c6bd..a75f36a 100644 > --- a/xen/include/xen/8250-uart.h > +++ b/xen/include/xen/8250-uart.h > @@ -60,19 +60,55 @@ > #define UART_FCR_CLRX 0x02 /* clear Rx FIFO */ > #define UART_FCR_CLTX 0x04 /* clear Tx FIFO */ > #define UART_FCR_DMA 0x10 /* enter DMA mode */ > + > #define UART_FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */ > #define UART_FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */ > #define UART_FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */ > #define UART_FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */ > > +/* > + * Note: The FIFO trigger levels are chip specific: > + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 > + * PC16550D: 1 4 8 14 xx xx xx xx > + * TI16C550A: 1 4 8 14 xx xx xx xx > + * TI16C550C: 1 4 8 14 xx xx xx xx > + * ST16C550: 1 4 8 14 xx xx xx xx > + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 > + * NS16C552: 1 4 8 14 xx xx xx xx > + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 > + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 > + * TI16C752: 8 16 56 60 8 16 32 56 > + * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA > + */ > +#define UART_FCR_R_TRIG_00 0x00 > +#define UART_FCR_R_TRIG_01 0x40 > +#define UART_FCR_R_TRIG_10 0x80 > +#define UART_FCR_R_TRIG_11 0xc0 > +#define UART_FCR_T_TRIG_00 0x00 > +#define UART_FCR_T_TRIG_01 0x10 > +#define UART_FCR_T_TRIG_10 0x20 > +#define UART_FCR_T_TRIG_11 0x30 > + > /* Line Control Register */ > #define UART_LCR_DLAB 0x80 /* Divisor Latch Access */ > > +/* > + * Access to some registers depends on register access / configuration > + * mode. > + */ > +#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ > +#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ > + > /* Modem Control Register */ > -#define UART_MCR_DTR 0x01 /* Data Terminal Ready */ > -#define UART_MCR_RTS 0x02 /* Request to Send */ > -#define UART_MCR_OUT2 0x08 /* OUT2: interrupt mask */ > +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ > +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ > +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */Don''t add unnecessary define.> +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ > #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ > +#define UART_MCR_OUT2 0x08 /* Out2 complement */ > +#define UART_MCR_OUT1 0x04 /* Out1 complement */ > +#define UART_MCR_RTS 0x02 /* RTS complement */ > +#define UART_MCR_DTR 0x01 /* DTR complement */ > > /* Line Status Register */ > #define UART_LSR_DR 0x01 /* Data ready */ > @@ -98,6 +134,38 @@ > #define RESUME_DELAY MILLISECS(10) > #define RESUME_RETRIES 100 > > +/* Enhanced feature register */ > +#define UART_OMAP_EFR 0x02 > + > +#define UART_OMAP_EFR_CTS 0x80 /* CTS flow control */ > +#define UART_OMAP_EFR_RTS 0x40 /* RTS flow control */ > +#define UART_OMAP_EFR_SCD 0x20 /* Special character detect */ > +#define UART_OMAP_EFR_ECB 0x10 /* Enhanced control bit */ > + > +/* Mode definition register 1 */ > +#define UART_OMAP_MDR1 0x08 > + > +/* > + * These are the definitions for the MDR1 register > + */ > +#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ > +#define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ > +#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ > +#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ > +#define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ > +#define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ > +#define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ > +#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ > + > +/* Supplementary control register */ > +#define UART_OMAP_SCR 0x10 > + > +/* SCR register bitmasks */ > +#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) > +#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) > +#define OMAP_UART_SCR_TX_EMPTY (1 << 3) > + > + > #endif /* __XEN_8250_UART_H__ */ > > /*-- Julien Grall
Julien Grall
2013-Aug-06 21:50 UTC
Re: [PATCH 2/5] xen/arm: add OMAP5432 UART support for early_printk
Add Bamvor. On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote:> Signed-off-by: Chen Baozi <baozich@gmail.com> > --- > docs/misc/arm/early-printk.txt | 1 + > xen/arch/arm/Rules.mk | 4 ++++ > xen/arch/arm/arm32/debug-8250.inc | 41 +++++++++++++++++++++++++++++++++++++++ > xen/include/xen/8250-uart.h | 6 ++++++ > 4 files changed, 52 insertions(+) > create mode 100644 xen/arch/arm/arm32/debug-8250.inc > > diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt > index fbc3208..874488f 100644 > --- a/docs/misc/arm/early-printk.txt > +++ b/docs/misc/arm/early-printk.txt > @@ -13,6 +13,7 @@ where mach is the name of the machine: > - exynos5250: printk with the second UART > - midway: printk with the pl011 on Calxeda Midway processors > - fastmodel: printk on ARM Fastmodel software emulators > + - omap5432: printk with UART3 on TI OMAP5432 processorsThis patch looks similar to http://lists.xen.org/archives/html/xen-devel/2013-07/msg00194.html. Could you also add suni6 support?> > The base address and baud rate is hardcoded in xen/arch/arm/Rules.mk, > see there when adding support for new machines. > diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk > index a18e7fd..346c824 100644 > --- a/xen/arch/arm/Rules.mk > +++ b/xen/arch/arm/Rules.mk > @@ -64,6 +64,10 @@ EARLY_PRINTK_INC := pl011 > EARLY_PRINTK_BAUD := 115200 > EARLY_UART_BASE_ADDRESS := 0xfff36000 > endif > +ifeq ($(CONFIG_EARLY_PRINTK), omap5432) > +EARLY_PRINTK_INC := 8250 > +EARLY_UART_BASE_ADDRESS := 0x48020000 > +endif > > ifneq ($(EARLY_PRINTK_INC),) > EARLY_PRINTK := y > diff --git a/xen/arch/arm/arm32/debug-8250.inc b/xen/arch/arm/arm32/debug-8250.inc > new file mode 100644 > index 0000000..955d90c > --- /dev/null > +++ b/xen/arch/arm/arm32/debug-8250.inc > @@ -0,0 +1,41 @@ > +/* > + * xen/arch/arm/arm32/debug-8250.inc > + * > + * 8250 specific debug code > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + */ > + > +#include <xen/8250-uart.h> > + > +/* OMAP UART wait UART to be ready to transmits/OMAP/8250/> + * rb: register which contains the UART base address > + * rc: scratch register */ > +.macro early_uart_ready rb rc > +1: > + ldr \rc, [\rb, #(UART_LSR << REG_SHIFT)] /* Read LSR */ > + tst \rc, #UART_LSR_THRE /* Check Xmit holding register flag */ > + beq 1b /* Wait for the UART to be ready */ > +.endm > + > +/* OMAP UART transmit characterSame here.> + * rb: register which contains the UART base address > + * rt: register which contains the character to transmit */ > +.macro early_uart_transmit rb rt > + str \rt, [\rb, #UART_THR] /* Write Transmit buffer */ > +.endm > + > +/* > + * Local variables: > + * mode: ASM > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h > index 7287364..0e6c6bd 100644 > --- a/xen/include/xen/8250-uart.h > +++ b/xen/include/xen/8250-uart.h > @@ -22,6 +22,12 @@ > #ifndef __XEN_8250_UART_H__ > #define __XEN_8250_UART_H__ > > +#ifdef CONFIG_ARM > +#define REG_SHIFT 2 > +#else > +#define REG_SHIFT 0 > +#endifIf you don''t use REG_SHIFT in other code than ARM, you can remove the #else.> /* Register offsets */ > #define UART_RBR 0x00 /* receive buffer */ > #define UART_THR 0x00 /* transmit holding */-- Julien Grall
Julien Grall
2013-Aug-06 22:00 UTC
Re: [PATCH 4/5] xen/arm: Introduce platform recognition codes for the OMAP5
On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote:> Signed-off-by: Chen Baozi <baozich@gmail.com> > --- > xen/arch/arm/platforms/Makefile | 1 + > xen/arch/arm/platforms/omap5.c | 41 +++++++++++++++++++++++++++++++++++ > xen/include/asm-arm/platforms/omap5.h | 23 ++++++++++++++++++++ > 3 files changed, 65 insertions(+) > create mode 100644 xen/arch/arm/platforms/omap5.c > create mode 100644 xen/include/asm-arm/platforms/omap5.h > > diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile > index ff2b65b..90ddcb1 100644 > --- a/xen/arch/arm/platforms/Makefile > +++ b/xen/arch/arm/platforms/Makefile > @@ -1,2 +1,3 @@ > obj-y += vexpress.o > obj-y += exynos5.o > +obj-y += omap5.o > diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c > new file mode 100644 > index 0000000..eecf35b > --- /dev/null > +++ b/xen/arch/arm/platforms/omap5.c > @@ -0,0 +1,41 @@ > +/* > + * xen/arch/arm/platforma/omap5.c > + * > + * OMAP5 specific settings > + * > + * Chen Baozi <baozich@gmail.com> > + * Copyright (c) 2013 > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributted in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU Gerneral Public License for more details. > + */ > + > +#include <xen/config.h> > +#include <asm/platforms/omap5.h> > +#include <asm/platform.h> > + > +static const char const *omap5_dt_compat[] __initdata > +{ > + "ti,omap5", > + NULL > +}; > + > +PLATFORM_START(omap5, "TI OMAP5") > + .compatible = omap5_dt_compat, > +PLATFORM_END > + > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */ > diff --git a/xen/include/asm-arm/platforms/omap5.h b/xen/include/asm-arm/platforms/omap5.h > new file mode 100644 > index 0000000..fa825b7 > --- /dev/null > +++ b/xen/include/asm-arm/platforms/omap5.h > @@ -0,0 +1,23 @@ > +#ifndef __ASM_ARM_PLATFORMS_OMAP5_H > +#define __ASM_ASM_PLATFORMS_OMAP5_H > + > +/* Constants below is only used in assembly because the DTS is not yet parsed */ > +#ifdef __ASSEMBLY__ > + > +/* GIC Base Address */ > +#define OMAP5_GIC_BASE_ADDRESS 0x48210000 > + > +/* OMAP5432 uEVM machine ID */ > +#define MACH_TYPE_UEVM 3777These 2 values seems unused in your patch series. Do you plan to use it in the future?> +#endif /* __ASSEMBLY__ */ > + > +#endif /* __ASM_ARM_PLATFORMS_OMAP5_H */ > +/* > + * Local variables: > + * mode: C > + * c-file-style: "BSD" > + * c-basic-offset: 4 > + * indent-tabs-mode: nil > + * End: > + */-- Julien Grall
Julien Grall
2013-Aug-06 22:14 UTC
Re: [PATCH 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote:> Signed-off-by: Chen Baozi <baozich@gmail.com> > --- > xen/arch/arm/platforms/omap5.c | 72 +++++++++++++++++++++++++++++++++++ > xen/arch/arm/time.c | 7 +++- > xen/include/asm-arm/platforms/omap5.h | 15 ++++++++ > 3 files changed, 93 insertions(+), 1 deletion(-) > > diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c > index eecf35b..568b53d 100644 > --- a/xen/arch/arm/platforms/omap5.c > +++ b/xen/arch/arm/platforms/omap5.c > @@ -20,6 +20,77 @@ > #include <xen/config.h> > #include <asm/platforms/omap5.h> > #include <asm/platform.h> > +#include <xen/mm.h> > +#include <xen/vmap.h> > + > +static uint16_t num_den[8][2] = { > + { 0, 0 }, /* not used */ > + { 26 * 64, 26 * 125 }, /* 12.0 Mhz */ > + { 2 * 768, 2 * 1625 }, /* 13.0 Mhz */ > + { 0, 0 }, /* not used */ > + { 130 * 8, 130 * 25 }, /* 19.2 Mhz */ > + { 2 * 384, 2 * 1625 }, /* 26.0 Mhz */ > + { 3 * 256, 3 * 1125 }, /* 27.0 Mhz */ > + { 130 * 4, 130 * 25 }, /* 38.4 Mhz */ > +}; > + > +/* > + * The realtime counter also called master counter, is a free-running > + * counter, which is related to real time. It produces the count used > + * by the CPU local timer peripherals in teh MPU cluster. The timer counts > + * at a rate of 6.144 MHz. Because the device operates on different clocks > + * in different power modes, the master counter shifts operation between > + * clocks, adjusting the increment per clock in hardware accordingly to > + * maintain a constant count rate. > + */ > +static int omap5_init_time(void) > +{ > + void __iomem *ckgen_prm_base; > + void __iomem *rt_ct_base; > + unsigned int sys_clksel; > + unsigned int num, den, frac1, frac2; > + > + ckgen_prm_base = ioremap_attr(OMAP5_CKGEN_PRM_BASE, > + 0x20, PAGE_HYPERVISOR_NOCACHE); > + if (!ckgen_prm_base) { > + dprintk(XENLOG_ERR, "%s: PRM_BASE ioremap failed\n", __func__); > + return -ENOMEM; > + } > + > + sys_clksel = ioreadl(ckgen_prm_base + OMAP5_CM_CLKSEL_SYS) & > + ~SYS_CLKSEL_MASK; > + > + iounmap(ckgen_prm_base); > + > + rt_ct_base = ioremap_attr(REALTIME_COUNTER_BASE, > + 0x20, PAGE_HYPERVISOR_NOCACHE); > + if (!rt_ct_base) { > + dprintk(XENLOG_ERR, "%s: REALTIME_COUNTER_BASE ioremap failed\n", __func__); > + return -ENOMEM; > + } > + > + frac1 = ioreadl(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET); > + num = frac1 & ~NUMERATOR_DENUMERATOR_MASK; > + if (num_den[sys_clksel][0] != num) { > + frac1 &= NUMERATOR_DENUMERATOR_MASK; > + frac1 |= num_den[sys_clksel][0]; > + } > + > + frac2 = ioreadl(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); > + den = frac2 & ~NUMERATOR_DENUMERATOR_MASK; > + if (num_den[sys_clksel][1] != num) { > + frac2 &= NUMERATOR_DENUMERATOR_MASK; > + frac2 |= num_den[sys_clksel][1]; > + } > + > + iowritel(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET, frac1); > + iowritel(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET, > + frac2 | PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD); > + > + iounmap(rt_ct_base); > + > + return 0; > +} > > static const char const *omap5_dt_compat[] __initdata > { > @@ -29,6 +100,7 @@ static const char const *omap5_dt_compat[] __initdata > > PLATFORM_START(omap5, "TI OMAP5") > .compatible = omap5_dt_compat, > + .init_time = omap5_init_time, > PLATFORM_END > > /* > diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c > index 4ed7882..6ca030a 100644 > --- a/xen/arch/arm/time.c > +++ b/xen/arch/arm/time.c > @@ -104,6 +104,7 @@ int __init init_xen_time(void) > struct dt_device_node *dev; > int res; > unsigned int i; > + const __be32 *rate; > > dev = dt_find_compatible_node(NULL, NULL, "arm,armv7-timer"); > if ( !dev ) > @@ -134,7 +135,11 @@ int __init init_xen_time(void) > if ( !cpu_has_gentimer ) > panic("CPU does not support the Generic Timer v1 interface.\n"); > > - cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; > + rate = dt_get_property(dev, "clock-frequency", NULL);You need to check if the length match the size of rate. Perhaps, you can add an helper dt_property_read_u32 (see linux/include/linux/of.h).> + if (rate) > + cpu_khz = be32_to_cpup(rate) / 1000; > + else > + cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; > > boot_count = READ_SYSREG64(CNTPCT_EL0); > printk("Using generic timer at %lu KHz\n", cpu_khz); > diff --git a/xen/include/asm-arm/platforms/omap5.h b/xen/include/asm-arm/platforms/omap5.h > index fa825b7..41d178e 100644 > --- a/xen/include/asm-arm/platforms/omap5.h > +++ b/xen/include/asm-arm/platforms/omap5.h > @@ -1,6 +1,21 @@ > #ifndef __ASM_ARM_PLATFORMS_OMAP5_H > #define __ASM_ASM_PLATFORMS_OMAP5_H > > +#define REALTIME_COUNTER_BASE 0x48243200 > +#define INCREMENTER_NUMERATOR_OFFSET 0x10 > +#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 > +#define NUMERATOR_DENUMERATOR_MASK 0xfffff000 > +#define PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD 0x00010000 > + > +#define OMAP5_L4_WKUP 0x4AE00000 > +#define OMAP5_PRM_BASE (OMAP5_L4_WKUP + 0x6000) > +#define OMAP5_CKGEN_PRM_BASE (OMAP5_PRM_BASE + 0x100) > +#define OMAP5_CM_CLKSEL_SYS 0x10 > +#define SYS_CLKSEL_MASK 0xfffffff8 > + > +/* Timer''s frequency */ > +#define OMAP5_TIMER_FREQUENCY 6144000 /* 6.144 Mhz*/Do you use this define somewhere? -- Julien Grall
On Aug 7, 2013, at 3:14 AM, Julien Grall <julien.grall@linaro.org> wrote:> On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote: >> TI OMAP UART introduces some features such as register access modes, which >> makes its configuration and interrupt handling differs from 8250 compatible >> UART. Thus, we seperate this driver from ns16550''s implementation. > > On your previous version of this patch series you use a modified ns16550, > why didn''t you continue in the same way?I used to think that OMAP UART is 8250 compatible with just a few additional registers. However, since I read the manual carefully last weekend, I found it rather different than a common 8250 UART, especially switching different register access modes to do do initialization and disable THRE interrupt after finishing tx. Those features would make the modified ns16550 share less common codes between X86 and ARM. What''s more, OMAP''s UART codes cannot be reused on other ARM platform such as suni6. So I think it would be better to separate it into a new driver and leave ns16550 as the driver for a more common 8250 UART such as suni6.> >> Signed-off-by: Chen Baozi <baozich@gmail.com> >> --- >> config/arm32.mk | 1 + >> xen/drivers/char/Makefile | 1 + >> xen/drivers/char/omap-uart.c | 358 +++++++++++++++++++++++++++++++++++++++++++ >> xen/include/xen/8250-uart.h | 74 ++++++++- >> 4 files changed, 431 insertions(+), 3 deletions(-) >> create mode 100644 xen/drivers/char/omap-uart.c >> >> diff --git a/config/arm32.mk b/config/arm32.mk >> index 8e21158..76e229d 100644 >> --- a/config/arm32.mk >> +++ b/config/arm32.mk >> @@ -11,6 +11,7 @@ CFLAGS += -marm >> >> HAS_PL011 := y >> HAS_EXYNOS4210 := y >> +HAS_OMAP := y >> >> # Use only if calling $(LD) directly. >> LDFLAGS_DIRECT += -EL >> diff --git a/xen/drivers/char/Makefile b/xen/drivers/char/Makefile >> index 37543f0..911b788 100644 >> --- a/xen/drivers/char/Makefile >> +++ b/xen/drivers/char/Makefile >> @@ -2,6 +2,7 @@ obj-y += console.o >> obj-$(HAS_NS16550) += ns16550.o >> obj-$(HAS_PL011) += pl011.o >> obj-$(HAS_EXYNOS4210) += exynos4210-uart.o >> +obj-$(HAS_OMAP) += omap-uart.o >> obj-$(HAS_EHCI) += ehci-dbgp.o >> obj-$(CONFIG_ARM) += dt-uart.o >> obj-y += serial.o >> diff --git a/xen/drivers/char/omap-uart.c b/xen/drivers/char/omap-uart.c >> new file mode 100644 >> index 0000000..a8cbcc7 >> --- /dev/null >> +++ b/xen/drivers/char/omap-uart.c >> @@ -0,0 +1,358 @@ >> +/* >> + * omap-uart.c >> + * Based on drivers/char/ns16550.c >> + * >> + * Driver for OMAP-UART contorller >> + * >> + * Copyright (C) 2012, Chen Baozi <baozich@gmail.com> >> + * >> + * Note: This driver is made separate from 16550-series UART driver as >> + * omap platform has some specific configurations >> + */ >> + >> +#include <xen/config.h> >> +#include <xen/console.h> >> +#include <xen/serial.h> >> +#include <xen/init.h> >> +#include <xen/irq.h> >> +#include <asm/early_printk.h> >> +#include <xen/device_tree.h> >> +#include <asm/device.h> >> +#include <xen/errno.h> >> +#include <xen/mm.h> >> +#include <xen/vmap.h> >> +#include <xen/8250-uart.h> >> + >> +static struct omap_uart { >> + u32 baud, clock_hz, data_bits, parity, stop_bits, fifo_size; >> + struct dt_irq irq; >> + volatile uint32_t *regs; >> + struct irqaction irqaction; >> + >> + u32 dll; >> + u32 ier; >> + u32 dlh; >> + u32 fcr; >> + u32 efr; >> + u32 lcr; >> + u32 mcr; >> + u32 mdr1; >> + u32 scr; >> + >> +} omap_com = {0}; >> + >> +static void omap_uart_interrupt(int irq, void *data, struct cpu_user_regs *regs) >> +{ >> + struct serial_port *port = data; >> + struct omap_uart *uart = port->uart; >> + u32 lsr; >> + >> + do >> + { > > Why do you change the while by a do-while?Hmmm, it is due to the intermediate implementation of this function. I used to check LSR status in the loop statement, where lsr should be loaded before reaching the statement. After times of debugging/modifications, it comes to be the situation as present, but keep the old do-while structure... If there are any coding-style problems, I''m OK to change it to the while…> >> + lsr = uart->regs[UART_LSR] & 0xff; > > Please use ioread{l,w,...} instead of uart->regs[...]. Same for > everywhere in you driver.No problem. Any potential hazard using uart->regs[...]?> >> + if (lsr & UART_LSR_THRE) >> + serial_tx_interrupt(port, regs); >> + if (lsr & UART_LSR_DR) >> + serial_rx_interrupt(port, regs); >> + >> + if ( port->txbufc == port->txbufp ) { > Unnecessary bracket. >> + uart->regs[UART_IER] = UART_IER_ERDAI | UART_IER_ELSI; >> + } >> + } while (!(uart->regs[UART_IIR] & UART_IIR_NOINT)); >> + >> + >> +} >> + >> +static void baud_protocol_setup(struct omap_uart *uart) >> +{ >> + /* >> + * Switch to register configuration mode B to access the UART_OMAP_EFR >> + * register. >> + */ >> + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B; >> + /* >> + * Enable access to the UART_IER[7:4] bit field. >> + */ >> + uart->efr = uart->regs[UART_OMAP_EFR]; >> + uart->regs[UART_OMAP_EFR] = uart->efr | UART_OMAP_EFR_ECB; >> + /* >> + * Switch to register operation mode to access the UART_IER register. >> + */ >> + uart->regs[UART_LCR] = 0x0; >> + /* >> + * Clear the UART_IER register (set the UART_IER[4] SLEEP_MODE bit >> + * to 0 to change the UART_DLL and UART_DLM register). Set the >> + * UART_IER register value to 0x0000. >> + */ >> + uart->regs[UART_IER] = 0x0; >> + /* >> + * Switch to register configuartion mode B to access the UART_DLL and >> + * UART_DLM registers. >> + */ >> + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B; >> + /* >> + * Load divisor value. >> + */ >> + uart->regs[UART_DLL] = uart->dll; >> + uart->regs[UART_DLM] = uart->dlh; >> + /* >> + * Restore the UART_OMAP_EFR >> + */ >> + uart->regs[UART_OMAP_EFR] = uart->efr; >> + /* >> + * Load the new protocol formatting (parity, stop-bit, character length) >> + * and switch to register operational mode. >> + */ >> + uart->regs[UART_LCR] = uart->lcr; >> +} >> + >> +static void fifo_setup(struct omap_uart *uart) >> +{ >> + /* >> + * Switch to register configuration mode B to access the UART_OMAP_EFR >> + * register. >> + */ >> + uart->lcr = uart->regs[UART_LCR]; >> + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B; >> + /* >> + * Enable register submode TCR_TLR to access the UART_OMAP_TLR register. >> + */ >> + uart->efr = uart->regs[UART_OMAP_EFR]; >> + uart->regs[UART_OMAP_EFR] = uart->efr | UART_OMAP_EFR_ECB; >> + /* >> + * Switch to register configuration mode A to access the UART_MCR >> + * register. >> + */ >> + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_A; >> + /* >> + * Enable register submode TCR_TLR to access the UART_OMAP_TLR register >> + */ >> + uart->mcr = uart->regs[UART_MCR]; >> + uart->regs[UART_MCR] = uart->mcr | UART_MCR_TCRTLR; >> + /* >> + * Enable the FIFO; load the new FIFO trigger and the new DMA mode. >> + */ >> + uart->regs[UART_FCR] = uart->fcr; >> + /* >> + * Switch to register configuration mode B to access the UART_EFR >> + * register. >> + */ >> + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_B; >> + /* >> + * Load the new FIFO triggers and the new DMA mode bit. >> + */ >> + uart->regs[UART_OMAP_SCR] = uart->scr; >> + /* >> + * Restore the UART_OMAP_EFR[4] value. >> + */ >> + uart->regs[UART_OMAP_EFR] = uart->efr; >> + /* >> + * Switch to register configuration mode A to access the UART_MCR >> + * register. >> + */ >> + uart->regs[UART_LCR] = UART_LCR_CONF_MODE_A; >> + /* >> + * Restore UART_MCR[6] value. >> + */ >> + uart->regs[UART_MCR] = uart->mcr; >> + /* >> + * Restore UART_LCR value. >> + */ >> + uart->regs[UART_LCR] = uart->lcr; >> +} >> + >> +static void __init omap_uart_init_preirq(struct serial_port *port) >> +{ >> + struct omap_uart *uart = port->uart; >> + unsigned int divisor; >> + >> + /* >> + * Clear the FIFO buffers. >> + */ >> + uart->regs[UART_FCR] = UART_FCR_ENABLE; >> + uart->regs[UART_FCR] = UART_FCR_ENABLE | UART_FCR_CLRX | UART_FCR_CLTX; >> + uart->regs[UART_FCR] = 0; >> + >> + /* >> + * Calculate desired value. >> + */ >> + divisor = uart->clock_hz / (uart->baud << 4); >> + uart->dll = divisor & 0xff; >> + uart->dlh = divisor >> 8; >> + uart->lcr = (uart->data_bits - 5) | ((uart->stop_bits - 1) << 2) | uart->parity; >> + uart->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_10 | UART_FCR_ENABLE; >> + uart->scr = OMAP_UART_SCR_RX_TRIG_GRANU1_MASK; >> + uart->ier = UART_IER_ERDAI | UART_IER_ETHREI | UART_IER_ELSI; > > You are wasting space just to store hardcoded value (for fcr, scr, > ier). You should use macro. > >> + >> + /* >> + * The TRM says the mode should be disabled while UART_DLL and UART_DHL >> + * are being changed so we disable before setup, then enable. >> + */ >> + uart->regs[UART_OMAP_MDR1] = UART_OMAP_MDR1_DISABLE; >> + >> + /* Baud rate & protocol format setup */ >> + baud_protocol_setup(uart); >> + >> + /* FIFO setup */ >> + fifo_setup(uart); >> + >> + /* No flow control */ >> + uart->regs[UART_MCR] = UART_MCR_DTR | UART_MCR_RTS; >> + >> + uart->regs[UART_OMAP_MDR1] = UART_OMAP_MDR1_16X_MODE; >> + >> + uart->fifo_size = 64; >> +} >> + >> +static void __init omap_uart_init_postirq(struct serial_port *port) >> +{ >> + struct omap_uart *uart = port->uart; >> + >> + uart->irqaction.handler = omap_uart_interrupt; >> + uart->irqaction.name = "omap_uart"; >> + uart->irqaction.dev_id = port; >> + >> + if (setup_dt_irq(&uart->irq, &uart->irqaction) != 0) > > Missing space for the if. > if ( a ) ... > >> + dprintk(XENLOG_ERR, "Failed to allocated omap_uart IRQ %d\n", >> + uart->irq.irq); >> + >> + /* Enable interrupts */ >> + uart->regs[UART_IER] = uart->ier; > > Don''t enable IRQ if setup has failed. > >> +} >> + >> +static void omap_uart_suspend(struct serial_port *port) >> +{ >> + BUG(); >> +} >> + >> +static void omap_uart_resume(struct serial_port *port) >> +{ >> + BUG(); >> +} >> + >> +static unsigned int omap_uart_tx_ready(struct serial_port *port) >> +{ >> + struct omap_uart *uart = port->uart; >> + >> + uart->regs[UART_IER] = uart->ier; >> + >> + return uart->regs[UART_LSR] & UART_LSR_THRE ? uart->fifo_size : 0; >> +} >> + >> +static void omap_uart_putc(struct serial_port *port, char c) >> +{ >> + struct omap_uart *uart = port->uart; >> + >> + uart->regs[UART_THR] = (uint32_t)(unsigned char) c; >> +} >> + >> +static int omap_uart_getc(struct serial_port *port, char *pc) >> +{ >> + struct omap_uart *uart = port->uart; >> + >> + if (!(uart->regs[UART_LSR] & UART_LSR_DR)) > Missing space for the if. > >> + return 0; >> + >> + *pc = uart->regs[UART_RBR] & 0xff; >> + return 1; >> +} >> + >> +static int __init omap_uart_irq(struct serial_port *port) >> +{ >> + struct omap_uart *uart = port->uart; >> + >> + return ((uart->irq.irq > 0) ? uart->irq.irq : -1); >> +} >> + >> +static const struct dt_irq __init *omap_uart_dt_irq(struct serial_port *port) >> +{ >> + struct omap_uart *uart = port->uart; >> + >> + return &uart->irq; >> +} >> + >> +static struct uart_driver __read_mostly omap_uart_driver = { >> + .init_preirq = omap_uart_init_preirq, >> + .init_postirq = omap_uart_init_postirq, >> + .endboot = NULL, >> + .suspend = omap_uart_suspend, >> + .resume = omap_uart_resume, >> + .tx_ready = omap_uart_tx_ready, >> + .putc = omap_uart_putc, >> + .getc = omap_uart_getc, >> + .irq = omap_uart_irq, >> + .dt_irq_get = omap_uart_dt_irq, >> +}; >> + >> +static int __init omap_uart_init(struct dt_device_node *dev, >> + const void *data) >> +{ >> + const char *config = data; >> + struct omap_uart *uart; >> + const __be32 *clkspec; >> + int res; >> + u64 addr, size; >> + >> + if (strcmp(config, "")) >> + early_printk("WARNING: UART configuration is not supported\n"); >> + >> + uart = &omap_com; >> + >> + clkspec = dt_get_property(dev, "clock-frequency", NULL); >> + if (clkspec == NULL) { >> + early_printk("omap-uart: Unable to retrieve the clock frequency\n"); >> + return -EINVAL; >> + } >> + >> + uart->clock_hz = be32_to_cpup(clkspec); >> + uart->baud = 115200; >> + uart->data_bits = 8; >> + uart->parity = UART_PARITY_NONE; >> + uart->stop_bits = 1; >> + >> + res = dt_device_get_address(dev, 0, &addr, &size); >> + if (res) { > The bracket needs to be on a new line. >> + early_printk("omap-uart: Unable to retrieve the base" >> + " address of the UART\n"); >> + return res; >> + } >> + >> + uart->regs = ioremap_attr(addr, size, PAGE_HYPERVISOR_NOCACHE); >> + if (!uart->regs) { > > Missing space and bracket in newline. > >> + early_printk("omap-uart: Unable to map the UART memory\n"); >> + return -ENOMEM; >> + } >> + >> + res = dt_device_get_irq(dev, 0, &uart->irq); >> + if (res) { > Same here. >> + early_printk("omap-uart: Unable to retrieve the IRQ\n"); >> + return res; >> + } >> + >> + /* Register with generic serial driver */ >> + serial_register_uart(SERHND_DTUART, &omap_uart_driver, uart); >> + >> + dt_device_set_used_by(dev, DOMID_XEN); >> + >> + return 0; >> +} >> + >> +static const char const *omap_uart_dt_compat[] __initdata >> +{ >> + "ti,omap4-uart", >> + NULL >> +}; >> + >> +DT_DEVICE_START(omap_uart, "OMAP UART", DEVICE_SERIAL) >> + .compatible = omap_uart_dt_compat, >> + .init = omap_uart_init, >> +DT_DEVICE_END >> + >> +/* >> + * Local variables: >> + * mode: C >> + * c-file-style: "BSD" >> + * c-basic-offset: 4 >> + * indent-tabs-mode: nil >> + * End: >> + */ >> diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h >> index 0e6c6bd..a75f36a 100644 >> --- a/xen/include/xen/8250-uart.h >> +++ b/xen/include/xen/8250-uart.h >> @@ -60,19 +60,55 @@ >> #define UART_FCR_CLRX 0x02 /* clear Rx FIFO */ >> #define UART_FCR_CLTX 0x04 /* clear Tx FIFO */ >> #define UART_FCR_DMA 0x10 /* enter DMA mode */ >> + >> #define UART_FCR_TRG1 0x00 /* Rx FIFO trig lev 1 */ >> #define UART_FCR_TRG4 0x40 /* Rx FIFO trig lev 4 */ >> #define UART_FCR_TRG8 0x80 /* Rx FIFO trig lev 8 */ >> #define UART_FCR_TRG14 0xc0 /* Rx FIFO trig lev 14 */ >> >> +/* >> + * Note: The FIFO trigger levels are chip specific: >> + * RX:76 = 00 01 10 11 TX:54 = 00 01 10 11 >> + * PC16550D: 1 4 8 14 xx xx xx xx >> + * TI16C550A: 1 4 8 14 xx xx xx xx >> + * TI16C550C: 1 4 8 14 xx xx xx xx >> + * ST16C550: 1 4 8 14 xx xx xx xx >> + * ST16C650: 8 16 24 28 16 8 24 30 PORT_16650V2 >> + * NS16C552: 1 4 8 14 xx xx xx xx >> + * ST16C654: 8 16 56 60 8 16 32 56 PORT_16654 >> + * TI16C750: 1 16 32 56 xx xx xx xx PORT_16750 >> + * TI16C752: 8 16 56 60 8 16 32 56 >> + * Tegra: 1 4 8 14 16 8 4 1 PORT_TEGRA >> + */ >> +#define UART_FCR_R_TRIG_00 0x00 >> +#define UART_FCR_R_TRIG_01 0x40 >> +#define UART_FCR_R_TRIG_10 0x80 >> +#define UART_FCR_R_TRIG_11 0xc0 >> +#define UART_FCR_T_TRIG_00 0x00 >> +#define UART_FCR_T_TRIG_01 0x10 >> +#define UART_FCR_T_TRIG_10 0x20 >> +#define UART_FCR_T_TRIG_11 0x30 >> + >> /* Line Control Register */ >> #define UART_LCR_DLAB 0x80 /* Divisor Latch Access */ >> >> +/* >> + * Access to some registers depends on register access / configuration >> + * mode. >> + */ >> +#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ >> +#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ >> + >> /* Modem Control Register */ >> -#define UART_MCR_DTR 0x01 /* Data Terminal Ready */ >> -#define UART_MCR_RTS 0x02 /* Request to Send */ >> -#define UART_MCR_OUT2 0x08 /* OUT2: interrupt mask */ >> +#define UART_MCR_CLKSEL 0x80 /* Divide clock by 4 (TI16C752, EFR[4]=1) */ >> +#define UART_MCR_TCRTLR 0x40 /* Access TCR/TLR (TI16C752, EFR[4]=1) */ >> +#define UART_MCR_XONANY 0x20 /* Enable Xon Any (TI16C752, EFR[4]=1) */ > > Don''t add unnecessary define. > >> +#define UART_MCR_AFE 0x20 /* Enable auto-RTS/CTS (TI16C550C/TI16C750) */ >> #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */ >> +#define UART_MCR_OUT2 0x08 /* Out2 complement */ >> +#define UART_MCR_OUT1 0x04 /* Out1 complement */ >> +#define UART_MCR_RTS 0x02 /* RTS complement */ >> +#define UART_MCR_DTR 0x01 /* DTR complement */ >> >> /* Line Status Register */ >> #define UART_LSR_DR 0x01 /* Data ready */ >> @@ -98,6 +134,38 @@ >> #define RESUME_DELAY MILLISECS(10) >> #define RESUME_RETRIES 100 >> >> +/* Enhanced feature register */ >> +#define UART_OMAP_EFR 0x02 >> + >> +#define UART_OMAP_EFR_CTS 0x80 /* CTS flow control */ >> +#define UART_OMAP_EFR_RTS 0x40 /* RTS flow control */ >> +#define UART_OMAP_EFR_SCD 0x20 /* Special character detect */ >> +#define UART_OMAP_EFR_ECB 0x10 /* Enhanced control bit */ >> + >> +/* Mode definition register 1 */ >> +#define UART_OMAP_MDR1 0x08 >> + >> +/* >> + * These are the definitions for the MDR1 register >> + */ >> +#define UART_OMAP_MDR1_16X_MODE 0x00 /* UART 16x mode */ >> +#define UART_OMAP_MDR1_SIR_MODE 0x01 /* SIR mode */ >> +#define UART_OMAP_MDR1_16X_ABAUD_MODE 0x02 /* UART 16x auto-baud */ >> +#define UART_OMAP_MDR1_13X_MODE 0x03 /* UART 13x mode */ >> +#define UART_OMAP_MDR1_MIR_MODE 0x04 /* MIR mode */ >> +#define UART_OMAP_MDR1_FIR_MODE 0x05 /* FIR mode */ >> +#define UART_OMAP_MDR1_CIR_MODE 0x06 /* CIR mode */ >> +#define UART_OMAP_MDR1_DISABLE 0x07 /* Disable (default state) */ >> + >> +/* Supplementary control register */ >> +#define UART_OMAP_SCR 0x10 >> + >> +/* SCR register bitmasks */ >> +#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7) >> +#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6) >> +#define OMAP_UART_SCR_TX_EMPTY (1 << 3) >> + >> + >> #endif /* __XEN_8250_UART_H__ */ >> >> /*Thanks for reviewing. I''ll rework and resend it later. Cheers, Baozi
Chen Baozi
2013-Aug-07 03:22 UTC
Re: [PATCH 2/5] xen/arm: add OMAP5432 UART support for early_printk
On Aug 7, 2013, at 5:50 AM, Julien Grall <julien.grall@linaro.org> wrote:> Add Bamvor. > > On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote: >> Signed-off-by: Chen Baozi <baozich@gmail.com> >> --- >> docs/misc/arm/early-printk.txt | 1 + >> xen/arch/arm/Rules.mk | 4 ++++ >> xen/arch/arm/arm32/debug-8250.inc | 41 +++++++++++++++++++++++++++++++++++++++ >> xen/include/xen/8250-uart.h | 6 ++++++ >> 4 files changed, 52 insertions(+) >> create mode 100644 xen/arch/arm/arm32/debug-8250.inc >> >> diff --git a/docs/misc/arm/early-printk.txt b/docs/misc/arm/early-printk.txt >> index fbc3208..874488f 100644 >> --- a/docs/misc/arm/early-printk.txt >> +++ b/docs/misc/arm/early-printk.txt >> @@ -13,6 +13,7 @@ where mach is the name of the machine: >> - exynos5250: printk with the second UART >> - midway: printk with the pl011 on Calxeda Midway processors >> - fastmodel: printk on ARM Fastmodel software emulators >> + - omap5432: printk with UART3 on TI OMAP5432 processors > > This patch looks similar to > http://lists.xen.org/archives/html/xen-devel/2013-07/msg00194.html. > Could you also add suni6 support?No problem. Sorry, I forgot to cc to Bamvor. It is OK for me either using Bamvor''s patch with OMAP support or mine with suni6 support.> >> >> The base address and baud rate is hardcoded in xen/arch/arm/Rules.mk, >> see there when adding support for new machines. >> diff --git a/xen/arch/arm/Rules.mk b/xen/arch/arm/Rules.mk >> index a18e7fd..346c824 100644 >> --- a/xen/arch/arm/Rules.mk >> +++ b/xen/arch/arm/Rules.mk >> @@ -64,6 +64,10 @@ EARLY_PRINTK_INC := pl011 >> EARLY_PRINTK_BAUD := 115200 >> EARLY_UART_BASE_ADDRESS := 0xfff36000 >> endif >> +ifeq ($(CONFIG_EARLY_PRINTK), omap5432) >> +EARLY_PRINTK_INC := 8250 >> +EARLY_UART_BASE_ADDRESS := 0x48020000 >> +endif >> >> ifneq ($(EARLY_PRINTK_INC),) >> EARLY_PRINTK := y >> diff --git a/xen/arch/arm/arm32/debug-8250.inc b/xen/arch/arm/arm32/debug-8250.inc >> new file mode 100644 >> index 0000000..955d90c >> --- /dev/null >> +++ b/xen/arch/arm/arm32/debug-8250.inc >> @@ -0,0 +1,41 @@ >> +/* >> + * xen/arch/arm/arm32/debug-8250.inc >> + * >> + * 8250 specific debug code >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation; either version 2 of the License, or >> + * (at your option) any later version. >> + * >> + * This program is distributed in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU General Public License for more details. >> + */ >> + >> +#include <xen/8250-uart.h> >> + >> +/* OMAP UART wait UART to be ready to transmit > s/OMAP/8250/ >> + * rb: register which contains the UART base address >> + * rc: scratch register */ >> +.macro early_uart_ready rb rc >> +1: >> + ldr \rc, [\rb, #(UART_LSR << REG_SHIFT)] /* Read LSR */ >> + tst \rc, #UART_LSR_THRE /* Check Xmit holding register flag */ >> + beq 1b /* Wait for the UART to be ready */ >> +.endm >> + >> +/* OMAP UART transmit character > Same here. >> + * rb: register which contains the UART base address >> + * rt: register which contains the character to transmit */ >> +.macro early_uart_transmit rb rt >> + str \rt, [\rb, #UART_THR] /* Write Transmit buffer */ >> +.endm >> + >> +/* >> + * Local variables: >> + * mode: ASM >> + * indent-tabs-mode: nil >> + * End: >> + */ >> diff --git a/xen/include/xen/8250-uart.h b/xen/include/xen/8250-uart.h >> index 7287364..0e6c6bd 100644 >> --- a/xen/include/xen/8250-uart.h >> +++ b/xen/include/xen/8250-uart.h >> @@ -22,6 +22,12 @@ >> #ifndef __XEN_8250_UART_H__ >> #define __XEN_8250_UART_H__ >> >> +#ifdef CONFIG_ARM >> +#define REG_SHIFT 2 >> +#else >> +#define REG_SHIFT 0 >> +#endif > > If you don''t use REG_SHIFT in other code than ARM, you can remove > the #else. > >> /* Register offsets */ >> #define UART_RBR 0x00 /* receive buffer */ >> #define UART_THR 0x00 /* transmit holding */ > > -- > Julien Grall
Chen Baozi
2013-Aug-07 03:24 UTC
Re: [PATCH 4/5] xen/arm: Introduce platform recognition codes for the OMAP5
On Aug 7, 2013, at 6:00 AM, Julien Grall <julien.grall@linaro.org> wrote:> On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote: >> Signed-off-by: Chen Baozi <baozich@gmail.com> >> --- >> xen/arch/arm/platforms/Makefile | 1 + >> xen/arch/arm/platforms/omap5.c | 41 +++++++++++++++++++++++++++++++++++ >> xen/include/asm-arm/platforms/omap5.h | 23 ++++++++++++++++++++ >> 3 files changed, 65 insertions(+) >> create mode 100644 xen/arch/arm/platforms/omap5.c >> create mode 100644 xen/include/asm-arm/platforms/omap5.h >> >> diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile >> index ff2b65b..90ddcb1 100644 >> --- a/xen/arch/arm/platforms/Makefile >> +++ b/xen/arch/arm/platforms/Makefile >> @@ -1,2 +1,3 @@ >> obj-y += vexpress.o >> obj-y += exynos5.o >> +obj-y += omap5.o >> diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c >> new file mode 100644 >> index 0000000..eecf35b >> --- /dev/null >> +++ b/xen/arch/arm/platforms/omap5.c >> @@ -0,0 +1,41 @@ >> +/* >> + * xen/arch/arm/platforma/omap5.c >> + * >> + * OMAP5 specific settings >> + * >> + * Chen Baozi <baozich@gmail.com> >> + * Copyright (c) 2013 >> + * >> + * This program is free software; you can redistribute it and/or modify >> + * it under the terms of the GNU General Public License as published by >> + * the Free Software Foundation; either version 2 of the License, or >> + * (at your option) any later version. >> + * >> + * This program is distributted in the hope that it will be useful, >> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >> + * GNU Gerneral Public License for more details. >> + */ >> + >> +#include <xen/config.h> >> +#include <asm/platforms/omap5.h> >> +#include <asm/platform.h> >> + >> +static const char const *omap5_dt_compat[] __initdata >> +{ >> + "ti,omap5", >> + NULL >> +}; >> + >> +PLATFORM_START(omap5, "TI OMAP5") >> + .compatible = omap5_dt_compat, >> +PLATFORM_END >> + >> +/* >> + * Local variables: >> + * mode: C >> + * c-file-style: "BSD" >> + * c-basic-offset: 4 >> + * indent-tabs-mode: nil >> + * End: >> + */ >> diff --git a/xen/include/asm-arm/platforms/omap5.h b/xen/include/asm-arm/platforms/omap5.h >> new file mode 100644 >> index 0000000..fa825b7 >> --- /dev/null >> +++ b/xen/include/asm-arm/platforms/omap5.h >> @@ -0,0 +1,23 @@ >> +#ifndef __ASM_ARM_PLATFORMS_OMAP5_H >> +#define __ASM_ASM_PLATFORMS_OMAP5_H >> + >> +/* Constants below is only used in assembly because the DTS is not yet parsed */ >> +#ifdef __ASSEMBLY__ >> + >> +/* GIC Base Address */ >> +#define OMAP5_GIC_BASE_ADDRESS 0x48210000 >> + >> +/* OMAP5432 uEVM machine ID */ >> +#define MACH_TYPE_UEVM 3777 > > These 2 values seems unused in your patch series. Do you plan to use > it in the future?Yes, it will be used in SMP boot codes, which I''m now working on. Or, should I add this macros in the SMP boot patch?> >> +#endif /* __ASSEMBLY__ */ >> + >> +#endif /* __ASM_ARM_PLATFORMS_OMAP5_H */ >> +/* >> + * Local variables: >> + * mode: C >> + * c-file-style: "BSD" >> + * c-basic-offset: 4 >> + * indent-tabs-mode: nil >> + * End: >> + */ > > -- > Julien Grall
Chen Baozi
2013-Aug-07 03:28 UTC
Re: [PATCH 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
On Aug 7, 2013, at 6:14 AM, Julien Grall <julien.grall@linaro.org> wrote:> On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote: >> Signed-off-by: Chen Baozi <baozich@gmail.com> >> --- >> xen/arch/arm/platforms/omap5.c | 72 +++++++++++++++++++++++++++++++++++ >> xen/arch/arm/time.c | 7 +++- >> xen/include/asm-arm/platforms/omap5.h | 15 ++++++++ >> 3 files changed, 93 insertions(+), 1 deletion(-) >> >> diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c >> index eecf35b..568b53d 100644 >> --- a/xen/arch/arm/platforms/omap5.c >> +++ b/xen/arch/arm/platforms/omap5.c >> @@ -20,6 +20,77 @@ >> #include <xen/config.h> >> #include <asm/platforms/omap5.h> >> #include <asm/platform.h> >> +#include <xen/mm.h> >> +#include <xen/vmap.h> >> + >> +static uint16_t num_den[8][2] = { >> + { 0, 0 }, /* not used */ >> + { 26 * 64, 26 * 125 }, /* 12.0 Mhz */ >> + { 2 * 768, 2 * 1625 }, /* 13.0 Mhz */ >> + { 0, 0 }, /* not used */ >> + { 130 * 8, 130 * 25 }, /* 19.2 Mhz */ >> + { 2 * 384, 2 * 1625 }, /* 26.0 Mhz */ >> + { 3 * 256, 3 * 1125 }, /* 27.0 Mhz */ >> + { 130 * 4, 130 * 25 }, /* 38.4 Mhz */ >> +}; >> + >> +/* >> + * The realtime counter also called master counter, is a free-running >> + * counter, which is related to real time. It produces the count used >> + * by the CPU local timer peripherals in teh MPU cluster. The timer counts >> + * at a rate of 6.144 MHz. Because the device operates on different clocks >> + * in different power modes, the master counter shifts operation between >> + * clocks, adjusting the increment per clock in hardware accordingly to >> + * maintain a constant count rate. >> + */ >> +static int omap5_init_time(void) >> +{ >> + void __iomem *ckgen_prm_base; >> + void __iomem *rt_ct_base; >> + unsigned int sys_clksel; >> + unsigned int num, den, frac1, frac2; >> + >> + ckgen_prm_base = ioremap_attr(OMAP5_CKGEN_PRM_BASE, >> + 0x20, PAGE_HYPERVISOR_NOCACHE); >> + if (!ckgen_prm_base) { >> + dprintk(XENLOG_ERR, "%s: PRM_BASE ioremap failed\n", __func__); >> + return -ENOMEM; >> + } >> + >> + sys_clksel = ioreadl(ckgen_prm_base + OMAP5_CM_CLKSEL_SYS) & >> + ~SYS_CLKSEL_MASK; >> + >> + iounmap(ckgen_prm_base); >> + >> + rt_ct_base = ioremap_attr(REALTIME_COUNTER_BASE, >> + 0x20, PAGE_HYPERVISOR_NOCACHE); >> + if (!rt_ct_base) { >> + dprintk(XENLOG_ERR, "%s: REALTIME_COUNTER_BASE ioremap failed\n", __func__); >> + return -ENOMEM; >> + } >> + >> + frac1 = ioreadl(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET); >> + num = frac1 & ~NUMERATOR_DENUMERATOR_MASK; >> + if (num_den[sys_clksel][0] != num) { >> + frac1 &= NUMERATOR_DENUMERATOR_MASK; >> + frac1 |= num_den[sys_clksel][0]; >> + } >> + >> + frac2 = ioreadl(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET); >> + den = frac2 & ~NUMERATOR_DENUMERATOR_MASK; >> + if (num_den[sys_clksel][1] != num) { >> + frac2 &= NUMERATOR_DENUMERATOR_MASK; >> + frac2 |= num_den[sys_clksel][1]; >> + } >> + >> + iowritel(rt_ct_base + INCREMENTER_NUMERATOR_OFFSET, frac1); >> + iowritel(rt_ct_base + INCREMENTER_DENUMERATOR_RELOAD_OFFSET, >> + frac2 | PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD); >> + >> + iounmap(rt_ct_base); >> + >> + return 0; >> +} >> >> static const char const *omap5_dt_compat[] __initdata >> { >> @@ -29,6 +100,7 @@ static const char const *omap5_dt_compat[] __initdata >> >> PLATFORM_START(omap5, "TI OMAP5") >> .compatible = omap5_dt_compat, >> + .init_time = omap5_init_time, >> PLATFORM_END >> >> /* >> diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c >> index 4ed7882..6ca030a 100644 >> --- a/xen/arch/arm/time.c >> +++ b/xen/arch/arm/time.c >> @@ -104,6 +104,7 @@ int __init init_xen_time(void) >> struct dt_device_node *dev; >> int res; >> unsigned int i; >> + const __be32 *rate; >> >> dev = dt_find_compatible_node(NULL, NULL, "arm,armv7-timer"); >> if ( !dev ) >> @@ -134,7 +135,11 @@ int __init init_xen_time(void) >> if ( !cpu_has_gentimer ) >> panic("CPU does not support the Generic Timer v1 interface.\n"); >> >> - cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; >> + rate = dt_get_property(dev, "clock-frequency", NULL); > > You need to check if the length match the size of rate. > Perhaps, you can add an helper dt_property_read_u32 (see > linux/include/linux/of.h).OK.> >> + if (rate) >> + cpu_khz = be32_to_cpup(rate) / 1000; >> + else >> + cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; >> >> boot_count = READ_SYSREG64(CNTPCT_EL0); >> printk("Using generic timer at %lu KHz\n", cpu_khz); >> diff --git a/xen/include/asm-arm/platforms/omap5.h b/xen/include/asm-arm/platforms/omap5.h >> index fa825b7..41d178e 100644 >> --- a/xen/include/asm-arm/platforms/omap5.h >> +++ b/xen/include/asm-arm/platforms/omap5.h >> @@ -1,6 +1,21 @@ >> #ifndef __ASM_ARM_PLATFORMS_OMAP5_H >> #define __ASM_ASM_PLATFORMS_OMAP5_H >> >> +#define REALTIME_COUNTER_BASE 0x48243200 >> +#define INCREMENTER_NUMERATOR_OFFSET 0x10 >> +#define INCREMENTER_DENUMERATOR_RELOAD_OFFSET 0x14 >> +#define NUMERATOR_DENUMERATOR_MASK 0xfffff000 >> +#define PRM_FRAC_INCREMENTER_DENUMERATOR_RELOAD 0x00010000 >> + >> +#define OMAP5_L4_WKUP 0x4AE00000 >> +#define OMAP5_PRM_BASE (OMAP5_L4_WKUP + 0x6000) >> +#define OMAP5_CKGEN_PRM_BASE (OMAP5_PRM_BASE + 0x100) >> +#define OMAP5_CM_CLKSEL_SYS 0x10 >> +#define SYS_CLKSEL_MASK 0xfffffff8 >> + >> +/* Timer''s frequency */ >> +#define OMAP5_TIMER_FREQUENCY 6144000 /* 6.144 Mhz*/ > > Do you use this define somewhere?Oh, sorry. It is used at initial version of this patch. I should have removed it when switching to DTS value. Cheers, Baozi
On Wed, 2013-08-07 at 11:14 +0800, Chen Baozi wrote:> On Aug 7, 2013, at 3:14 AM, Julien Grall <julien.grall@linaro.org> wrote: > > > On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote: > >> TI OMAP UART introduces some features such as register access modes, which > >> makes its configuration and interrupt handling differs from 8250 compatible > >> UART. Thus, we seperate this driver from ns16550''s implementation. > > > > On your previous version of this patch series you use a modified ns16550, > > why didn''t you continue in the same way? > > I used to think that OMAP UART is 8250 compatible with just a few > additional registers. However, since I read the manual carefully last > weekend, I found it rather different than a common 8250 UART, > especially switching different register access modes to do > do initialization> and disable THRE interrupt after finishing tx.This sounds like something which would perhaps be harmless on all other systems too, or it could be implemented as a quirk within the existing driver.> Those features would make the modified ns16550 share less common > codes between X86 and ARM. What''s more, OMAP''s UART codes cannot be > reused on other ARM platform such as suni6. So I think it would > be better to separate it into a new driver and leave ns16550 as the > driver for a more common 8250 UART such as suni6.It looks like Linux has gone down the same path? The commit in Linux says the reason has to do with DMA setup, and we likely wouldn''t do DMA console in the hypervisor. Anyway, it''s a shame if this code cannot be common but I suppose we can live with it.> > > >> + lsr = uart->regs[UART_LSR] & 0xff; > > > > Please use ioread{l,w,...} instead of uart->regs[...]. Same for > > everywhere in you driver. > > No problem. > > Any potential hazard using uart->regs[...]?It doesn''t have any barriers (compiler or processor) and it isn''t guaranteed (although it is highly likely) that the compiler will implement this as a simple store. pl011 has switched too by the way.> >> > >> +/* > >> + * Access to some registers depends on register access / configuration > >> + * mode. > >> + */ > >> +#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ > >> +#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */"Configuration" twice Ian.
Andrii Anisov
2013-Aug-07 10:25 UTC
Re: [PATCH 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
> > > >> diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c > >> index 4ed7882..6ca030a 100644 > >> --- a/xen/arch/arm/time.c > >> +++ b/xen/arch/arm/time.c > >> @@ -104,6 +104,7 @@ int __init init_xen_time(void) > >> struct dt_device_node *dev; > >> int res; > >> unsigned int i; > >> + const __be32 *rate; > >> > >> dev = dt_find_compatible_node(NULL, NULL, "arm,armv7-timer"); > >> if ( !dev ) > >> @@ -134,7 +135,11 @@ int __init init_xen_time(void) > >> if ( !cpu_has_gentimer ) > >> panic("CPU does not support the Generic Timer v1 interface.\n"); > >> > >> - cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; > >> + rate = dt_get_property(dev, "clock-frequency", NULL); > > > > You need to check if the length match the size of rate. > > Perhaps, you can add an helper dt_property_read_u32 (see > > linux/include/linux/of.h). > > OK. > >I would propose another approach here: just let cpu_khz be set up by architecture code. *Sincerely,* *Andrii Anisov.* _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
Andrii Anisov
2013-Aug-07 10:32 UTC
Re: [PATCH 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
On Wed, Aug 7, 2013 at 1:25 PM, Andrii Anisov <andrii.anisov@globallogic.com> wrote:> >> > You need to check if the length match the size of rate. >> > Perhaps, you can add an helper dt_property_read_u32 (see >> > linux/include/linux/of.h). >> >> OK. >> >> > I would propose another approach here: just let cpu_khz be set up by architecture > code. > >Yep, platform code. *Sincerely,* *Andrii Anisov.* _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
On Aug 7, 2013, at 4:46 PM, Ian Campbell <Ian.Campbell@citrix.com> wrote:> On Wed, 2013-08-07 at 11:14 +0800, Chen Baozi wrote: >> On Aug 7, 2013, at 3:14 AM, Julien Grall <julien.grall@linaro.org> wrote: >> >>> On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote: >>>> TI OMAP UART introduces some features such as register access modes, which >>>> makes its configuration and interrupt handling differs from 8250 compatible >>>> UART. Thus, we seperate this driver from ns16550''s implementation. >>> >>> On your previous version of this patch series you use a modified ns16550, >>> why didn''t you continue in the same way? >> >> I used to think that OMAP UART is 8250 compatible with just a few >> additional registers. However, since I read the manual carefully last >> weekend, I found it rather different than a common 8250 UART, >> especially switching different register access modes to do >> do initialization > > > >> and disable THRE interrupt after finishing tx. > > This sounds like something which would perhaps be harmless on all other > systems too, or it could be implemented as a quirk within the existing > driver. > >> Those features would make the modified ns16550 share less common >> codes between X86 and ARM. What''s more, OMAP''s UART codes cannot be >> reused on other ARM platform such as suni6. So I think it would >> be better to separate it into a new driver and leave ns16550 as the >> driver for a more common 8250 UART such as suni6. > > It looks like Linux has gone down the same path? The commit in Linux > says the reason has to do with DMA setup, and we likely wouldn''t do DMA > console in the hypervisor.After reading the Linux driver, I think the commit log here actually means the DMA feature of OMAP change the setup flow. Cheers, Baozi> > Anyway, it''s a shame if this code cannot be common but I suppose we can > live with it. > >>> >>>> + lsr = uart->regs[UART_LSR] & 0xff; >>> >>> Please use ioread{l,w,...} instead of uart->regs[...]. Same for >>> everywhere in you driver. >> >> No problem. >> >> Any potential hazard using uart->regs[...]? > > It doesn''t have any barriers (compiler or processor) and it isn''t > guaranteed (although it is highly likely) that the compiler will > implement this as a simple store. > > pl011 has switched too by the way. >>>> >>>> +/* >>>> + * Access to some registers depends on register access / configuration >>>> + * mode. >>>> + */ >>>> +#define UART_LCR_CONF_MODE_A UART_LCR_DLAB /* Configutation mode A */ >>>> +#define UART_LCR_CONF_MODE_B 0xBF /* Configutation mode B */ > > "Configuration" twice > > Ian. >
Julien Grall
2013-Aug-07 11:21 UTC
Re: [PATCH 4/5] xen/arm: Introduce platform recognition codes for the OMAP5
On 08/07/2013 04:24 AM, Chen Baozi wrote:> > On Aug 7, 2013, at 6:00 AM, Julien Grall <julien.grall@linaro.org> wrote: > >> On 5 August 2013 12:49, Chen Baozi <baozich@gmail.com> wrote: >>> Signed-off-by: Chen Baozi <baozich@gmail.com> >>> --- >>> xen/arch/arm/platforms/Makefile | 1 + >>> xen/arch/arm/platforms/omap5.c | 41 +++++++++++++++++++++++++++++++++++ >>> xen/include/asm-arm/platforms/omap5.h | 23 ++++++++++++++++++++ >>> 3 files changed, 65 insertions(+) >>> create mode 100644 xen/arch/arm/platforms/omap5.c >>> create mode 100644 xen/include/asm-arm/platforms/omap5.h >>> >>> diff --git a/xen/arch/arm/platforms/Makefile b/xen/arch/arm/platforms/Makefile >>> index ff2b65b..90ddcb1 100644 >>> --- a/xen/arch/arm/platforms/Makefile >>> +++ b/xen/arch/arm/platforms/Makefile >>> @@ -1,2 +1,3 @@ >>> obj-y += vexpress.o >>> obj-y += exynos5.o >>> +obj-y += omap5.o >>> diff --git a/xen/arch/arm/platforms/omap5.c b/xen/arch/arm/platforms/omap5.c >>> new file mode 100644 >>> index 0000000..eecf35b >>> --- /dev/null >>> +++ b/xen/arch/arm/platforms/omap5.c >>> @@ -0,0 +1,41 @@ >>> +/* >>> + * xen/arch/arm/platforma/omap5.c >>> + * >>> + * OMAP5 specific settings >>> + * >>> + * Chen Baozi <baozich@gmail.com> >>> + * Copyright (c) 2013 >>> + * >>> + * This program is free software; you can redistribute it and/or modify >>> + * it under the terms of the GNU General Public License as published by >>> + * the Free Software Foundation; either version 2 of the License, or >>> + * (at your option) any later version. >>> + * >>> + * This program is distributted in the hope that it will be useful, >>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of >>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the >>> + * GNU Gerneral Public License for more details. >>> + */ >>> + >>> +#include <xen/config.h> >>> +#include <asm/platforms/omap5.h> >>> +#include <asm/platform.h> >>> + >>> +static const char const *omap5_dt_compat[] __initdata >>> +{ >>> + "ti,omap5", >>> + NULL >>> +}; >>> + >>> +PLATFORM_START(omap5, "TI OMAP5") >>> + .compatible = omap5_dt_compat, >>> +PLATFORM_END >>> + >>> +/* >>> + * Local variables: >>> + * mode: C >>> + * c-file-style: "BSD" >>> + * c-basic-offset: 4 >>> + * indent-tabs-mode: nil >>> + * End: >>> + */ >>> diff --git a/xen/include/asm-arm/platforms/omap5.h b/xen/include/asm-arm/platforms/omap5.h >>> new file mode 100644 >>> index 0000000..fa825b7 >>> --- /dev/null >>> +++ b/xen/include/asm-arm/platforms/omap5.h >>> @@ -0,0 +1,23 @@ >>> +#ifndef __ASM_ARM_PLATFORMS_OMAP5_H >>> +#define __ASM_ASM_PLATFORMS_OMAP5_H >>> + >>> +/* Constants below is only used in assembly because the DTS is not yet parsed */ >>> +#ifdef __ASSEMBLY__ >>> + >>> +/* GIC Base Address */ >>> +#define OMAP5_GIC_BASE_ADDRESS 0x48210000 >>> + >>> +/* OMAP5432 uEVM machine ID */ >>> +#define MACH_TYPE_UEVM 3777 >> >> These 2 values seems unused in your patch series. Do you plan to use >> it in the future? > > Yes, it will be used in SMP boot codes, which I''m now working on. > Or, should I add this macros in the SMP boot patch?I would prefer, if you define these macros in the SMP boot patch. -- Julien
Julien Grall
2013-Aug-07 11:37 UTC
Re: [PATCH 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
On 08/07/2013 11:25 AM, Andrii Anisov wrote:> > >> diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c > >> index 4ed7882..6ca030a 100644 > >> --- a/xen/arch/arm/time.c > >> +++ b/xen/arch/arm/time.c > >> @@ -104,6 +104,7 @@ int __init init_xen_time(void) > >> struct dt_device_node *dev; > >> int res; > >> unsigned int i; > >> + const __be32 *rate; > >> > >> dev = dt_find_compatible_node(NULL, NULL, "arm,armv7-timer"); > >> if ( !dev ) > >> @@ -134,7 +135,11 @@ int __init init_xen_time(void) > >> if ( !cpu_has_gentimer ) > >> panic("CPU does not support the Generic Timer v1 > interface.\n"); > >> > >> - cpu_khz = READ_SYSREG32(CNTFRQ_EL0) / 1000; > >> + rate = dt_get_property(dev, "clock-frequency", NULL); > > > > You need to check if the length match the size of rate. > > Perhaps, you can add an helper dt_property_read_u32 (see > > linux/include/linux/of.h). > > OK. > > > I would propose another approach here: just let cpu_khz be set up by > architecture code.Linux uses the same approach as Chen. From linux/Documentation/devicetree/bindings/arm/arch_timer.txt: ** Timer node properties: - clock-frequency : The frequency of the main counter, in Hz. Optional. As Xen uses the arch timer, which is common for all ARMv7 platform, why does the platform code need to set up cpu_khz? -- Julien
Andrii Anisov
2013-Aug-07 11:58 UTC
Re: [PATCH 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
> > I would propose another approach here: just let cpu_khz be set up by > > architecture code. > > Linux uses the same approach as Chen. > From linux/Documentation/devicetree/bindings/arm/arch_timer.txt: > > ** Timer node properties: > - clock-frequency : The frequency of the main counter, in Hz. Optional. > > As Xen uses the arch timer, which is common for all ARMv7 platform, why > does the platform code need to set up cpu_khz? >Well, your argument is fair. It would be better to keep all the stuff together while timer freq is acquired from dt or CNTFRQ_EL0 only. SIncerely, Andrii Anisov. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel
Andrii Anisov
2013-Aug-07 12:04 UTC
Re: [PATCH 5/5] xen/arm: Add OMAP5 architected timer initialization codes.
It looks I stick a bit in android for omap world. Here we do not have device-tree support. So I miss it from time to time. Sincerely, Andrii Anisov. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xen.org http://lists.xen.org/xen-devel