Xen devel - Jun 2013 - vmx_disable_intercept_for_msr(v, MSR_SHADOW_GS_BASE)

Hi,

I am wondering if we can disable the VMX interception for
MSR_SHADOW_GS_BASE as AMD is already doing that.

Any comments?

Thanks,
CJ


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>>> On 28.06.13 at 23:02, Cyclonus J <cyclonusj@gmail.com> wrote:
> I am wondering if we can disable the VMX interception for
> MSR_SHADOW_GS_BASE as AMD is already doing that.
I can''t immediately see any reason why we shouldn''t be
permitted
to do this, but I also don''t think this should be performance critical.

If you feel this is important, why don''t you contribute a patch,
with its description saying under what conditions this can yield
measurable benefit?

Jan

On 01/07/13 10:38, Jan Beulich wrote:
>>>> On 28.06.13 at 23:02, Cyclonus J <cyclonusj@gmail.com>
wrote:
>> I am wondering if we can disable the VMX interception for
>> MSR_SHADOW_GS_BASE as AMD is already doing that.
> I can''t immediately see any reason why we shouldn''t be
permitted
> to do this, but I also don''t think this should be performance
critical.
>
> If you feel this is important, why don''t you contribute a patch,
> with its description saying under what conditions this can yield
> measurable benefit?
>
> Jan
Will this not cause a VMexit on each swapgs instruction, as the
instruction itself does write to MSR 0xC0000102?

I have looked quite closely through the Intel manuals and cant find
confirmation one way or another.

~Andrew
>
>
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel

>>> On 01.07.13 at 11:44, Andrew Cooper
<andrew.cooper3@citrix.com> wrote:
> On 01/07/13 10:38, Jan Beulich wrote:
>>>>> On 28.06.13 at 23:02, Cyclonus J
<cyclonusj@gmail.com> wrote:
>>> I am wondering if we can disable the VMX interception for
>>> MSR_SHADOW_GS_BASE as AMD is already doing that.
>> I can''t immediately see any reason why we shouldn''t
be permitted
>> to do this, but I also don''t think this should be performance
critical.
>>
>> If you feel this is important, why don''t you contribute a
patch,
>> with its description saying under what conditions this can yield
>> measurable benefit?
> 
> Will this not cause a VMexit on each swapgs instruction, as the
> instruction itself does write to MSR 0xC0000102?
No - see the comments in vmx.c around the handling of that MSR.

Jan

On 01/07/2013 10:44, "Andrew Cooper" <andrew.cooper3@citrix.com>
wrote:
> On 01/07/13 10:38, Jan Beulich wrote:
>>>>> On 28.06.13 at 23:02, Cyclonus J
<cyclonusj@gmail.com> wrote:
>>> I am wondering if we can disable the VMX interception for
>>> MSR_SHADOW_GS_BASE as AMD is already doing that.
>> I can''t immediately see any reason why we shouldn''t
be permitted
>> to do this, but I also don''t think this should be performance
critical.
>> 
>> If you feel this is important, why don''t you contribute a
patch,
>> with its description saying under what conditions this can yield
>> measurable benefit?
>> 
>> Jan
> 
> Will this not cause a VMexit on each swapgs instruction, as the
> instruction itself does write to MSR 0xC0000102?
> 
> I have looked quite closely through the Intel manuals and cant find
> confirmation one way or another.
Only RDMSR/WRMSR trap on the MSR bitmaps.
> ~Andrew
> 
>> 
>> 
>> _______________________________________________
>> Xen-devel mailing list
>> Xen-devel@lists.xen.org
>> http://lists.xen.org/xen-devel
> 
> 
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel

On 01/07/13 10:51, Keir Fraser wrote:
> On 01/07/2013 10:44, "Andrew Cooper"
<andrew.cooper3@citrix.com> wrote:
>
>> On 01/07/13 10:38, Jan Beulich wrote:
>>>>>> On 28.06.13 at 23:02, Cyclonus J
<cyclonusj@gmail.com> wrote:
>>>> I am wondering if we can disable the VMX interception for
>>>> MSR_SHADOW_GS_BASE as AMD is already doing that.
>>> I can''t immediately see any reason why we
shouldn''t be permitted
>>> to do this, but I also don''t think this should be
performance critical.
>>>
>>> If you feel this is important, why don''t you contribute a
patch,
>>> with its description saying under what conditions this can yield
>>> measurable benefit?
>>>
>>> Jan
>> Will this not cause a VMexit on each swapgs instruction, as the
>> instruction itself does write to MSR 0xC0000102?
>>
>> I have looked quite closely through the Intel manuals and cant find
>> confirmation one way or another.
> Only RDMSR/WRMSR trap on the MSR bitmaps.
Ok - so the performance aspect depends on whether the guest is using
per-thread kernel areas or not, in combination with swapgs.

I would have thought that this would be a sensible change to make at the
start of 4.4

~Andrew