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Christoph Egger

2013-Jun-13 10:22 UTC

[PATCH] xentrace: Correct PV trace dump

commit c1855d1ad8c5ce218b5ef6825401dc985a3d1f4d
Author: Christoph Egger <chegger@amazon.de>
Date:   Fri May 24 11:33:38 2013 +0000

    xentrace: Correct PV trace dump
    
    Signed-off-by: Christoph Egger <chegger@amazon.de>

diff --git a/tools/xentrace/formats b/tools/xentrace/formats
index 67fd42d..d88de75 100644
--- a/tools/xentrace/formats
+++ b/tools/xentrace/formats
@@ -84,30 +84,30 @@
 0x0010f002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_grant_unmap    [ domid =
%(1)d ]
 0x0010f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_grant_transfer [ domid =
%(1)d ]
 
-0x00201001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ eip = 0x%(1)08x,
eax = 0x%(2)08x ]
-0x00201101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ rip =
0x%(2)08x%(1)08x, eax = 0x%(3)08x ]
-0x00201003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ eip = 0x%(1)08x,
trapnr:error = 0x%(2)08x ]
-0x00201103  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ rip =
0x%(2)08x%(1)08x, trapnr:error = 0x%(3)08x ]
-0x00201004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ eip = 0x%(1)08x,
addr = 0x%(2)08x, error = 0x%(3)08x ]
-0x00201104  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ rip =
0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x, error = 0x%(5)08x ]
-0x00201005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [ eip =
0x%(1)08x ]
-0x00201105  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [ rip =
0x%(2)08x%(1)08x ]
-0x00201006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [ eip =
0x%(1)08x ]
-0x00201106  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [ rip =
0x%(2)08x%(1)08x ]
-0x00201007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [ eip =
0x%(1)08x ]
-0x00201107  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [ rip =
0x%(2)08x%(1)08x ]
-0x00201008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
-0x00201108  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
-0x00201009  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [ eip =
0x%(1)08x, addr = 0x%(2)08x ]
-0x00201109  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [ rip =
0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x ]
-0x0020100a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault  [ eip =
0x%(1)08x, offset = 0x%(2)08x ]
-0x0020110a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault  [ rip =
0x%(2)08x%(1)08x, offset = 0x%(4)08x%(3)08x ]
-0x0020100b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [ addr =
0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
-0x0020110b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [ addr =
0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
-0x0020100c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [ addr =
0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
-0x0020110c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [ addr =
0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
+0x0020f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ eip = 0x%(1)08x,
eax = 0x%(2)08x ]
+0x0020f101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ rip =
0x%(2)08x%(1)08x, eax = 0x%(3)08x ]
+0x0020f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ eip = 0x%(1)08x,
trapnr:error = 0x%(2)08x ]
+0x0020f103  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ rip =
0x%(2)08x%(1)08x, trapnr:error = 0x%(3)08x ]
+0x0020f004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ eip = 0x%(1)08x,
addr = 0x%(2)08x, error = 0x%(3)08x ]
+0x0020f104  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ rip =
0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x, error = 0x%(5)08x ]
+0x0020f005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [ eip =
0x%(1)08x ]
+0x0020f105  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [ rip =
0x%(2)08x%(1)08x ]
+0x0020f006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [ eip =
0x%(1)08x ]
+0x0020f106  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [ rip =
0x%(2)08x%(1)08x ]
+0x0020f007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [ eip =
0x%(1)08x ]
+0x0020f107  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [ rip =
0x%(2)08x%(1)08x ]
+0x0020f008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
+0x0020f108  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
+0x0020f009  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [ eip =
0x%(1)08x, addr = 0x%(2)08x ]
+0x0020f109  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [ rip =
0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x ]
+0x0020f00a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault  [ eip =
0x%(1)08x, offset = 0x%(2)08x ]
+0x0020f10a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault  [ rip =
0x%(2)08x%(1)08x, offset = 0x%(4)08x%(3)08x ]
+0x0020f00b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [ addr =
0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
+0x0020f10b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [ addr =
0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
+0x0020f00c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [ addr =
0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
+0x0020f10c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [ addr =
0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
 0x0020100d  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ op = 0x%(1)08x ]
-0x0020200e  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)    hypercall  [ op = 0x%(1)08x ]
+0x0020200e  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ op = 0x%(1)08x ]
 
 0x0040f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  shadow_not_shadow              
[ gl1e = 0x%(2)08x%(1)08x, va = 0x%(3)08x, flags = 0x%(4)08x ]
 0x0040f101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  shadow_not_shadow              
[ gl1e = 0x%(2)08x%(1)08x, va = 0x%(4)08x%(3)08x, flags = 0x%(5)08x ]


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Andrew Cooper

2013-Jun-13 10:39 UTC

head link

Re: [PATCH] xentrace: Correct PV trace dump

On 13/06/13 11:22, Christoph Egger wrote:> commit c1855d1ad8c5ce218b5ef6825401dc985a3d1f4d
> Author: Christoph Egger <chegger@amazon.de>
> Date:   Fri May 24 11:33:38 2013 +0000
>
>     xentrace: Correct PV trace dump
>     
>     Signed-off-by: Christoph Egger <chegger@amazon.de>
Can you describe in the commit message what you are changing and why?

It took me quite a while to see that the main set of changes were only
the identifier.

~Andrew
>
> diff --git a/tools/xentrace/formats b/tools/xentrace/formats
> index 67fd42d..d88de75 100644
> --- a/tools/xentrace/formats
> +++ b/tools/xentrace/formats
> @@ -84,30 +84,30 @@
>  0x0010f002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_grant_unmap    [
domid = %(1)d ]
>  0x0010f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_grant_transfer [
domid = %(1)d ]
>  
> -0x00201001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ eip =
0x%(1)08x, eax = 0x%(2)08x ]
> -0x00201101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ rip =
0x%(2)08x%(1)08x, eax = 0x%(3)08x ]
> -0x00201003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ eip =
0x%(1)08x, trapnr:error = 0x%(2)08x ]
> -0x00201103  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ rip =
0x%(2)08x%(1)08x, trapnr:error = 0x%(3)08x ]
> -0x00201004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ eip =
0x%(1)08x, addr = 0x%(2)08x, error = 0x%(3)08x ]
> -0x00201104  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ rip =
0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x, error = 0x%(5)08x ]
> -0x00201005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [ eip
= 0x%(1)08x ]
> -0x00201105  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [ rip
= 0x%(2)08x%(1)08x ]
> -0x00201006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [ eip
= 0x%(1)08x ]
> -0x00201106  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [ rip
= 0x%(2)08x%(1)08x ]
> -0x00201007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [ eip
= 0x%(1)08x ]
> -0x00201107  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [ rip
= 0x%(2)08x%(1)08x ]
> -0x00201008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
> -0x00201108  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
> -0x00201009  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [ eip
= 0x%(1)08x, addr = 0x%(2)08x ]
> -0x00201109  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [ rip
= 0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x ]
> -0x0020100a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault  [
eip = 0x%(1)08x, offset = 0x%(2)08x ]
> -0x0020110a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault  [
rip = 0x%(2)08x%(1)08x, offset = 0x%(4)08x%(3)08x ]
> -0x0020100b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [ addr
= 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
> -0x0020110b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [ addr
= 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
> -0x0020100c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [ addr
= 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
> -0x0020110c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [ addr
= 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
> +0x0020f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ eip =
0x%(1)08x, eax = 0x%(2)08x ]
> +0x0020f101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ rip =
0x%(2)08x%(1)08x, eax = 0x%(3)08x ]
> +0x0020f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ eip =
0x%(1)08x, trapnr:error = 0x%(2)08x ]
> +0x0020f103  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ rip =
0x%(2)08x%(1)08x, trapnr:error = 0x%(3)08x ]
> +0x0020f004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ eip =
0x%(1)08x, addr = 0x%(2)08x, error = 0x%(3)08x ]
> +0x0020f104  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ rip =
0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x, error = 0x%(5)08x ]
> +0x0020f005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [ eip
= 0x%(1)08x ]
> +0x0020f105  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [ rip
= 0x%(2)08x%(1)08x ]
> +0x0020f006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [ eip
= 0x%(1)08x ]
> +0x0020f106  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [ rip
= 0x%(2)08x%(1)08x ]
> +0x0020f007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [ eip
= 0x%(1)08x ]
> +0x0020f107  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [ rip
= 0x%(2)08x%(1)08x ]
> +0x0020f008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
> +0x0020f108  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
> +0x0020f009  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [ eip
= 0x%(1)08x, addr = 0x%(2)08x ]
> +0x0020f109  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [ rip
= 0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x ]
> +0x0020f00a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault  [
eip = 0x%(1)08x, offset = 0x%(2)08x ]
> +0x0020f10a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault  [
rip = 0x%(2)08x%(1)08x, offset = 0x%(4)08x%(3)08x ]
> +0x0020f00b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [ addr
= 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
> +0x0020f10b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [ addr
= 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
> +0x0020f00c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [ addr
= 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
> +0x0020f10c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [ addr
= 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
>  0x0020100d  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ op =
0x%(1)08x ]
> -0x0020200e  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)    hypercall  [ op =
0x%(1)08x ]
> +0x0020200e  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ op =
0x%(1)08x ]
>  
>  0x0040f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  shadow_not_shadow         
[ gl1e = 0x%(2)08x%(1)08x, va = 0x%(3)08x, flags = 0x%(4)08x ]
>  0x0040f101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  shadow_not_shadow         
[ gl1e = 0x%(2)08x%(1)08x, va = 0x%(4)08x%(3)08x, flags = 0x%(5)08x ]

Egger, Christoph

2013-Jun-13 10:51 UTC

head link

Re: [PATCH] xentrace: Correct PV trace dump

On 13.06.13 12:39, Andrew Cooper wrote:> On 13/06/13 11:22, Christoph Egger wrote:
>> commit c1855d1ad8c5ce218b5ef6825401dc985a3d1f4d
>> Author: Christoph Egger <chegger@amazon.de>
>> Date:   Fri May 24 11:33:38 2013 +0000
>>
>>     xentrace: Correct PV trace dump
>>     
>>     Signed-off-by: Christoph Egger <chegger@amazon.de>
> 
> Can you describe in the commit message what you are changing and why?
Without this patch the PV traces are not decoded at all
as the identifier is wrong.

This patch makes the identifier match with
xen/include/public/trace.h and the PV traces get decoded correctly.

Christoph
> 
> It took me quite a while to see that the main set of changes were only
> the identifier.
> 
> ~Andrew
> 
>>
>> diff --git a/tools/xentrace/formats b/tools/xentrace/formats
>> index 67fd42d..d88de75 100644
>> --- a/tools/xentrace/formats
>> +++ b/tools/xentrace/formats
>> @@ -84,30 +84,30 @@
>>  0x0010f002  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_grant_unmap    [
domid = %(1)d ]
>>  0x0010f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_grant_transfer [
domid = %(1)d ]
>>  
>> -0x00201001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ eip =
0x%(1)08x, eax = 0x%(2)08x ]
>> -0x00201101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ rip =
0x%(2)08x%(1)08x, eax = 0x%(3)08x ]
>> -0x00201003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ eip =
0x%(1)08x, trapnr:error = 0x%(2)08x ]
>> -0x00201103  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ rip =
0x%(2)08x%(1)08x, trapnr:error = 0x%(3)08x ]
>> -0x00201004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ eip =
0x%(1)08x, addr = 0x%(2)08x, error = 0x%(3)08x ]
>> -0x00201104  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ rip =
0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x, error = 0x%(5)08x ]
>> -0x00201005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [
eip = 0x%(1)08x ]
>> -0x00201105  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [
rip = 0x%(2)08x%(1)08x ]
>> -0x00201006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [
eip = 0x%(1)08x ]
>> -0x00201106  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [
rip = 0x%(2)08x%(1)08x ]
>> -0x00201007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [
eip = 0x%(1)08x ]
>> -0x00201107  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [
rip = 0x%(2)08x%(1)08x ]
>> -0x00201008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
>> -0x00201108  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
>> -0x00201009  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [
eip = 0x%(1)08x, addr = 0x%(2)08x ]
>> -0x00201109  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [
rip = 0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x ]
>> -0x0020100a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault 
[ eip = 0x%(1)08x, offset = 0x%(2)08x ]
>> -0x0020110a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault 
[ rip = 0x%(2)08x%(1)08x, offset = 0x%(4)08x%(3)08x ]
>> -0x0020100b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [
addr = 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
>> -0x0020110b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [
addr = 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
>> -0x0020100c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [
addr = 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
>> -0x0020110c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [
addr = 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
>> +0x0020f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ eip =
0x%(1)08x, eax = 0x%(2)08x ]
>> +0x0020f101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ rip =
0x%(2)08x%(1)08x, eax = 0x%(3)08x ]
>> +0x0020f003  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ eip =
0x%(1)08x, trapnr:error = 0x%(2)08x ]
>> +0x0020f103  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  trap       [ rip =
0x%(2)08x%(1)08x, trapnr:error = 0x%(3)08x ]
>> +0x0020f004  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ eip =
0x%(1)08x, addr = 0x%(2)08x, error = 0x%(3)08x ]
>> +0x0020f104  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  page_fault [ rip =
0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x, error = 0x%(5)08x ]
>> +0x0020f005  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [
eip = 0x%(1)08x ]
>> +0x0020f105  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  forced_invalid_op   [
rip = 0x%(2)08x%(1)08x ]
>> +0x0020f006  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [
eip = 0x%(1)08x ]
>> +0x0020f106  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_privop      [
rip = 0x%(2)08x%(1)08x ]
>> +0x0020f007  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [
eip = 0x%(1)08x ]
>> +0x0020f107  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  emulate_4G          [
rip = 0x%(2)08x%(1)08x ]
>> +0x0020f008  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
>> +0x0020f108  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  math_state_restore
>> +0x0020f009  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [
eip = 0x%(1)08x, addr = 0x%(2)08x ]
>> +0x0020f109  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  paging_fixup        [
rip = 0x%(2)08x%(1)08x, addr = 0x%(4)08x%(3)08x ]
>> +0x0020f00a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault 
[ eip = 0x%(1)08x, offset = 0x%(2)08x ]
>> +0x0020f10a  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  gdt_ldt_mapping_fault 
[ rip = 0x%(2)08x%(1)08x, offset = 0x%(4)08x%(3)08x ]
>> +0x0020f00b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [
addr = 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
>> +0x0020f10b  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation      [
addr = 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
>> +0x0020f00c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [
addr = 0x%(3)08x, eip = 0x%(4)08x, npte = 0x%(2)08x%(1)08x ]
>> +0x0020f10c  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  ptwr_emulation_pae  [
addr = 0x%(4)08x%(3)08x, rip = 0x%(6)08x%(5)08x, npte = 0x%(2)08x%(1)08x ]
>>  0x0020100d  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ op =
0x%(1)08x ]
>> -0x0020200e  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)    hypercall  [ op =
0x%(1)08x ]
>> +0x0020200e  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  hypercall  [ op =
0x%(1)08x ]
>>  
>>  0x0040f001  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  shadow_not_shadow     
[ gl1e = 0x%(2)08x%(1)08x, va = 0x%(3)08x, flags = 0x%(4)08x ]
>>  0x0040f101  CPU%(cpu)d  %(tsc)d (+%(reltsc)8d)  shadow_not_shadow     
[ gl1e = 0x%(2)08x%(1)08x, va = 0x%(4)08x%(3)08x, flags = 0x%(5)08x ]
>

George Dunlap

2013-Jun-13 14:17 UTC

head link

Re: [PATCH] xentrace: Correct PV trace dump

On 13/06/13 11:51, Egger, Christoph wrote:> On 13.06.13 12:39, Andrew Cooper wrote:
>> On 13/06/13 11:22, Christoph Egger wrote:
>>> commit c1855d1ad8c5ce218b5ef6825401dc985a3d1f4d
>>> Author: Christoph Egger <chegger@amazon.de>
>>> Date:   Fri May 24 11:33:38 2013 +0000
>>>
>>>      xentrace: Correct PV trace dump
>>>      
>>>      Signed-off-by: Christoph Egger <chegger@amazon.de>
>> Can you describe in the commit message what you are changing and why?
> Without this patch the PV traces are not decoded at all
> as the identifier is wrong.
>
> This patch makes the identifier match with
> xen/include/public/trace.h and the PV traces get decoded correctly.
I think he was asking you to re-send the patch with a more descriptive 
commit message.

  -George

Egger, Christoph

2013-Jun-13 14:27 UTC

head link

Re: [PATCH] xentrace: Correct PV trace dump

On 13.06.13 16:17, George Dunlap wrote:> On 13/06/13 11:51, Egger, Christoph wrote:
>> On 13.06.13 12:39, Andrew Cooper wrote:
>>> On 13/06/13 11:22, Christoph Egger wrote:
>>>> commit c1855d1ad8c5ce218b5ef6825401dc985a3d1f4d
>>>> Author: Christoph Egger <chegger@amazon.de>
>>>> Date:   Fri May 24 11:33:38 2013 +0000
>>>>
>>>>      xentrace: Correct PV trace dump
>>>>           Signed-off-by: Christoph Egger
<chegger@amazon.de>
>>> Can you describe in the commit message what you are changing and
why?
>> Without this patch the PV traces are not decoded at all
>> as the identifier is wrong.
>>
>> This patch makes the identifier match with
>> xen/include/public/trace.h and the PV traces get decoded correctly.
> 
> I think he was asking you to re-send the patch with a more descriptive
> commit message.
Done.

Christoph

George Dunlap

2013-Jun-13 14:33 UTC

head link

Re: [PATCH] xentrace: Correct PV trace dump

On 13/06/13 15:27, Egger, Christoph wrote:> On 13.06.13 16:17, George Dunlap wrote:
>> On 13/06/13 11:51, Egger, Christoph wrote:
>>> On 13.06.13 12:39, Andrew Cooper wrote:
>>>> On 13/06/13 11:22, Christoph Egger wrote:
>>>>> commit c1855d1ad8c5ce218b5ef6825401dc985a3d1f4d
>>>>> Author: Christoph Egger <chegger@amazon.de>
>>>>> Date:   Fri May 24 11:33:38 2013 +0000
>>>>>
>>>>>       xentrace: Correct PV trace dump
>>>>>            Signed-off-by: Christoph Egger
<chegger@amazon.de>
>>>> Can you describe in the commit message what you are changing
and why?
>>> Without this patch the PV traces are not decoded at all
>>> as the identifier is wrong.
>>>
>>> This patch makes the identifier match with
>>> xen/include/public/trace.h and the PV traces get decoded correctly.
>> I think he was asking you to re-send the patch with a more descriptive
>> commit message.
> Done.
No, not really.

What you wrote above is starting to become a descriptive message -- what 
you put in the re-sent patch is basically nothing.  You need to write 
what the problem was, and and also the technical thing that you are doing.

In particular, in this case, a whole series of trace records in 
xentrace_format have "1" for the subclass field, when they should have
"f".

  -George

Xen devel - Jun 2013 - [PATCH] xentrace: Correct PV trace dump

[PATCH] xentrace: Correct PV trace dump

Re: [PATCH] xentrace: Correct PV trace dump

Re: [PATCH] xentrace: Correct PV trace dump

Re: [PATCH] xentrace: Correct PV trace dump

Re: [PATCH] xentrace: Correct PV trace dump

Re: [PATCH] xentrace: Correct PV trace dump