This is a series of two patches, the first a prerequisite for the second, but functionally unrelated. The first adds readq/writeq for 64bit MMIO, and changes the existing MMIO accessors to use explicit bit widths. The second patch is an errata workaround, suitable for unstable. A slightly tweaked patch applicable for 4.2 and previously to follow very shortly. ~Andrew
Andrew Cooper
2013-May-22 10:13 UTC
[PATCH 1 of 2] x86: Use explicit widths for MMIO read/write, and add 64bit varients
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
diff -r 2369a9d759f0 -r 12e991b1d50b xen/include/asm-x86/io.h
--- a/xen/include/asm-x86/io.h
+++ b/xen/include/asm-x86/io.h
@@ -5,12 +5,14 @@
#include <xen/types.h>
#include <asm/page.h>
-#define readb(x) (*(volatile char *)(x))
-#define readw(x) (*(volatile short *)(x))
-#define readl(x) (*(volatile int *)(x))
-#define writeb(d,x) (*(volatile char *)(x) = (d))
-#define writew(d,x) (*(volatile short *)(x) = (d))
-#define writel(d,x) (*(volatile int *)(x) = (d))
+#define readb(x) (*(volatile uint8_t *)(x))
+#define readw(x) (*(volatile uint16_t *)(x))
+#define readl(x) (*(volatile uint32_t *)(x))
+#define readq(x) (*(volatile uint64_t *)(x))
+#define writeb(d,x) (*(volatile uint8_t *)(x) = (d))
+#define writew(d,x) (*(volatile uint16_t *)(x) = (d))
+#define writel(d,x) (*(volatile uint32_t *)(x) = (d))
+#define writeq(d,x) (*(volatile uint64_t *)(x) = (d))
#define __OUT1(s,x) \
static inline void out##s(unsigned x value, unsigned short port) {
Andrew Cooper
2013-May-22 10:13 UTC
[PATCH 2 of 2] AMD/iommu: SR56x0 Erratum 64 - Reset all head & tail pointers
Reference at time of patch:
http://support.amd.com/us/ChipsetMotherboard_TechDocs/46303.pdf
Erratum 64 states that the head and tail pointers for the Command buffer and
Event log are only reset on a cold boot, not a warm boot.
While the erratum is limited to systems using SR56xx chipsets (such as Family
10h CPUs), resetting the pointers is a sensible action in all cases, including
the PPR log for consistency.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
--
Changes since v1:
* Reset PPR head/tail pointer as well
* Make use of writeq()
diff -r 12e991b1d50b -r 50eb8a3229ec xen/drivers/passthrough/amd/iommu_init.c
--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -154,6 +154,11 @@ static void register_iommu_cmd_buffer_in
IOMMU_CMD_BUFFER_LENGTH_MASK,
IOMMU_CMD_BUFFER_LENGTH_SHIFT, &entry);
writel(entry, iommu->mmio_base+IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET);
+
+ /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
+ * automatically for us. */
+ writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
+ writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
}
static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu)
@@ -182,6 +187,11 @@ static void register_iommu_event_log_in_
IOMMU_EVENT_LOG_LENGTH_MASK,
IOMMU_EVENT_LOG_LENGTH_SHIFT, &entry);
writel(entry, iommu->mmio_base+IOMMU_EVENT_LOG_BASE_HIGH_OFFSET);
+
+ /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
+ * automatically for us. */
+ writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
+ writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
}
static void register_iommu_ppr_log_in_mmio_space(struct amd_iommu *iommu)
@@ -210,6 +220,9 @@ static void register_iommu_ppr_log_in_mm
IOMMU_PPR_LOG_LENGTH_MASK,
IOMMU_PPR_LOG_LENGTH_SHIFT, &entry);
writel(entry, iommu->mmio_base + IOMMU_PPR_LOG_BASE_HIGH_OFFSET);
+
+ writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
+ writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
}
On 22/05/2013 11:13, "Andrew Cooper" <andrew.cooper3@citrix.com> wrote:> This is a series of two patches, the first a prerequisite for the second, but > functionally unrelated. > > The first adds readq/writeq for 64bit MMIO, and changes the existing MMIO > accessors to use explicit bit widths. > > The second patch is an errata workaround, suitable for unstable. > > A slightly tweaked patch applicable for 4.2 and previously to follow very > shortly.Both are fine by me. Acked-by: Keir Fraser <keir@xen.org>> ~Andrew
Suthikulpanit, Suravee
2013-May-22 12:51 UTC
Re: [PATCH 2 of 2] AMD/iommu: SR56x0 Erratum 64 - Reset all head & tail pointers
Acked: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Thank you,
Suravee
-----Original Message-----
From: Andrew Cooper [mailto:andrew.cooper3@citrix.com]
Sent: Wednesday, May 22, 2013 5:14 AM
To: xen-devel@lists.xen.org
Cc: Keir Fraser; Jan Beulich; Suthikulpanit, Suravee; Shin, Jacob
Subject: [PATCH 2 of 2] AMD/iommu: SR56x0 Erratum 64 - Reset all head & tail
pointers
Reference at time of patch:
http://support.amd.com/us/ChipsetMotherboard_TechDocs/46303.pdf
Erratum 64 states that the head and tail pointers for the Command buffer and
Event log are only reset on a cold boot, not a warm boot.
While the erratum is limited to systems using SR56xx chipsets (such as Family
10h CPUs), resetting the pointers is a sensible action in all cases, including
the PPR log for consistency.
Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com>
--
Changes since v1:
* Reset PPR head/tail pointer as well
* Make use of writeq()
diff -r 12e991b1d50b -r 50eb8a3229ec xen/drivers/passthrough/amd/iommu_init.c
--- a/xen/drivers/passthrough/amd/iommu_init.c
+++ b/xen/drivers/passthrough/amd/iommu_init.c
@@ -154,6 +154,11 @@ static void register_iommu_cmd_buffer_in
IOMMU_CMD_BUFFER_LENGTH_MASK,
IOMMU_CMD_BUFFER_LENGTH_SHIFT, &entry);
writel(entry, iommu->mmio_base+IOMMU_CMD_BUFFER_BASE_HIGH_OFFSET);
+
+ /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
+ * automatically for us. */
+ writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_HEAD_OFFSET);
+ writeq(0, iommu->mmio_base + IOMMU_CMD_BUFFER_TAIL_OFFSET);
}
static void register_iommu_event_log_in_mmio_space(struct amd_iommu *iommu) @@
-182,6 +187,11 @@ static void register_iommu_event_log_in_
IOMMU_EVENT_LOG_LENGTH_MASK,
IOMMU_EVENT_LOG_LENGTH_SHIFT, &entry);
writel(entry, iommu->mmio_base+IOMMU_EVENT_LOG_BASE_HIGH_OFFSET);
+
+ /* Reset head/tail pointer. SR56x0 Erratum 64 means this might not happen
+ * automatically for us. */
+ writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_HEAD_OFFSET);
+ writeq(0, iommu->mmio_base + IOMMU_EVENT_LOG_TAIL_OFFSET);
}
static void register_iommu_ppr_log_in_mmio_space(struct amd_iommu *iommu) @@
-210,6 +220,9 @@ static void register_iommu_ppr_log_in_mm
IOMMU_PPR_LOG_LENGTH_MASK,
IOMMU_PPR_LOG_LENGTH_SHIFT, &entry);
writel(entry, iommu->mmio_base + IOMMU_PPR_LOG_BASE_HIGH_OFFSET);
+
+ writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_HEAD_OFFSET);
+ writeq(0, iommu->mmio_base + IOMMU_PPR_LOG_TAIL_OFFSET);
}