thr3ads.net - Xen devel - [PATCH] xen/arm: trap SMC instructions and inject an UND exception [May 2013]

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Ian Campbell

2013-May-02 11:01 UTC

[PATCH] xen/arm: trap SMC instructions and inject an UND exception

Currently only handles 32 bit guests. The 64-bit exception model is
considerably different.

Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
There are probably other places where injecting UND would be more appropriate
than killing the guest. It should also be reasonably easy to extend this logic
to inject DABT and PABT.
---
 xen/arch/arm/traps.c                  |   56 ++++++++++++++++++++++++++++++++-
 xen/include/asm-arm/arm32/processor.h |    4 ++-
 xen/include/asm-arm/processor.h       |    8 +++++
 xen/include/public/arch-arm.h         |    1 +
 4 files changed, 67 insertions(+), 2 deletions(-)

diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index b7487b7..72dddb2 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -59,7 +59,7 @@ void __cpuinit init_traps(void)
     WRITE_SYSREG((vaddr_t)hyp_traps_vector, VBAR_EL2);
 
     /* Setup hypervisor traps */
-    WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_VM, HCR_EL2);
+    WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_TSC|HCR_VM,
HCR_EL2);
     isb();
 }
 
@@ -239,6 +239,54 @@ void panic_PAR(uint64_t par)
     panic("Error during Hypervisor-to-physical address
translation\n");
 }
 
+static void cpsr_switch_mode(struct cpu_user_regs *regs, int mode)
+{
+    uint32_t sctlr = READ_SYSREG32(SCTLR_EL1);
+
+    regs->cpsr &=
~(PSR_MODE_MASK|PSR_IT_MASK|PSR_JAZELLE|PSR_BIG_ENDIAN|PSR_THUMB);
+
+    regs->cpsr |= mode;
+    regs->cpsr |= PSR_IRQ_MASK;
+    if (sctlr & SCTLR_TE)
+        regs->cpsr |= PSR_THUMB;
+    if (sctlr & SCTLR_EE)
+        regs->cpsr |= PSR_BIG_ENDIAN;
+}
+
+static vaddr_t exception_handler(vaddr_t offset)
+{
+    uint32_t sctlr = READ_SYSREG32(SCTLR_EL1);
+
+    if (sctlr & SCTLR_V)
+        return 0xffff0000 + offset;
+    else /* always have security exceptions */
+        return READ_SYSREG(VBAR_EL1) + offset;
+}
+
+/* Injects an Undefined Instruction exception into the current vcpu,
+ * PC is the exact address of the faulting instruction (without
+ * pipeline adjustments). See TakeUndefInstrException pseudocode in
+ * ARM.
+ */
+static void inject_undef_exception(struct cpu_user_regs *regs,
+                                   register_t preferred_return)
+{
+    uint32_t spsr = regs->cpsr;
+    int is_thumb = (regs->cpsr & PSR_THUMB);
+    /* Saved PC points to the instruction past the faulting instruction. */
+    uint32_t return_offset = is_thumb ? 2 : 4;
+
+    /* Update processor mode */
+    cpsr_switch_mode(regs, PSR_MODE_UND);
+
+    /* Update banked registers */
+    regs->spsr_und = spsr;
+    regs->lr_und = preferred_return + return_offset;
+
+    /* Branch to exception vector */
+    regs->pc32 = exception_handler(VECTOR32_UND);
+}
+
 struct reg_ctxt {
     uint32_t sctlr, tcr;
     uint64_t ttbr0, ttbr1;
@@ -941,6 +989,12 @@ asmlinkage void do_trap_hypervisor(struct cpu_user_regs
*regs)
             goto bad_trap;
         do_cp15_64(regs, hsr);
         break;
+    case HSR_EC_SMC:
+        /* PC32 already contains the preferred exception return
+         * address, so no need to adjust here.
+         */
+        inject_undef_exception(regs, regs->pc32);
+        break;
     case HSR_EC_HVC:
         if ( (hsr.iss & 0xff00) == 0xff00 )
             return do_debug_trap(regs, hsr.iss & 0x00ff);
diff --git a/xen/include/asm-arm/arm32/processor.h
b/xen/include/asm-arm/arm32/processor.h
index cd79170..d26fc85 100644
--- a/xen/include/asm-arm/arm32/processor.h
+++ b/xen/include/asm-arm/arm32/processor.h
@@ -31,7 +31,9 @@ struct cpu_user_regs
         uint32_t lr_usr;
     };
 
-    uint32_t pc; /* Return IP */
+    union {  /* Return IP, pc32 is used to allow code to be common with 64-bit
*/
+        uint32_t pc, pc32;
+    };
     uint32_t cpsr; /* Return mode */
     uint32_t pad0; /* Doubleword-align the kernel half of the frame */
 
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 1681ebf..1c9d793 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -85,6 +85,7 @@
 #define HSR_EC_CP14_64              0x0c
 #define HSR_EC_SVC                  0x11
 #define HSR_EC_HVC                  0x12
+#define HSR_EC_SMC                  0x13
 #define HSR_EC_INSTR_ABORT_GUEST    0x20
 #define HSR_EC_INSTR_ABORT_HYP      0x21
 #define HSR_EC_DATA_ABORT_GUEST     0x24
@@ -342,6 +343,13 @@ union hsr {
 #define CNTx_CTL_MASK     (1u<<1)  /* Mask IRQ */
 #define CNTx_CTL_PENDING  (1u<<2)  /* IRQ pending */
 
+/* Exception Vector offsets */
+#define VECTOR32_RST  0
+#define VECTOR32_UND  4
+#define VECTOR32_SVC  8
+#define VECTOR32_PABT 12
+#define VECTOR32_DABT 16
+
 #if defined(CONFIG_ARM_32)
 # include <asm/arm32/processor.h>
 #elif defined(CONFIG_ARM_64)
diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
index 2f5ce18..cea12b2 100644
--- a/xen/include/public/arch-arm.h
+++ b/xen/include/public/arch-arm.h
@@ -234,6 +234,7 @@ typedef uint64_t xen_callback_t;
 #define PSR_IRQ_MASK    (1<<7)        /* Interrupt mask */
 #define PSR_ABT_MASK    (1<<8)        /* Asynchronous Abort mask */
 #define PSR_BIG_ENDIAN  (1<<9)        /* Big Endian Mode */
+#define PSR_IT_MASK     (0x0600fc00)  /* Thumb If-Then Mask */
 #define PSR_JAZELLE     (1<<24)       /* Jazelle Mode */
 
 #endif /*  __XEN_PUBLIC_ARCH_ARM_H__ */
-- 
1.7.2.5

Ian Campbell

2013-May-02 11:12 UTC

head link

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

On Thu, 2013-05-02 at 12:01 +0100, Ian Campbell wrote:> Currently only handles 32 bit guests. The 64-bit exception model is
> considerably different.
> 
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
Tested with the following Linux patch...


diff --git a/arch/arm/kernel/setup.c b/arch/arm/kernel/setup.c
index 234e339..dbf2d03 100644
--- a/arch/arm/kernel/setup.c
+++ b/arch/arm/kernel/setup.c
@@ -43,6 +43,7 @@
 #include <asm/cacheflush.h>
 #include <asm/cachetype.h>
 #include <asm/tlbflush.h>
+#include <asm/opcodes-sec.h>
 
 #include <asm/prom.h>
 #include <asm/mach/arch.h>
@@ -730,6 +731,43 @@ static int __init meminfo_cmp(const void *_a, const void
*_b)
 	return cmp < 0 ? -1 : cmp > 0 ? 1 : 0;
 }
 
+static int __initdata test_und_count = 0;
+
+static int __init test_und_handler(struct pt_regs *regs, unsigned int instr)
+{
+	test_und_count++;
+	regs->ARM_pc += 4;
+	return 0;
+}
+
+static struct __initdata undef_hook und_hook = {
+	.instr_mask	= 0,
+	.instr_val	= 0,
+	.cpsr_mask	= MODE_MASK,
+	.cpsr_val	= SVC_MODE,
+	.fn		= test_und_handler,
+};
+
+static void __init test_und(void)
+{
+	int before = test_und_count;
+
+	register_undef_hook(&und_hook);
+	printk(KERN_INFO "Testing UND instruction... ");
+	asm volatile(".long 0xe7f000f0" : : : "memory");
+	printk(KERN_CONT "%s with count %d\n",
+	       (before + 1) == test_und_count ? "success" :
"failure",
+	       test_und_count);
+
+	printk(KERN_INFO "Testing SMC instruction... ");
+	before = test_und_count;
+	asm volatile(__SMC(0) : : : "memory");
+	printk(KERN_CONT "%s with count %d\n",
+	       (before + 1) == test_und_count ? "success" :
"failure",
+	       test_und_count);
+	unregister_undef_hook(&und_hook);
+}
+
 void __init hyp_mode_check(void)
 {
 #ifdef CONFIG_ARM_VIRT_EXT
@@ -784,6 +822,8 @@ void __init setup_arch(char **cmdline_p)
 
 	unflatten_device_tree();
 
+	test_und();
+
 	arm_dt_init_cpu_maps();
 #ifdef CONFIG_SMP
 	if (is_smp()) {

Stefano Stabellini

2013-May-02 13:53 UTC

head link

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

On Thu, 2 May 2013, Ian Campbell wrote:> Currently only handles 32 bit guests. The 64-bit exception model is
> considerably different.
> 
> Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
>
> There are probably other places where injecting UND would be more
appropriate
> than killing the guest. It should also be reasonably easy to extend this
logic
> to inject DABT and PABT.
> ---
>  xen/arch/arm/traps.c                  |   56
++++++++++++++++++++++++++++++++-
>  xen/include/asm-arm/arm32/processor.h |    4 ++-
>  xen/include/asm-arm/processor.h       |    8 +++++
>  xen/include/public/arch-arm.h         |    1 +
>  4 files changed, 67 insertions(+), 2 deletions(-)
> 
> diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
> index b7487b7..72dddb2 100644
> --- a/xen/arch/arm/traps.c
> +++ b/xen/arch/arm/traps.c
> @@ -59,7 +59,7 @@ void __cpuinit init_traps(void)
>      WRITE_SYSREG((vaddr_t)hyp_traps_vector, VBAR_EL2);
>  
>      /* Setup hypervisor traps */
> -    WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_VM, HCR_EL2);
> +    WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_TSC|HCR_VM,
HCR_EL2);
>      isb();
>  }
My recent patch http://marc.info/?l=xen-devel&m=136734156810415 does
this

> @@ -239,6 +239,54 @@ void panic_PAR(uint64_t par)
>      panic("Error during Hypervisor-to-physical address
translation\n");
>  }
>  
> +static void cpsr_switch_mode(struct cpu_user_regs *regs, int mode)
> +{
> +    uint32_t sctlr = READ_SYSREG32(SCTLR_EL1);
> +
> +    regs->cpsr &=
~(PSR_MODE_MASK|PSR_IT_MASK|PSR_JAZELLE|PSR_BIG_ENDIAN|PSR_THUMB);
> +
> +    regs->cpsr |= mode;
> +    regs->cpsr |= PSR_IRQ_MASK;
> +    if (sctlr & SCTLR_TE)
> +        regs->cpsr |= PSR_THUMB;
> +    if (sctlr & SCTLR_EE)
> +        regs->cpsr |= PSR_BIG_ENDIAN;
> +}
> +
> +static vaddr_t exception_handler(vaddr_t offset)
> +{
> +    uint32_t sctlr = READ_SYSREG32(SCTLR_EL1);
> +
> +    if (sctlr & SCTLR_V)
> +        return 0xffff0000 + offset;
> +    else /* always have security exceptions */
> +        return READ_SYSREG(VBAR_EL1) + offset;
> +}
> +
> +/* Injects an Undefined Instruction exception into the current vcpu,
> + * PC is the exact address of the faulting instruction (without
> + * pipeline adjustments). See TakeUndefInstrException pseudocode in
> + * ARM.
> + */
> +static void inject_undef_exception(struct cpu_user_regs *regs,
> +                                   register_t preferred_return)
> +{
> +    uint32_t spsr = regs->cpsr;
> +    int is_thumb = (regs->cpsr & PSR_THUMB);
> +    /* Saved PC points to the instruction past the faulting instruction.
*/
> +    uint32_t return_offset = is_thumb ? 2 : 4;
> +
> +    /* Update processor mode */
> +    cpsr_switch_mode(regs, PSR_MODE_UND);
> +
> +    /* Update banked registers */
> +    regs->spsr_und = spsr;
> +    regs->lr_und = preferred_return + return_offset;
> +
> +    /* Branch to exception vector */
> +    regs->pc32 = exception_handler(VECTOR32_UND);
> +}
> +
>  struct reg_ctxt {
>      uint32_t sctlr, tcr;
>      uint64_t ttbr0, ttbr1;
> @@ -941,6 +989,12 @@ asmlinkage void do_trap_hypervisor(struct
cpu_user_regs *regs)
>              goto bad_trap;
>          do_cp15_64(regs, hsr);
>          break;
> +    case HSR_EC_SMC:
> +        /* PC32 already contains the preferred exception return
> +         * address, so no need to adjust here.
> +         */
> +        inject_undef_exception(regs, regs->pc32);
> +        break;
>      case HSR_EC_HVC:
>          if ( (hsr.iss & 0xff00) == 0xff00 )
>              return do_debug_trap(regs, hsr.iss & 0x00ff);
> diff --git a/xen/include/asm-arm/arm32/processor.h
b/xen/include/asm-arm/arm32/processor.h
> index cd79170..d26fc85 100644
> --- a/xen/include/asm-arm/arm32/processor.h
> +++ b/xen/include/asm-arm/arm32/processor.h
> @@ -31,7 +31,9 @@ struct cpu_user_regs
>          uint32_t lr_usr;
>      };
>  
> -    uint32_t pc; /* Return IP */
> +    union {  /* Return IP, pc32 is used to allow code to be common with
64-bit */
> +        uint32_t pc, pc32;
> +    };
>      uint32_t cpsr; /* Return mode */
>      uint32_t pad0; /* Doubleword-align the kernel half of the frame */
>  
> diff --git a/xen/include/asm-arm/processor.h
b/xen/include/asm-arm/processor.h
> index 1681ebf..1c9d793 100644
> --- a/xen/include/asm-arm/processor.h
> +++ b/xen/include/asm-arm/processor.h
> @@ -85,6 +85,7 @@
>  #define HSR_EC_CP14_64              0x0c
>  #define HSR_EC_SVC                  0x11
>  #define HSR_EC_HVC                  0x12
> +#define HSR_EC_SMC                  0x13
>  #define HSR_EC_INSTR_ABORT_GUEST    0x20
>  #define HSR_EC_INSTR_ABORT_HYP      0x21
>  #define HSR_EC_DATA_ABORT_GUEST     0x24
> @@ -342,6 +343,13 @@ union hsr {
>  #define CNTx_CTL_MASK     (1u<<1)  /* Mask IRQ */
>  #define CNTx_CTL_PENDING  (1u<<2)  /* IRQ pending */
>  
> +/* Exception Vector offsets */
> +#define VECTOR32_RST  0
> +#define VECTOR32_UND  4
> +#define VECTOR32_SVC  8
> +#define VECTOR32_PABT 12
> +#define VECTOR32_DABT 16
> +
>  #if defined(CONFIG_ARM_32)
>  # include <asm/arm32/processor.h>
>  #elif defined(CONFIG_ARM_64)
> diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
> index 2f5ce18..cea12b2 100644
> --- a/xen/include/public/arch-arm.h
> +++ b/xen/include/public/arch-arm.h
> @@ -234,6 +234,7 @@ typedef uint64_t xen_callback_t;
>  #define PSR_IRQ_MASK    (1<<7)        /* Interrupt mask */
>  #define PSR_ABT_MASK    (1<<8)        /* Asynchronous Abort mask */
>  #define PSR_BIG_ENDIAN  (1<<9)        /* Big Endian Mode */
> +#define PSR_IT_MASK     (0x0600fc00)  /* Thumb If-Then Mask */
>  #define PSR_JAZELLE     (1<<24)       /* Jazelle Mode */
>  
>  #endif /*  __XEN_PUBLIC_ARCH_ARM_H__ */
> -- 
> 1.7.2.5
>

Ian Campbell

2013-May-02 15:55 UTC

head link

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

On Thu, 2013-05-02 at 14:53 +0100, Stefano Stabellini
wrote:> On Thu, 2 May 2013, Ian Campbell wrote:
> > Currently only handles 32 bit guests. The 64-bit exception model is
> > considerably different.
> > 
> > Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
> >
> > There are probably other places where injecting UND would be more
appropriate
> > than killing the guest. It should also be reasonably easy to extend
this logic
> > to inject DABT and PABT.
> > ---
> >  xen/arch/arm/traps.c                  |   56
++++++++++++++++++++++++++++++++-
> >  xen/include/asm-arm/arm32/processor.h |    4 ++-
> >  xen/include/asm-arm/processor.h       |    8 +++++
> >  xen/include/public/arch-arm.h         |    1 +
> >  4 files changed, 67 insertions(+), 2 deletions(-)
> > 
> > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
> > index b7487b7..72dddb2 100644
> > --- a/xen/arch/arm/traps.c
> > +++ b/xen/arch/arm/traps.c
> > @@ -59,7 +59,7 @@ void __cpuinit init_traps(void)
> >      WRITE_SYSREG((vaddr_t)hyp_traps_vector, VBAR_EL2);
> >  
> >      /* Setup hypervisor traps */
> > -    WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_VM,
HCR_EL2);
> > +   
WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_TSC|HCR_VM, HCR_EL2);
> >      isb();
> >  }
> 
> My recent patch http://marc.info/?l=xen-devel&m=136734156810415 does
> this
Right, I should have mentioned that. What do you do with the SMCs? I
think we''ve concluded that undef is the right response?

Ian.

Stefano Stabellini

2013-May-02 16:08 UTC

head link

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

On Thu, 2 May 2013, Ian Campbell wrote:> On Thu, 2013-05-02 at 14:53 +0100, Stefano Stabellini wrote:
> > On Thu, 2 May 2013, Ian Campbell wrote:
> > > Currently only handles 32 bit guests. The 64-bit exception model
is
> > > considerably different.
> > > 
> > > Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
> > >
> > > There are probably other places where injecting UND would be more
appropriate
> > > than killing the guest. It should also be reasonably easy to
extend this logic
> > > to inject DABT and PABT.
> > > ---
> > >  xen/arch/arm/traps.c                  |   56
++++++++++++++++++++++++++++++++-
> > >  xen/include/asm-arm/arm32/processor.h |    4 ++-
> > >  xen/include/asm-arm/processor.h       |    8 +++++
> > >  xen/include/public/arch-arm.h         |    1 +
> > >  4 files changed, 67 insertions(+), 2 deletions(-)
> > > 
> > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
> > > index b7487b7..72dddb2 100644
> > > --- a/xen/arch/arm/traps.c
> > > +++ b/xen/arch/arm/traps.c
> > > @@ -59,7 +59,7 @@ void __cpuinit init_traps(void)
> > >      WRITE_SYSREG((vaddr_t)hyp_traps_vector, VBAR_EL2);
> > >  
> > >      /* Setup hypervisor traps */
> > > -    WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_VM,
HCR_EL2);
> > > +   
WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_TSC|HCR_VM, HCR_EL2);
> > >      isb();
> > >  }
> > 
> > My recent patch http://marc.info/?l=xen-devel&m=136734156810415
does
> > this
> 
> Right, I should have mentioned that. What do you do with the SMCs? I
> think we''ve concluded that undef is the right response?
I was going to support SMC as a conduit for PSCI calls.

Ian Campbell

2013-May-03 09:07 UTC

head link

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

On Thu, 2013-05-02 at 17:08 +0100, Stefano Stabellini
wrote:> On Thu, 2 May 2013, Ian Campbell wrote:
> > On Thu, 2013-05-02 at 14:53 +0100, Stefano Stabellini wrote:
> > > On Thu, 2 May 2013, Ian Campbell wrote:
> > > > Currently only handles 32 bit guests. The 64-bit exception
model is
> > > > considerably different.
> > > > 
> > > > Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
> > > >
> > > > There are probably other places where injecting UND would be
more appropriate
> > > > than killing the guest. It should also be reasonably easy to
extend this logic
> > > > to inject DABT and PABT.
> > > > ---
> > > >  xen/arch/arm/traps.c                  |   56
++++++++++++++++++++++++++++++++-
> > > >  xen/include/asm-arm/arm32/processor.h |    4 ++-
> > > >  xen/include/asm-arm/processor.h       |    8 +++++
> > > >  xen/include/public/arch-arm.h         |    1 +
> > > >  4 files changed, 67 insertions(+), 2 deletions(-)
> > > > 
> > > > diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
> > > > index b7487b7..72dddb2 100644
> > > > --- a/xen/arch/arm/traps.c
> > > > +++ b/xen/arch/arm/traps.c
> > > > @@ -59,7 +59,7 @@ void __cpuinit init_traps(void)
> > > >      WRITE_SYSREG((vaddr_t)hyp_traps_vector, VBAR_EL2);
> > > >  
> > > >      /* Setup hypervisor traps */
> > > > -   
WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_VM, HCR_EL2);
> > > > +   
WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_TSC|HCR_VM, HCR_EL2);
> > > >      isb();
> > > >  }
> > > 
> > > My recent patch
http://marc.info/?l=xen-devel&m=136734156810415 does
> > > this
> > 
> > Right, I should have mentioned that. What do you do with the SMCs? I
> > think we''ve concluded that undef is the right response?
> 
> I was going to support SMC as a conduit for PSCI calls.
I think we have agreed with the PSCI guys that HVC will be a supported
conduit and since that is what we (will) advertise to guests I think
that''s all we should support -- there''s no need to allow two
ways to do
it.

Ian.

Stefano Stabellini

2013-May-03 10:12 UTC

head link

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

On Fri, 3 May 2013, Ian Campbell wrote:> On Thu, 2013-05-02 at 17:08 +0100, Stefano Stabellini wrote:
> > On Thu, 2 May 2013, Ian Campbell wrote:
> > > On Thu, 2013-05-02 at 14:53 +0100, Stefano Stabellini wrote:
> > > > On Thu, 2 May 2013, Ian Campbell wrote:
> > > > > Currently only handles 32 bit guests. The 64-bit
exception model is
> > > > > considerably different.
> > > > > 
> > > > > Signed-off-by: Ian Campbell
<ian.campbell@citrix.com>
> > > > >
> > > > > There are probably other places where injecting UND
would be more appropriate
> > > > > than killing the guest. It should also be reasonably
easy to extend this logic
> > > > > to inject DABT and PABT.
> > > > > ---
> > > > >  xen/arch/arm/traps.c                  |   56
++++++++++++++++++++++++++++++++-
> > > > >  xen/include/asm-arm/arm32/processor.h |    4 ++-
> > > > >  xen/include/asm-arm/processor.h       |    8 +++++
> > > > >  xen/include/public/arch-arm.h         |    1 +
> > > > >  4 files changed, 67 insertions(+), 2 deletions(-)
> > > > > 
> > > > > diff --git a/xen/arch/arm/traps.c
b/xen/arch/arm/traps.c
> > > > > index b7487b7..72dddb2 100644
> > > > > --- a/xen/arch/arm/traps.c
> > > > > +++ b/xen/arch/arm/traps.c
> > > > > @@ -59,7 +59,7 @@ void __cpuinit init_traps(void)
> > > > >      WRITE_SYSREG((vaddr_t)hyp_traps_vector, VBAR_EL2);
> > > > >  
> > > > >      /* Setup hypervisor traps */
> > > > > -   
WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_VM, HCR_EL2);
> > > > > +   
WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_TSC|HCR_VM, HCR_EL2);
> > > > >      isb();
> > > > >  }
> > > > 
> > > > My recent patch
http://marc.info/?l=xen-devel&m=136734156810415 does
> > > > this
> > > 
> > > Right, I should have mentioned that. What do you do with the
SMCs? I
> > > think we''ve concluded that undef is the right response?
> > 
> > I was going to support SMC as a conduit for PSCI calls.
> 
> I think we have agreed with the PSCI guys that HVC will be a supported
> conduit and since that is what we (will) advertise to guests I think
> that''s all we should support -- there''s no need to allow
two ways to do
> it.
The patch were written before the discussion.
Now I agree that we can just support HVC and get away with it.
I''ll update my series.

Ian Campbell

2013-May-03 10:19 UTC

head link

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

On Fri, 2013-05-03 at 11:12 +0100, Stefano Stabellini
wrote:> On Fri, 3 May 2013, Ian Campbell wrote:
> > On Thu, 2013-05-02 at 17:08 +0100, Stefano Stabellini wrote:
> > > On Thu, 2 May 2013, Ian Campbell wrote:
> > > > On Thu, 2013-05-02 at 14:53 +0100, Stefano Stabellini wrote:
> > > > > On Thu, 2 May 2013, Ian Campbell wrote:
> > > > > > Currently only handles 32 bit guests. The 64-bit
exception model is
> > > > > > considerably different.
> > > > > > 
> > > > > > Signed-off-by: Ian Campbell
<ian.campbell@citrix.com>
> > > > > >
> > > > > > There are probably other places where injecting
UND would be more appropriate
> > > > > > than killing the guest. It should also be
reasonably easy to extend this logic
> > > > > > to inject DABT and PABT.
> > > > > > ---
> > > > > >  xen/arch/arm/traps.c                  |   56
++++++++++++++++++++++++++++++++-
> > > > > >  xen/include/asm-arm/arm32/processor.h |    4 ++-
> > > > > >  xen/include/asm-arm/processor.h       |    8
+++++
> > > > > >  xen/include/public/arch-arm.h         |    1 +
> > > > > >  4 files changed, 67 insertions(+), 2 deletions(-)
> > > > > > 
> > > > > > diff --git a/xen/arch/arm/traps.c
b/xen/arch/arm/traps.c
> > > > > > index b7487b7..72dddb2 100644
> > > > > > --- a/xen/arch/arm/traps.c
> > > > > > +++ b/xen/arch/arm/traps.c
> > > > > > @@ -59,7 +59,7 @@ void __cpuinit init_traps(void)
> > > > > >      WRITE_SYSREG((vaddr_t)hyp_traps_vector,
VBAR_EL2);
> > > > > >  
> > > > > >      /* Setup hypervisor traps */
> > > > > > -   
WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_VM, HCR_EL2);
> > > > > > +   
WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_TSC|HCR_VM, HCR_EL2);
> > > > > >      isb();
> > > > > >  }
> > > > > 
> > > > > My recent patch
http://marc.info/?l=xen-devel&m=136734156810415 does
> > > > > this
> > > > 
> > > > Right, I should have mentioned that. What do you do with the
SMCs? I
> > > > think we''ve concluded that undef is the right
response?
> > > 
> > > I was going to support SMC as a conduit for PSCI calls.
> > 
> > I think we have agreed with the PSCI guys that HVC will be a supported
> > conduit and since that is what we (will) advertise to guests I think
> > that''s all we should support -- there''s no need to
allow two ways to do
> > it.
> 
> The patch were written before the discussion.
Right, I missed a "now" out of my first sentence.
> Now I agree that we can just support HVC and get away with it.
> I''ll update my series.
ACK. Do you just want to pull this patch in at the head? Or ack it and
I''ll apply as a baseline for you.

I''m also happy to rebase this over your original (i.e. remove the smc
support in it) too if you would prefer. Not sure if your current posting
has other changes required anyway.

Ian.

Stefano Stabellini

2013-May-03 10:30 UTC

head link

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

On Fri, 3 May 2013, Ian Campbell wrote:> On Fri, 2013-05-03 at 11:12 +0100, Stefano Stabellini wrote:
> > On Fri, 3 May 2013, Ian Campbell wrote:
> > > On Thu, 2013-05-02 at 17:08 +0100, Stefano Stabellini wrote:
> > > > On Thu, 2 May 2013, Ian Campbell wrote:
> > > > > On Thu, 2013-05-02 at 14:53 +0100, Stefano Stabellini
wrote:
> > > > > > On Thu, 2 May 2013, Ian Campbell wrote:
> > > > > > > Currently only handles 32 bit guests. The
64-bit exception model is
> > > > > > > considerably different.
> > > > > > > 
> > > > > > > Signed-off-by: Ian Campbell
<ian.campbell@citrix.com>
> > > > > > >
> > > > > > > There are probably other places where
injecting UND would be more appropriate
> > > > > > > than killing the guest. It should also be
reasonably easy to extend this logic
> > > > > > > to inject DABT and PABT.
> > > > > > > ---
> > > > > > >  xen/arch/arm/traps.c                  |   56
++++++++++++++++++++++++++++++++-
> > > > > > >  xen/include/asm-arm/arm32/processor.h |    4
++-
> > > > > > >  xen/include/asm-arm/processor.h       |    8
+++++
> > > > > > >  xen/include/public/arch-arm.h         |    1
+
> > > > > > >  4 files changed, 67 insertions(+), 2
deletions(-)
> > > > > > > 
> > > > > > > diff --git a/xen/arch/arm/traps.c
b/xen/arch/arm/traps.c
> > > > > > > index b7487b7..72dddb2 100644
> > > > > > > --- a/xen/arch/arm/traps.c
> > > > > > > +++ b/xen/arch/arm/traps.c
> > > > > > > @@ -59,7 +59,7 @@ void __cpuinit
init_traps(void)
> > > > > > >      WRITE_SYSREG((vaddr_t)hyp_traps_vector,
VBAR_EL2);
> > > > > > >  
> > > > > > >      /* Setup hypervisor traps */
> > > > > > > -   
WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_VM, HCR_EL2);
> > > > > > > +   
WRITE_SYSREG(HCR_PTW|HCR_BSU_OUTER|HCR_AMO|HCR_IMO|HCR_TSC|HCR_VM, HCR_EL2);
> > > > > > >      isb();
> > > > > > >  }
> > > > > > 
> > > > > > My recent patch
http://marc.info/?l=xen-devel&m=136734156810415 does
> > > > > > this
> > > > > 
> > > > > Right, I should have mentioned that. What do you do
with the SMCs? I
> > > > > think we''ve concluded that undef is the right
response?
> > > > 
> > > > I was going to support SMC as a conduit for PSCI calls.
> > > 
> > > I think we have agreed with the PSCI guys that HVC will be a
supported
> > > conduit and since that is what we (will) advertise to guests I
think
> > > that''s all we should support -- there''s no need
to allow two ways to do
> > > it.
> > 
> > The patch were written before the discussion.
> 
> Right, I missed a "now" out of my first sentence.
> 
> > Now I agree that we can just support HVC and get away with it.
> > I''ll update my series.
> 
> ACK. Do you just want to pull this patch in at the head? Or ack it and
> I''ll apply as a baseline for you.
OK, I can do that.
> I''m also happy to rebase this over your original (i.e. remove the
smc
> support in it) too if you would prefer. Not sure if your current posting
> has other changes required anyway.
I need to repost anyway.

Xen devel - May 2013 - [PATCH] xen/arm: trap SMC instructions and inject an UND exception

[PATCH] xen/arm: trap SMC instructions and inject an UND exception

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception

Re: [PATCH] xen/arm: trap SMC instructions and inject an UND exception