This is the last remaining part of "arm: tools: build for arm64 and enable cross-compiling for both arm32 and arm64", specifically the xenctx bit. Since that posting I''ve split out the ia64 cleanup + a whitespace cleanup and made xenctx actually do something useful on ARM. I''ve runtime tested on arm32 but only build tested on arm64 since you can''t trace dom0 and I''ve not got an arm64 guest kernel handy. Ian.
Ian Campbell
2013-Apr-12 13:13 UTC
[PATCH 1/4] arm: mark vcpus as initialised when they have been
I noticed this because XEN_DOMCTL_getvcpucontext won''t return anything
for a
VCPU which isn''t initialised.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
xen/arch/arm/domain.c | 2 ++
xen/arch/arm/domain_build.c | 1 +
2 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index e308813..04be3d6 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -557,6 +557,8 @@ int arch_set_info_guest(
v->arch.ttbr1 = ctxt->ttbr1;
v->arch.ttbcr = ctxt->ttbcr;
+ v->is_initialised = 1;
+
if ( ctxt->flags & VGCF_online )
clear_bit(_VPF_down, &v->pause_flags);
else
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index a6d8e9d..17aadcf 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -412,6 +412,7 @@ int construct_dom0(struct domain *d)
discard_initial_modules();
+ v->is_initialised = 1;
clear_bit(_VPF_down, &v->pause_flags);
memset(regs, 0, sizeof(*regs));
--
1.7.9.1
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
tools/xentrace/xenctx.c | 302 +----------------------------------------------
1 files changed, 1 insertions(+), 301 deletions(-)
diff --git a/tools/xentrace/xenctx.c b/tools/xentrace/xenctx.c
index 62327f7..70a5455 100644
--- a/tools/xentrace/xenctx.c
+++ b/tools/xentrace/xenctx.c
@@ -49,18 +49,6 @@ int guest_word_size = sizeof (unsigned long);
/* Word-length of the context record we get from xen */
int ctxt_word_size = sizeof (unsigned long);
int guest_protected_mode = 1;
-#elif defined (__ia64__)
-/* On ia64, we can''t translate virtual address to physical address.
*/
-#define NO_TRANSLATION
-typedef size_t guest_word_t;
-
-/* Which registers should be displayed. */
-int disp_cr_regs;
-int disp_ar_regs;
-int disp_br_regs;
-int disp_bank_regs;
-int disp_tlb;
-
#elif defined(__arm__)
#define NO_TRANSLATION
typedef uint64_t guest_word_t;
@@ -442,248 +430,6 @@ static guest_word_t frame_pointer(vcpu_guest_context_any_t
*ctx)
return ctx->x64.user_regs.rbp;
}
-#elif defined(__ia64__)
-
-#define PTE_ED_SHIFT 52
-#define PTE_ED_MASK 1
-#define PTE_PPN_SHIFT 12
-#define PTE_PPN_MASK 0x3fffffffff
-#define PTE_AR_SHIFT 9
-#define PTE_AR_MASK 7
-#define PTE_PL_SHIFT 7
-#define PTE_PL_MASK 3
-#define PTE_D_SHIFT 6
-#define PTE_D_MASK 1
-#define PTE_A_SHIFT 5
-#define PTE_A_MASK 1
-#define PTE_MA_SHIFT 2
-#define PTE_MA_MASK 7
-#define PTE_P_SHIFT 0
-#define PTE_P_MASK 1
-#define ITIR_KEY_SHIFT 8
-#define ITIR_KEY_MASK 0xffffff
-#define ITIR_PS_SHIFT 2
-#define ITIR_PS_MASK 0x3f
-#define ITIR_PS_MIN 12
-#define ITIR_PS_MAX 28
-#define RR_RID_SHIFT 8
-#define RR_RID_MASK 0xffffff
-#define PSR_BN (1UL << 44)
-#define CFM_SOF_MASK 0x3f
-
-static void print_tr(int i, const struct ia64_tr_entry *tr)
-{
- int ps_val, ma_val;
- unsigned long pa;
-
- static const char ps[][5] = {" 4K", " 8K", "
16K", " ",
- " 64K", " ",
"256K", " ",
- " 1M", " ", "
4M", " ",
- " 16M", " ", "
64M", " ",
- "256M"};
- static const char ma[][4] = {"WB ", " ", "
", " ",
- "UC ", "UCE", "WC
", "Nat"};
-
- ps_val = tr->itir >> ITIR_PS_SHIFT & ITIR_PS_MASK;
- ma_val = tr->pte >> PTE_MA_SHIFT & PTE_MA_MASK;
- pa = (tr->pte >> PTE_PPN_SHIFT & PTE_PPN_MASK) <<
PTE_PPN_SHIFT;
- pa = (pa >> ps_val) << ps_val;
- printf(" [%d] %ld %06lx %016lx %013lx %02x %s %ld %ld %ld %ld
"
- "%ld %d %s %06lx\n", i,
- tr->pte >> PTE_P_SHIFT & PTE_P_MASK,
- tr->rid >> RR_RID_SHIFT & RR_RID_MASK,
- tr->vadr, pa, ps_val,
- ((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ?
- ps[ps_val - ITIR_PS_MIN] : " "),
- tr->pte >> PTE_ED_SHIFT & PTE_ED_MASK,
- tr->pte >> PTE_PL_SHIFT & PTE_PL_MASK,
- tr->pte >> PTE_AR_SHIFT & PTE_AR_MASK,
- tr->pte >> PTE_A_SHIFT & PTE_A_MASK,
- tr->pte >> PTE_D_SHIFT & PTE_D_MASK,
- ma_val, ma[ma_val],
- tr->itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK);
-}
-
-void print_ctx(vcpu_guest_context_any_t *ctx)
-{
- struct vcpu_guest_context_regs *regs = &ctx->c.regs;
- struct vcpu_tr_regs *tr = &ctx->c.regs.tr;
- int i;
- unsigned int rbs_size, cfm_sof;
-
- printf(" ip: %016lx ", regs->ip);
- print_symbol(regs->ip);
- printf("\n");
- printf(" psr: %016lx ", regs->psr);
- printf(" cfm: %016lx ", regs->cfm);
- printf(" pr: %016lx\n", regs->pr);
-
- if (disp_br_regs) {
- printf(" b0: %016lx ", regs->b[0]);
- printf(" b1: %016lx ", regs->b[1]);
- printf(" b2: %016lx\n", regs->b[2]);
- printf(" b3: %016lx ", regs->b[3]);
- printf(" b4: %016lx ", regs->b[4]);
- printf(" b5: %016lx\n", regs->b[5]);
- printf(" b6: %016lx ", regs->b[6]);
- printf(" b7: %016lx\n", regs->b[7]);
- } else {
- printf(" b0: %016lx\n", regs->b[0]);
- }
-
- if (disp_cr_regs) {
- printf ("\n"
- " CR:\n");
- printf(" dcr: %016lx ", regs->cr.dcr);
- printf(" itm: %016lx ", regs->cr.itm);
- printf(" iva: %016lx\n", regs->cr.iva);
- printf(" pta: %016lx ", regs->cr.pta);
- printf(" ipsr: %016lx ", regs->cr.ipsr);
- printf(" isr: %016lx\n", regs->cr.isr);
- printf(" iip: %016lx ", regs->cr.iip);
- printf(" ifa: %016lx ", regs->cr.ifa);
- printf(" itir: %016lx\n", regs->cr.itir);
- printf(" iipa: %016lx ", regs->cr.iipa);
- printf(" ifs: %016lx ", regs->cr.ifs);
- printf(" iim: %016lx\n", regs->cr.iim);
- printf(" iha: %016lx ", regs->cr.iha);
- printf(" lid: %016lx ", regs->cr.lid);
- printf(" ivr: %016lx\n", regs->cr.ivr);
- printf(" tpr: %016lx ", regs->cr.tpr);
- printf(" eoi: %016lx ", regs->cr.eoi);
- printf(" irr0: %016lx\n", regs->cr.irr[0]);
- printf(" irr1: %016lx ", regs->cr.irr[1]);
- printf(" irr2: %016lx ", regs->cr.irr[2]);
- printf(" irr3: %016lx\n", regs->cr.irr[3]);
- printf(" itv: %016lx ", regs->cr.itv);
- printf(" pmv: %016lx ", regs->cr.pmv);
- printf(" cmcv: %016lx\n", regs->cr.cmcv);
- printf(" lrr0: %016lx ", regs->cr.lrr0);
- printf(" lrr1: %016lx ", regs->cr.lrr1);
- printf(" ev_cb:%016lx\n", ctx->c.event_callback_ip);
-
- }
- if (disp_ar_regs) {
- printf ("\n"
- " AR:\n");
- printf(" kr0: %016lx ", regs->ar.kr[0]);
- printf(" kr1: %016lx ", regs->ar.kr[1]);
- printf(" kr2: %016lx\n", regs->ar.kr[2]);
- printf(" kr3: %016lx ", regs->ar.kr[3]);
- printf(" kr4: %016lx ", regs->ar.kr[4]);
- printf(" kr5: %016lx\n", regs->ar.kr[5]);
- printf(" kr6: %016lx ", regs->ar.kr[6]);
- printf(" kr7: %016lx ", regs->ar.kr[7]);
- printf(" rsc: %016lx\n", regs->ar.rsc);
- printf(" bsp: %016lx ", regs->ar.bsp);
- printf(" bsps: %016lx ", regs->ar.bspstore);
- printf(" rnat: %016lx\n", regs->ar.rnat);
- printf(" csd: %016lx ", regs->ar.csd);
- printf(" ccv: %016lx ", regs->ar.ccv);
- printf(" unat: %016lx\n", regs->ar.unat);
- printf(" fpsr: %016lx ", regs->ar.fpsr);
- printf(" itc: %016lx\n", regs->ar.itc);
- printf(" pfs: %016lx ", regs->ar.pfs);
- printf(" lc: %016lx ", regs->ar.lc);
- printf(" ec: %016lx\n", regs->ar.ec);
- }
- printf("\n");
- printf(" r1: %016lx ", regs->r[1]);
- printf(" r2: %016lx ", regs->r[2]);
- printf(" r3: %016lx\n", regs->r[3]);
- printf(" r4: %016lx ", regs->r[4]);
- printf(" r5: %016lx ", regs->r[5]);
- printf(" r6: %016lx\n", regs->r[6]);
- printf(" r7: %016lx ", regs->r[7]);
- printf(" r8: %016lx ", regs->r[8]);
- printf(" r9: %016lx\n", regs->r[9]);
- printf(" r10: %016lx ", regs->r[10]);
- printf(" r11: %016lx ", regs->r[11]);
- printf(" sp: %016lx\n", regs->r[12]);
- printf(" tp: %016lx ", regs->r[13]);
- printf(" r14: %016lx ", regs->r[14]);
- printf(" r15: %016lx\n", regs->r[15]);
- if (disp_bank_regs) {
- printf(" Bank %d (current) Bank
%d\n",
- (regs->psr & PSR_BN) ? 1 : 0, (regs->psr & PSR_BN)
? 0 : 1);
- printf ("16:%016lx ", regs->r[16]);
- printf ("17:%016lx ", regs->r[17]);
- printf ("16:%016lx ", regs->bank[0]);
- printf ("17:%016lx\n", regs->bank[1]);
- printf ("18:%016lx ", regs->r[18]);
- printf ("19:%016lx ", regs->r[19]);
- printf ("18:%016lx ", regs->bank[2]);
- printf ("19:%016lx\n", regs->bank[3]);
- printf ("20:%016lx ", regs->r[20]);
- printf ("21:%016lx ", regs->r[21]);
- printf ("20:%016lx ", regs->bank[4]);
- printf ("21:%016lx\n", regs->bank[5]);
- printf ("22:%016lx ", regs->r[22]);
- printf ("23:%016lx ", regs->r[23]);
- printf ("22:%016lx ", regs->bank[6]);
- printf ("23:%016lx\n", regs->bank[7]);
- printf ("24:%016lx ", regs->r[24]);
- printf ("25:%016lx ", regs->r[25]);
- printf ("24:%016lx ", regs->bank[8]);
- printf ("25:%016lx\n", regs->bank[9]);
- printf ("26:%016lx ", regs->r[26]);
- printf ("27:%016lx ", regs->r[27]);
- printf ("26:%016lx ", regs->bank[10]);
- printf ("27:%016lx\n", regs->bank[11]);
- printf ("28:%016lx ", regs->r[28]);
- printf ("29:%016lx ", regs->r[29]);
- printf ("28:%016lx ", regs->bank[12]);
- printf ("29:%016lx\n", regs->bank[13]);
- printf ("30:%016lx ", regs->r[30]);
- printf ("31:%016lx ", regs->r[31]);
- printf ("30:%016lx ", regs->bank[14]);
- printf ("31:%016lx\n", regs->bank[15]);
- } else {
- printf(" r16: %016lx ", regs->r[16]);
- printf(" r17: %016lx ", regs->r[17]);
- printf(" r18: %016lx\n", regs->r[18]);
- printf(" r19: %016lx ", regs->r[19]);
- printf(" r20: %016lx ", regs->r[20]);
- printf(" r21: %016lx\n", regs->r[21]);
- printf(" r22: %016lx ", regs->r[22]);
- printf(" r23: %016lx ", regs->r[23]);
- printf(" r24: %016lx\n", regs->r[24]);
- printf(" r25: %016lx ", regs->r[25]);
- printf(" r26: %016lx ", regs->r[26]);
- printf(" r27: %016lx\n", regs->r[27]);
- printf(" r28: %016lx ", regs->r[28]);
- printf(" r29: %016lx ", regs->r[29]);
- printf(" r30: %016lx\n", regs->r[30]);
- printf(" r31: %016lx\n", regs->r[31]);
- }
-
- printf("\n");
- rbs_size = (regs->ar.bsp - regs->ar.bspstore) / 8;
- cfm_sof = (regs->cfm & CFM_SOF_MASK);
- for (i = 0; i < cfm_sof; i++) {
- int off = cfm_sof - i;
- unsigned int rbs_off - (((62 - ((rbs_size +
regs->rbs_voff) % 63) + off)) / 63) + off;
- if (rbs_off > rbs_size)
- break;
- printf(" r%02d: %016lx%s", 32 + i,
- regs->rbs[rbs_size - rbs_off],
- (i % 3) != 2 ? " " : "\n");
- }
- if ((i % 3) != 0)
- printf ("\n");
-
- if (disp_tlb) {
- printf("\n itr: P rid va pa ps ed
pl "
- "ar a d ma key\n");
- for (i = 0; i < 8; i++)
- print_tr(i, &tr->itrs[i]);
- printf("\n dtr: P rid va pa ps ed
pl "
- "ar a d ma key\n");
- for (i = 0; i < 8; i++)
- print_tr(i, &tr->dtrs[i]);
- }
-}
#elif defined(__arm__)
static void print_ctx(vcpu_guest_context_any_t *ctx)
{
@@ -940,12 +686,7 @@ static void usage(void)
printf(" -S --stack-trace print a complete stack trace.\n");
printf(" -k, --kernel-start\n");
printf(" set user/kernel split. (default
0xc0000000)\n");
-#ifdef __ia64__
- printf(" -r LIST, --regs=LIST display more registers.\n");
- printf(" -a --all same as --regs=tlb,cr,ar,br,bk\n");
-#else
printf(" -a --all display more registers\n");
-#endif
printf(" -C --all-vcpus print info for all vcpus\n");
}
@@ -953,19 +694,12 @@ int main(int argc, char **argv)
{
int ch;
int ret;
- static const char *sopts = "fs:hak:SC"
-#ifdef __ia64__
- "r:"
-#endif
- ;
+ static const char *sopts = "fs:hak:SC";
static const struct option lopts[] = {
{"stack-trace", 0, NULL, ''S''},
{"symbol-table", 1, NULL, ''s''},
{"frame-pointers", 0, NULL, ''f''},
{"kernel-start", 1, NULL, ''k''},
-#ifdef __ia64__
- {"regs", 1, NULL, ''r''},
-#endif
{"all", 0, NULL, ''a''},
{"all-vcpus", 0, NULL, ''C''},
{"help", 0, NULL, ''h''},
@@ -986,43 +720,9 @@ int main(int argc, char **argv)
case ''S'':
xenctx.stack_trace = 1;
break;
-#ifdef __ia64__
- case ''r'':
- {
- char *r;
-
- r = strtok(optarg, ",");
- while (r) {
- if (strcmp (r, "cr") == 0)
- disp_cr_regs = 1;
- else if (strcmp (r, "ar") == 0)
- disp_ar_regs = 1;
- else if (strcmp (r, "br") == 0)
- disp_br_regs = 1;
- else if (strcmp (r, "bk") == 0)
- disp_bank_regs = 1;
- else if (strcmp (r, "tlb") == 0)
- disp_tlb = 1;
- else {
- fprintf(stderr,"unknown register set %s\n",
r);
- exit(-1);
- }
- r = strtok(NULL, "''");
- }
- }
- break;
- case ''a'':
- disp_cr_regs = 1;
- disp_ar_regs = 1;
- disp_br_regs = 1;
- disp_bank_regs = 1;
- disp_tlb = 1;
- break;
-#else
case ''a'':
xenctx.disp_all = 1;
break;
-#endif
case ''C'':
xenctx.all_vcpus = 1;
break;
--
1.7.9.1
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
tools/xentrace/xenctx.c | 18 +++++++++---------
1 files changed, 9 insertions(+), 9 deletions(-)
diff --git a/tools/xentrace/xenctx.c b/tools/xentrace/xenctx.c
index 70a5455..1984a31 100644
--- a/tools/xentrace/xenctx.c
+++ b/tools/xentrace/xenctx.c
@@ -64,7 +64,7 @@ struct symbol {
guest_word_t kernel_stext, kernel_etext, kernel_sinittext, kernel_einittext,
kernel_hypercallpage;
-#if defined (__i386__)
+#if defined (__i386__)
unsigned long long kernel_start = 0xc0000000;
#else
unsigned long long kernel_start = 0xffffffff80000000UL;
@@ -380,11 +380,11 @@ static void print_ctx_64(vcpu_guest_context_x86_64_t *ctx)
static void print_ctx(vcpu_guest_context_any_t *ctx)
{
- if (ctxt_word_size == 4)
+ if (ctxt_word_size == 4)
print_ctx_32(&ctx->x32);
else if (guest_word_size == 4)
print_ctx_32on64(&ctx->x64);
- else
+ else
print_ctx_64(&ctx->x64);
}
@@ -400,7 +400,7 @@ static guest_word_t instr_pointer(vcpu_guest_context_any_t
*ctx)
if ( !guest_protected_mode )
r += ctx->x32.user_regs.cs << NONPROT_MODE_SEGMENT_SHIFT;
}
- else
+ else
r = ctx->x64.user_regs.rip;
return r;
@@ -416,17 +416,17 @@ static guest_word_t stack_pointer(vcpu_guest_context_any_t
*ctx)
if ( !guest_protected_mode )
r += ctx->x32.user_regs.ss << NONPROT_MODE_SEGMENT_SHIFT;
}
- else
+ else
r = ctx->x64.user_regs.rsp;
-
+
return r;
}
static guest_word_t frame_pointer(vcpu_guest_context_any_t *ctx)
{
- if (ctxt_word_size == 4)
+ if (ctxt_word_size == 4)
return ctx->x32.user_regs.ebp;
- else
+ else
return ctx->x64.user_regs.rbp;
}
@@ -515,7 +515,7 @@ static int print_stack(vcpu_guest_context_any_t *ctx, int
vcpu, int width)
int i;
stack_limit = ((stack_pointer(ctx) + XC_PAGE_SIZE)
- & ~((guest_word_t) XC_PAGE_SIZE - 1));
+ & ~((guest_word_t) XC_PAGE_SIZE - 1));
printf("\n");
printf("Stack:\n");
for (i=1; i<5 && stack < stack_limit; i++) {
--
1.7.9.1
Ian Campbell
2013-Apr-12 13:13 UTC
[PATCH 4/4] xenctx: Support arm64 and actually implement output for 32 and 64 bit
A bit basic a fuggly but a start.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
v2: - split ia64 stuff into separate patch
- actually print the registers
---
tools/xentrace/xenctx.c | 141 +++++++++++++++++++++++++++++++++++++++++++++-
1 files changed, 137 insertions(+), 4 deletions(-)
diff --git a/tools/xentrace/xenctx.c b/tools/xentrace/xenctx.c
index 1984a31..060e480 100644
--- a/tools/xentrace/xenctx.c
+++ b/tools/xentrace/xenctx.c
@@ -54,6 +54,11 @@ int guest_protected_mode = 1;
typedef uint64_t guest_word_t;
#define FMT_32B_WORD "%08llx"
#define FMT_64B_WORD "%016llx"
+#elif defined(__aarch64__)
+#define NO_TRANSLATION
+typedef uint64_t guest_word_t;
+#define FMT_32B_WORD "%08lx"
+#define FMT_64B_WORD "%016lx"
#endif
struct symbol {
@@ -430,12 +435,140 @@ static guest_word_t
frame_pointer(vcpu_guest_context_any_t *ctx)
return ctx->x64.user_regs.rbp;
}
-#elif defined(__arm__)
-static void print_ctx(vcpu_guest_context_any_t *ctx)
+#elif defined(__arm__) || defined(__aarch64__)
+
+static void print_ctx_32(vcpu_guest_context_t *ctx)
{
- /* XXX: properly implement this */
- print_symbol(0);
+ vcpu_guest_core_regs_t *regs = &ctx->user_regs;
+
+ printf("PC: %08"PRIx32" ", regs->pc32);
+ print_symbol(regs->pc32);
+ printf("\n");
+ printf("CPSR: %08"PRIx32"\n", regs->cpsr);
+ printf("USR: SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->sp_usr, regs->lr_usr);
+ printf("SVC: SPSR:%08"PRIx32" SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->spsr_svc, regs->sp_svc, regs->lr_svc);
+ printf("FIQ: SPSR:%08"PRIx32" SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->spsr_fiq, regs->sp_fiq, regs->lr_fiq);
+ printf("IRQ: SPSR:%08"PRIx32" SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->spsr_irq, regs->sp_irq, regs->lr_irq);
+ printf("ABT: SPSR:%08"PRIx32" SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->spsr_abt, regs->sp_abt, regs->lr_abt);
+ printf("UND: SPSR:%08"PRIx32" SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->spsr_und, regs->sp_und, regs->lr_und);
+
+ printf("\n");
+ printf(" r0_usr: %08"PRIx32"\t", regs->r0_usr);
+ printf(" r1_usr: %08"PRIx32"\t", regs->r1_usr);
+ printf(" r2_usr: %08"PRIx32"\n", regs->r2_usr);
+
+ printf(" r3_usr: %08"PRIx32"\t", regs->r3_usr);
+ printf(" r4_usr: %08"PRIx32"\t", regs->r4_usr);
+ printf(" r5_usr: %08"PRIx32"\n", regs->r5_usr);
+
+ printf(" r6_usr: %08"PRIx32"\t", regs->r6_usr);
+ printf(" r7_usr: %08"PRIx32"\t", regs->r7_usr);
+ printf(" r8_usr: %08"PRIx32"\n", regs->r8_usr);
+
+ printf(" r9_usr: %08"PRIx32"\t", regs->r9_usr);
+ printf("r10_usr: %08"PRIx32"\t", regs->r10_usr);
+ printf("r11_usr: %08"PRIx32"\n", regs->r11_usr);
+
+ printf("r12_usr: %08"PRIx32"\n", regs->r12_usr);
+ printf("\n");
+
+ printf(" r8_fiq: %08"PRIx32"\n", regs->r8_fiq);
+
+ printf(" r9_fiq: %08"PRIx32"\t", regs->r9_fiq);
+ printf("r10_fiq: %08"PRIx32"\t", regs->r10_fiq);
+ printf("r11_fiq: %08"PRIx32"\n", regs->r11_fiq);
+
+ printf("r12_fiq: %08"PRIx32"\n", regs->r12_fiq);
+ printf("\n");
}
+
+#ifdef __aarch64__
+static void print_ctx_64(vcpu_guest_context_t *ctx)
+{
+ vcpu_guest_core_regs_t *regs = &ctx->user_regs;
+
+ printf("PC: %016"PRIx64" ", regs->pc64);
+ print_symbol(regs->pc64);
+ printf("\n");
+
+ printf("LR: %016"PRIx64"zn", regs->x30);
+ printf("ELR_EL1: %016"PRIx64"\n", regs->elr_el1);
+
+ printf("CPSR: %08"PRIx32"\n", regs->cpsr);
+ printf("SPSR_EL1: %08"PRIx32"\n", regs->spsr_el1);
+
+ printf("SP_EL0: %016"PRIx64"\n", regs->sp_el0);
+ printf("SP_EL1: %016"PRIx64"\n", regs->sp_el1);
+
+ printf("\n");
+ printf(" x0: %016"PRIx64"\t", regs->x0);
+ printf(" x1: %016"PRIx64"\t", regs->x1);
+ printf(" x2: %016"PRIx64"\n", regs->x2);
+
+ printf(" x3: %016"PRIx64"\t", regs->x3);
+ printf(" x4: %016"PRIx64"\t", regs->x4);
+ printf(" x5: %016"PRIx64"\n", regs->x5);
+
+ printf(" x6: %016"PRIx64"\t", regs->x6);
+ printf(" x7: %016"PRIx64"\t", regs->x7);
+ printf(" x8: %016"PRIx64"\n", regs->x8);
+
+ printf(" x9: %016"PRIx64"\t", regs->x9);
+ printf("x10: %016"PRIx64"\t", regs->x10);
+ printf("x11: %016"PRIx64"\n", regs->x11);
+
+ printf("x12: %016"PRIx64"\t", regs->x12);
+ printf("x13: %016"PRIx64"\t", regs->x13);
+ printf("x14: %016"PRIx64"\n", regs->x14);
+
+ printf("x15: %016"PRIx64"\t", regs->x15);
+ printf("x16: %016"PRIx64"\t", regs->x16);
+ printf("x17: %016"PRIx64"\n", regs->x17);
+
+ printf("x18: %016"PRIx64"\t", regs->x18);
+ printf("x19: %016"PRIx64"\t", regs->x19);
+ printf("x20: %016"PRIx64"\n", regs->x20);
+
+ printf("x21: %016"PRIx64"\t", regs->x21);
+ printf("x22: %016"PRIx64"\t", regs->x22);
+ printf("x23: %016"PRIx64"\n", regs->x23);
+
+ printf("x24: %016"PRIx64"\t", regs->x24);
+ printf("x25: %016"PRIx64"\t", regs->x25);
+ printf("x26: %016"PRIx64"\n", regs->x26);
+
+ printf("x27: %016"PRIx64"\t", regs->x27);
+ printf("x28: %016"PRIx64"\t", regs->x28);
+ printf("x29: %016"PRIx64"\n", regs->x29);
+ printf("\n");
+}
+#endif /* __aarch64__ */
+
+static void print_ctx(vcpu_guest_context_any_t *ctx_any)
+{
+ vcpu_guest_context_t *ctx = &ctx_any->c;
+
+#ifdef __aarch64__
+ if (ctx->user_regs.cpsr & PSR_MODE_BIT)
+ print_ctx_32(ctx);
+ else
+ print_ctx_64(ctx);
+#else
+ print_ctx_32(ctx);
+#endif
+
+ printf("SCTLR: %08"PRIx32"\n", ctx->sctlr);
+ printf("TTBCR: %08"PRIx32"\n", ctx->ttbcr);
+ printf("TTBR0: %016"PRIx64"\n", ctx->ttbr0);
+ printf("TTBR1: %016"PRIx64"\n", ctx->ttbr1);
+}
+
#endif
#ifndef NO_TRANSLATION
--
1.7.9.1
>>> On 12.04.13 at 15:13, Ian Campbell <ian.campbell@citrix.com> wrote: > Signed-off-by: Ian Campbell <ian.campbell@citrix.com>Acked-by: Jan Beulich <jbeulich@suse.com>> --- > tools/xentrace/xenctx.c | 302 +---------------------------------------------- > 1 files changed, 1 insertions(+), 301 deletions(-) > > diff --git a/tools/xentrace/xenctx.c b/tools/xentrace/xenctx.c > index 62327f7..70a5455 100644 > --- a/tools/xentrace/xenctx.c > +++ b/tools/xentrace/xenctx.c > @@ -49,18 +49,6 @@ int guest_word_size = sizeof (unsigned long); > /* Word-length of the context record we get from xen */ > int ctxt_word_size = sizeof (unsigned long); > int guest_protected_mode = 1; > -#elif defined (__ia64__) > -/* On ia64, we can''t translate virtual address to physical address. */ > -#define NO_TRANSLATION > -typedef size_t guest_word_t; > - > -/* Which registers should be displayed. */ > -int disp_cr_regs; > -int disp_ar_regs; > -int disp_br_regs; > -int disp_bank_regs; > -int disp_tlb; > - > #elif defined(__arm__) > #define NO_TRANSLATION > typedef uint64_t guest_word_t; > @@ -442,248 +430,6 @@ static guest_word_t > frame_pointer(vcpu_guest_context_any_t *ctx) > return ctx->x64.user_regs.rbp; > } > > -#elif defined(__ia64__) > - > -#define PTE_ED_SHIFT 52 > -#define PTE_ED_MASK 1 > -#define PTE_PPN_SHIFT 12 > -#define PTE_PPN_MASK 0x3fffffffff > -#define PTE_AR_SHIFT 9 > -#define PTE_AR_MASK 7 > -#define PTE_PL_SHIFT 7 > -#define PTE_PL_MASK 3 > -#define PTE_D_SHIFT 6 > -#define PTE_D_MASK 1 > -#define PTE_A_SHIFT 5 > -#define PTE_A_MASK 1 > -#define PTE_MA_SHIFT 2 > -#define PTE_MA_MASK 7 > -#define PTE_P_SHIFT 0 > -#define PTE_P_MASK 1 > -#define ITIR_KEY_SHIFT 8 > -#define ITIR_KEY_MASK 0xffffff > -#define ITIR_PS_SHIFT 2 > -#define ITIR_PS_MASK 0x3f > -#define ITIR_PS_MIN 12 > -#define ITIR_PS_MAX 28 > -#define RR_RID_SHIFT 8 > -#define RR_RID_MASK 0xffffff > -#define PSR_BN (1UL << 44) > -#define CFM_SOF_MASK 0x3f > - > -static void print_tr(int i, const struct ia64_tr_entry *tr) > -{ > - int ps_val, ma_val; > - unsigned long pa; > - > - static const char ps[][5] = {" 4K", " 8K", " 16K", " ", > - " 64K", " ", "256K", " ", > - " 1M", " ", " 4M", " ", > - " 16M", " ", " 64M", " ", > - "256M"}; > - static const char ma[][4] = {"WB ", " ", " ", " ", > - "UC ", "UCE", "WC ", "Nat"}; > - > - ps_val = tr->itir >> ITIR_PS_SHIFT & ITIR_PS_MASK; > - ma_val = tr->pte >> PTE_MA_SHIFT & PTE_MA_MASK; > - pa = (tr->pte >> PTE_PPN_SHIFT & PTE_PPN_MASK) << PTE_PPN_SHIFT; > - pa = (pa >> ps_val) << ps_val; > - printf(" [%d] %ld %06lx %016lx %013lx %02x %s %ld %ld %ld %ld " > - "%ld %d %s %06lx\n", i, > - tr->pte >> PTE_P_SHIFT & PTE_P_MASK, > - tr->rid >> RR_RID_SHIFT & RR_RID_MASK, > - tr->vadr, pa, ps_val, > - ((ps_val >= ITIR_PS_MIN && ps_val <= ITIR_PS_MAX) ? > - ps[ps_val - ITIR_PS_MIN] : " "), > - tr->pte >> PTE_ED_SHIFT & PTE_ED_MASK, > - tr->pte >> PTE_PL_SHIFT & PTE_PL_MASK, > - tr->pte >> PTE_AR_SHIFT & PTE_AR_MASK, > - tr->pte >> PTE_A_SHIFT & PTE_A_MASK, > - tr->pte >> PTE_D_SHIFT & PTE_D_MASK, > - ma_val, ma[ma_val], > - tr->itir >> ITIR_KEY_SHIFT & ITIR_KEY_MASK); > -} > - > -void print_ctx(vcpu_guest_context_any_t *ctx) > -{ > - struct vcpu_guest_context_regs *regs = &ctx->c.regs; > - struct vcpu_tr_regs *tr = &ctx->c.regs.tr; > - int i; > - unsigned int rbs_size, cfm_sof; > - > - printf(" ip: %016lx ", regs->ip); > - print_symbol(regs->ip); > - printf("\n"); > - printf(" psr: %016lx ", regs->psr); > - printf(" cfm: %016lx ", regs->cfm); > - printf(" pr: %016lx\n", regs->pr); > - > - if (disp_br_regs) { > - printf(" b0: %016lx ", regs->b[0]); > - printf(" b1: %016lx ", regs->b[1]); > - printf(" b2: %016lx\n", regs->b[2]); > - printf(" b3: %016lx ", regs->b[3]); > - printf(" b4: %016lx ", regs->b[4]); > - printf(" b5: %016lx\n", regs->b[5]); > - printf(" b6: %016lx ", regs->b[6]); > - printf(" b7: %016lx\n", regs->b[7]); > - } else { > - printf(" b0: %016lx\n", regs->b[0]); > - } > - > - if (disp_cr_regs) { > - printf ("\n" > - " CR:\n"); > - printf(" dcr: %016lx ", regs->cr.dcr); > - printf(" itm: %016lx ", regs->cr.itm); > - printf(" iva: %016lx\n", regs->cr.iva); > - printf(" pta: %016lx ", regs->cr.pta); > - printf(" ipsr: %016lx ", regs->cr.ipsr); > - printf(" isr: %016lx\n", regs->cr.isr); > - printf(" iip: %016lx ", regs->cr.iip); > - printf(" ifa: %016lx ", regs->cr.ifa); > - printf(" itir: %016lx\n", regs->cr.itir); > - printf(" iipa: %016lx ", regs->cr.iipa); > - printf(" ifs: %016lx ", regs->cr.ifs); > - printf(" iim: %016lx\n", regs->cr.iim); > - printf(" iha: %016lx ", regs->cr.iha); > - printf(" lid: %016lx ", regs->cr.lid); > - printf(" ivr: %016lx\n", regs->cr.ivr); > - printf(" tpr: %016lx ", regs->cr.tpr); > - printf(" eoi: %016lx ", regs->cr.eoi); > - printf(" irr0: %016lx\n", regs->cr.irr[0]); > - printf(" irr1: %016lx ", regs->cr.irr[1]); > - printf(" irr2: %016lx ", regs->cr.irr[2]); > - printf(" irr3: %016lx\n", regs->cr.irr[3]); > - printf(" itv: %016lx ", regs->cr.itv); > - printf(" pmv: %016lx ", regs->cr.pmv); > - printf(" cmcv: %016lx\n", regs->cr.cmcv); > - printf(" lrr0: %016lx ", regs->cr.lrr0); > - printf(" lrr1: %016lx ", regs->cr.lrr1); > - printf(" ev_cb:%016lx\n", ctx->c.event_callback_ip); > - > - } > - if (disp_ar_regs) { > - printf ("\n" > - " AR:\n"); > - printf(" kr0: %016lx ", regs->ar.kr[0]); > - printf(" kr1: %016lx ", regs->ar.kr[1]); > - printf(" kr2: %016lx\n", regs->ar.kr[2]); > - printf(" kr3: %016lx ", regs->ar.kr[3]); > - printf(" kr4: %016lx ", regs->ar.kr[4]); > - printf(" kr5: %016lx\n", regs->ar.kr[5]); > - printf(" kr6: %016lx ", regs->ar.kr[6]); > - printf(" kr7: %016lx ", regs->ar.kr[7]); > - printf(" rsc: %016lx\n", regs->ar.rsc); > - printf(" bsp: %016lx ", regs->ar.bsp); > - printf(" bsps: %016lx ", regs->ar.bspstore); > - printf(" rnat: %016lx\n", regs->ar.rnat); > - printf(" csd: %016lx ", regs->ar.csd); > - printf(" ccv: %016lx ", regs->ar.ccv); > - printf(" unat: %016lx\n", regs->ar.unat); > - printf(" fpsr: %016lx ", regs->ar.fpsr); > - printf(" itc: %016lx\n", regs->ar.itc); > - printf(" pfs: %016lx ", regs->ar.pfs); > - printf(" lc: %016lx ", regs->ar.lc); > - printf(" ec: %016lx\n", regs->ar.ec); > - } > - printf("\n"); > - printf(" r1: %016lx ", regs->r[1]); > - printf(" r2: %016lx ", regs->r[2]); > - printf(" r3: %016lx\n", regs->r[3]); > - printf(" r4: %016lx ", regs->r[4]); > - printf(" r5: %016lx ", regs->r[5]); > - printf(" r6: %016lx\n", regs->r[6]); > - printf(" r7: %016lx ", regs->r[7]); > - printf(" r8: %016lx ", regs->r[8]); > - printf(" r9: %016lx\n", regs->r[9]); > - printf(" r10: %016lx ", regs->r[10]); > - printf(" r11: %016lx ", regs->r[11]); > - printf(" sp: %016lx\n", regs->r[12]); > - printf(" tp: %016lx ", regs->r[13]); > - printf(" r14: %016lx ", regs->r[14]); > - printf(" r15: %016lx\n", regs->r[15]); > - if (disp_bank_regs) { > - printf(" Bank %d (current) Bank %d\n", > - (regs->psr & PSR_BN) ? 1 : 0, (regs->psr & PSR_BN) ? 0 : 1); > - printf ("16:%016lx ", regs->r[16]); > - printf ("17:%016lx ", regs->r[17]); > - printf ("16:%016lx ", regs->bank[0]); > - printf ("17:%016lx\n", regs->bank[1]); > - printf ("18:%016lx ", regs->r[18]); > - printf ("19:%016lx ", regs->r[19]); > - printf ("18:%016lx ", regs->bank[2]); > - printf ("19:%016lx\n", regs->bank[3]); > - printf ("20:%016lx ", regs->r[20]); > - printf ("21:%016lx ", regs->r[21]); > - printf ("20:%016lx ", regs->bank[4]); > - printf ("21:%016lx\n", regs->bank[5]); > - printf ("22:%016lx ", regs->r[22]); > - printf ("23:%016lx ", regs->r[23]); > - printf ("22:%016lx ", regs->bank[6]); > - printf ("23:%016lx\n", regs->bank[7]); > - printf ("24:%016lx ", regs->r[24]); > - printf ("25:%016lx ", regs->r[25]); > - printf ("24:%016lx ", regs->bank[8]); > - printf ("25:%016lx\n", regs->bank[9]); > - printf ("26:%016lx ", regs->r[26]); > - printf ("27:%016lx ", regs->r[27]); > - printf ("26:%016lx ", regs->bank[10]); > - printf ("27:%016lx\n", regs->bank[11]); > - printf ("28:%016lx ", regs->r[28]); > - printf ("29:%016lx ", regs->r[29]); > - printf ("28:%016lx ", regs->bank[12]); > - printf ("29:%016lx\n", regs->bank[13]); > - printf ("30:%016lx ", regs->r[30]); > - printf ("31:%016lx ", regs->r[31]); > - printf ("30:%016lx ", regs->bank[14]); > - printf ("31:%016lx\n", regs->bank[15]); > - } else { > - printf(" r16: %016lx ", regs->r[16]); > - printf(" r17: %016lx ", regs->r[17]); > - printf(" r18: %016lx\n", regs->r[18]); > - printf(" r19: %016lx ", regs->r[19]); > - printf(" r20: %016lx ", regs->r[20]); > - printf(" r21: %016lx\n", regs->r[21]); > - printf(" r22: %016lx ", regs->r[22]); > - printf(" r23: %016lx ", regs->r[23]); > - printf(" r24: %016lx\n", regs->r[24]); > - printf(" r25: %016lx ", regs->r[25]); > - printf(" r26: %016lx ", regs->r[26]); > - printf(" r27: %016lx\n", regs->r[27]); > - printf(" r28: %016lx ", regs->r[28]); > - printf(" r29: %016lx ", regs->r[29]); > - printf(" r30: %016lx\n", regs->r[30]); > - printf(" r31: %016lx\n", regs->r[31]); > - } > - > - printf("\n"); > - rbs_size = (regs->ar.bsp - regs->ar.bspstore) / 8; > - cfm_sof = (regs->cfm & CFM_SOF_MASK); > - for (i = 0; i < cfm_sof; i++) { > - int off = cfm_sof - i; > - unsigned int rbs_off > - (((62 - ((rbs_size + regs->rbs_voff) % 63) + off)) / 63) + off; > - if (rbs_off > rbs_size) > - break; > - printf(" r%02d: %016lx%s", 32 + i, > - regs->rbs[rbs_size - rbs_off], > - (i % 3) != 2 ? " " : "\n"); > - } > - if ((i % 3) != 0) > - printf ("\n"); > - > - if (disp_tlb) { > - printf("\n itr: P rid va pa ps ed > pl " > - "ar a d ma key\n"); > - for (i = 0; i < 8; i++) > - print_tr(i, &tr->itrs[i]); > - printf("\n dtr: P rid va pa ps ed > pl " > - "ar a d ma key\n"); > - for (i = 0; i < 8; i++) > - print_tr(i, &tr->dtrs[i]); > - } > -} > #elif defined(__arm__) > static void print_ctx(vcpu_guest_context_any_t *ctx) > { > @@ -940,12 +686,7 @@ static void usage(void) > printf(" -S --stack-trace print a complete stack trace.\n"); > printf(" -k, --kernel-start\n"); > printf(" set user/kernel split. (default > 0xc0000000)\n"); > -#ifdef __ia64__ > - printf(" -r LIST, --regs=LIST display more registers.\n"); > - printf(" -a --all same as --regs=tlb,cr,ar,br,bk\n"); > -#else > printf(" -a --all display more registers\n"); > -#endif > printf(" -C --all-vcpus print info for all vcpus\n"); > } > > @@ -953,19 +694,12 @@ int main(int argc, char **argv) > { > int ch; > int ret; > - static const char *sopts = "fs:hak:SC" > -#ifdef __ia64__ > - "r:" > -#endif > - ; > + static const char *sopts = "fs:hak:SC"; > static const struct option lopts[] = { > {"stack-trace", 0, NULL, ''S''}, > {"symbol-table", 1, NULL, ''s''}, > {"frame-pointers", 0, NULL, ''f''}, > {"kernel-start", 1, NULL, ''k''}, > -#ifdef __ia64__ > - {"regs", 1, NULL, ''r''}, > -#endif > {"all", 0, NULL, ''a''}, > {"all-vcpus", 0, NULL, ''C''}, > {"help", 0, NULL, ''h''}, > @@ -986,43 +720,9 @@ int main(int argc, char **argv) > case ''S'': > xenctx.stack_trace = 1; > break; > -#ifdef __ia64__ > - case ''r'': > - { > - char *r; > - > - r = strtok(optarg, ","); > - while (r) { > - if (strcmp (r, "cr") == 0) > - disp_cr_regs = 1; > - else if (strcmp (r, "ar") == 0) > - disp_ar_regs = 1; > - else if (strcmp (r, "br") == 0) > - disp_br_regs = 1; > - else if (strcmp (r, "bk") == 0) > - disp_bank_regs = 1; > - else if (strcmp (r, "tlb") == 0) > - disp_tlb = 1; > - else { > - fprintf(stderr,"unknown register set %s\n", r); > - exit(-1); > - } > - r = strtok(NULL, "''"); > - } > - } > - break; > - case ''a'': > - disp_cr_regs = 1; > - disp_ar_regs = 1; > - disp_br_regs = 1; > - disp_bank_regs = 1; > - disp_tlb = 1; > - break; > -#else > case ''a'': > xenctx.disp_all = 1; > break; > -#endif > case ''C'': > xenctx.all_vcpus = 1; > break; > -- > 1.7.9.1 > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xen.org > http://lists.xen.org/xen-devel
Ian Campbell
2013-Apr-12 14:25 UTC
Re: [PATCH 4/4] xenctx: Support arm64 and actually implement output for 32 and 64 bit
On Fri, 2013-04-12 at 14:13 +0100, Ian Campbell wrote:
This patch was missing a hunk, v3 is below.
(there''s actually an issue with this change, but I''m going to
comment on
that separately since it is thorny)
8<------------------------------
From b9f077e84b8259c183c7aca0adc13d2da80612f5 Mon Sep 17 00:00:00 2001
From: Ian Campbell <ian.campbell@citrix.com>
Date: Fri, 15 Mar 2013 09:46:35 +0000
Subject: [PATCH] xenctx: Support arm64 and actually implement output for 32
and 64 bit
A bit basic a fuggly but a start.
Signed-off-by: Ian Campbell <ian.campbell@citrix.com>
---
v3: - ensure PSR_MODE_* are defined even when building the tools.
v2: - split ia64 stuff into separate patch
- actually print the registers
---
tools/xentrace/xenctx.c | 141 +++++++++++++++++++++++++++++++++++++++-
xen/include/public/arch-arm.h | 2 +-
2 files changed, 138 insertions(+), 5 deletions(-)
diff --git a/tools/xentrace/xenctx.c b/tools/xentrace/xenctx.c
index 1984a31..060e480 100644
--- a/tools/xentrace/xenctx.c
+++ b/tools/xentrace/xenctx.c
@@ -54,6 +54,11 @@ int guest_protected_mode = 1;
typedef uint64_t guest_word_t;
#define FMT_32B_WORD "%08llx"
#define FMT_64B_WORD "%016llx"
+#elif defined(__aarch64__)
+#define NO_TRANSLATION
+typedef uint64_t guest_word_t;
+#define FMT_32B_WORD "%08lx"
+#define FMT_64B_WORD "%016lx"
#endif
struct symbol {
@@ -430,12 +435,140 @@ static guest_word_t
frame_pointer(vcpu_guest_context_any_t *ctx)
return ctx->x64.user_regs.rbp;
}
-#elif defined(__arm__)
-static void print_ctx(vcpu_guest_context_any_t *ctx)
+#elif defined(__arm__) || defined(__aarch64__)
+
+static void print_ctx_32(vcpu_guest_context_t *ctx)
{
- /* XXX: properly implement this */
- print_symbol(0);
+ vcpu_guest_core_regs_t *regs = &ctx->user_regs;
+
+ printf("PC: %08"PRIx32" ", regs->pc32);
+ print_symbol(regs->pc32);
+ printf("\n");
+ printf("CPSR: %08"PRIx32"\n", regs->cpsr);
+ printf("USR: SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->sp_usr, regs->lr_usr);
+ printf("SVC: SPSR:%08"PRIx32" SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->spsr_svc, regs->sp_svc, regs->lr_svc);
+ printf("FIQ: SPSR:%08"PRIx32" SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->spsr_fiq, regs->sp_fiq, regs->lr_fiq);
+ printf("IRQ: SPSR:%08"PRIx32" SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->spsr_irq, regs->sp_irq, regs->lr_irq);
+ printf("ABT: SPSR:%08"PRIx32" SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->spsr_abt, regs->sp_abt, regs->lr_abt);
+ printf("UND: SPSR:%08"PRIx32" SP:%08"PRIx32"
LR:%08"PRIx32"\n",
+ regs->spsr_und, regs->sp_und, regs->lr_und);
+
+ printf("\n");
+ printf(" r0_usr: %08"PRIx32"\t", regs->r0_usr);
+ printf(" r1_usr: %08"PRIx32"\t", regs->r1_usr);
+ printf(" r2_usr: %08"PRIx32"\n", regs->r2_usr);
+
+ printf(" r3_usr: %08"PRIx32"\t", regs->r3_usr);
+ printf(" r4_usr: %08"PRIx32"\t", regs->r4_usr);
+ printf(" r5_usr: %08"PRIx32"\n", regs->r5_usr);
+
+ printf(" r6_usr: %08"PRIx32"\t", regs->r6_usr);
+ printf(" r7_usr: %08"PRIx32"\t", regs->r7_usr);
+ printf(" r8_usr: %08"PRIx32"\n", regs->r8_usr);
+
+ printf(" r9_usr: %08"PRIx32"\t", regs->r9_usr);
+ printf("r10_usr: %08"PRIx32"\t", regs->r10_usr);
+ printf("r11_usr: %08"PRIx32"\n", regs->r11_usr);
+
+ printf("r12_usr: %08"PRIx32"\n", regs->r12_usr);
+ printf("\n");
+
+ printf(" r8_fiq: %08"PRIx32"\n", regs->r8_fiq);
+
+ printf(" r9_fiq: %08"PRIx32"\t", regs->r9_fiq);
+ printf("r10_fiq: %08"PRIx32"\t", regs->r10_fiq);
+ printf("r11_fiq: %08"PRIx32"\n", regs->r11_fiq);
+
+ printf("r12_fiq: %08"PRIx32"\n", regs->r12_fiq);
+ printf("\n");
}
+
+#ifdef __aarch64__
+static void print_ctx_64(vcpu_guest_context_t *ctx)
+{
+ vcpu_guest_core_regs_t *regs = &ctx->user_regs;
+
+ printf("PC: %016"PRIx64" ", regs->pc64);
+ print_symbol(regs->pc64);
+ printf("\n");
+
+ printf("LR: %016"PRIx64"zn", regs->x30);
+ printf("ELR_EL1: %016"PRIx64"\n", regs->elr_el1);
+
+ printf("CPSR: %08"PRIx32"\n", regs->cpsr);
+ printf("SPSR_EL1: %08"PRIx32"\n", regs->spsr_el1);
+
+ printf("SP_EL0: %016"PRIx64"\n", regs->sp_el0);
+ printf("SP_EL1: %016"PRIx64"\n", regs->sp_el1);
+
+ printf("\n");
+ printf(" x0: %016"PRIx64"\t", regs->x0);
+ printf(" x1: %016"PRIx64"\t", regs->x1);
+ printf(" x2: %016"PRIx64"\n", regs->x2);
+
+ printf(" x3: %016"PRIx64"\t", regs->x3);
+ printf(" x4: %016"PRIx64"\t", regs->x4);
+ printf(" x5: %016"PRIx64"\n", regs->x5);
+
+ printf(" x6: %016"PRIx64"\t", regs->x6);
+ printf(" x7: %016"PRIx64"\t", regs->x7);
+ printf(" x8: %016"PRIx64"\n", regs->x8);
+
+ printf(" x9: %016"PRIx64"\t", regs->x9);
+ printf("x10: %016"PRIx64"\t", regs->x10);
+ printf("x11: %016"PRIx64"\n", regs->x11);
+
+ printf("x12: %016"PRIx64"\t", regs->x12);
+ printf("x13: %016"PRIx64"\t", regs->x13);
+ printf("x14: %016"PRIx64"\n", regs->x14);
+
+ printf("x15: %016"PRIx64"\t", regs->x15);
+ printf("x16: %016"PRIx64"\t", regs->x16);
+ printf("x17: %016"PRIx64"\n", regs->x17);
+
+ printf("x18: %016"PRIx64"\t", regs->x18);
+ printf("x19: %016"PRIx64"\t", regs->x19);
+ printf("x20: %016"PRIx64"\n", regs->x20);
+
+ printf("x21: %016"PRIx64"\t", regs->x21);
+ printf("x22: %016"PRIx64"\t", regs->x22);
+ printf("x23: %016"PRIx64"\n", regs->x23);
+
+ printf("x24: %016"PRIx64"\t", regs->x24);
+ printf("x25: %016"PRIx64"\t", regs->x25);
+ printf("x26: %016"PRIx64"\n", regs->x26);
+
+ printf("x27: %016"PRIx64"\t", regs->x27);
+ printf("x28: %016"PRIx64"\t", regs->x28);
+ printf("x29: %016"PRIx64"\n", regs->x29);
+ printf("\n");
+}
+#endif /* __aarch64__ */
+
+static void print_ctx(vcpu_guest_context_any_t *ctx_any)
+{
+ vcpu_guest_context_t *ctx = &ctx_any->c;
+
+#ifdef __aarch64__
+ if (ctx->user_regs.cpsr & PSR_MODE_BIT)
+ print_ctx_32(ctx);
+ else
+ print_ctx_64(ctx);
+#else
+ print_ctx_32(ctx);
+#endif
+
+ printf("SCTLR: %08"PRIx32"\n", ctx->sctlr);
+ printf("TTBCR: %08"PRIx32"\n", ctx->ttbcr);
+ printf("TTBR0: %016"PRIx64"\n", ctx->ttbr0);
+ printf("TTBR1: %016"PRIx64"\n", ctx->ttbr1);
+}
+
#endif
#ifndef NO_TRANSLATION
diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
index 746df8e..2f5ce18 100644
--- a/xen/include/public/arch-arm.h
+++ b/xen/include/public/arch-arm.h
@@ -218,7 +218,7 @@ typedef uint64_t xen_callback_t;
#define PSR_MODE_SYS 0x1f
/* 64 bit modes */
-#ifdef CONFIG_ARM_64
+#ifdef __aarch64__
#define PSR_MODE_BIT 0x10 /* Set iff AArch32 */
#define PSR_MODE_EL3h 0x0d
#define PSR_MODE_EL3t 0x0c
--
1.7.9.1
Ian Campbell
2013-Apr-12 14:36 UTC
Re: [PATCH 4/4] xenctx: Support arm64 and actually implement output for 32 and 64 bit
On Fri, 2013-04-12 at 15:25 +0100, Ian Campbell wrote:> On Fri, 2013-04-12 at 14:13 +0100, Ian Campbell wrote: > (there''s actually an issue with this change, but I''m going to comment on > that separately since it is thorny)[...]> @@ -218,7 +218,7 @@ typedef uint64_t xen_callback_t; > #define PSR_MODE_SYS 0x1f > > /* 64 bit modes */ > -#ifdef CONFIG_ARM_64 > +#ifdef __aarch64__ > #define PSR_MODE_BIT 0x10 /* Set iff AArch32 */ > #define PSR_MODE_EL3h 0x0d > #define PSR_MODE_EL3t 0x0cThere is an issue here which is: tools/include/xen/arch-arm.h:229:0: error: "PSR_MODE_EL0t" redefined [-Werror] In file included from /usr/lib/gcc-cross/aarch64-linux-gnu/4.7/../../../../aarch64-linux-gnu/include/sys/user.h:25:0, from /usr/lib/gcc-cross/aarch64-linux-gnu/4.7/../../../../aarch64-linux-gnu/include/sys/procfs.h:34, from /usr/lib/gcc-cross/aarch64-linux-gnu/4.7/../../../../aarch64-linux-gnu/include/sys/ucontext.h:26, from /usr/lib/gcc-cross/aarch64-linux-gnu/4.7/../../../../aarch64-linux-gnu/include/signal.h:360, from xentrace.c:21: /usr/lib/gcc-cross/aarch64-linux-gnu/4.7/../../../../aarch64-linux-gnu/include/asm/ptrace.h:30:0: note: this is the location of the previous definition This is because Linux''s asm/ptrace.h (which is in the include chain from <signal.h>) defines a bunch of extra symbols. I "solved" it with the hack below, but really I think this is a bug in either Linux on arm64, or perhaps glibc for propagating it. I''ll bring it up with the kernel guys but I wonder if we ought to take the patch as a skanky workaround for now... Ian. 8<------------------- From 8d67164fce5e21e2b6353b02834aa40c81bb714a Mon Sep 17 00:00:00 2001 From: Ian Campbell <ian.campbell@citrix.com> Date: Fri, 12 Apr 2013 15:33:55 +0100 Subject: [PATCH] arm: Undefine PSR_MODE_* in public arch-arm.h These clash with symbols in Linux asm/ptrace.h. This is probably a bug in Linux (or perhaps glibc) but we work around it here. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> --- xen/include/public/arch-arm.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h index 2f5ce18..d1753d8 100644 --- a/xen/include/public/arch-arm.h +++ b/xen/include/public/arch-arm.h @@ -219,6 +219,16 @@ typedef uint64_t xen_callback_t; /* 64 bit modes */ #ifdef __aarch64__ + +#undef PSR_MODE_BIT +#undef PSR_MODE_EL3h +#undef PSR_MODE_EL3t +#undef PSR_MODE_EL2h +#undef PSR_MODE_EL2t +#undef PSR_MODE_EL1h +#undef PSR_MODE_EL1t +#undef PSR_MODE_EL0t + #define PSR_MODE_BIT 0x10 /* Set iff AArch32 */ #define PSR_MODE_EL3h 0x0d #define PSR_MODE_EL3t 0x0c -- 1.7.10.4
Ian Campbell writes ("[PATCH 0/4] arm: xenctx
support"):> This is the last remaining part of "arm: tools: build for arm64 and
> enable cross-compiling for both arm32 and arm64", specifically the
> xenctx bit. Since that posting I''ve split out the ia64 cleanup + a
> whitespace cleanup and made xenctx actually do something useful on ARM.
>
> I''ve runtime tested on arm32 but only build tested on arm64 since
you
> can''t trace dom0 and I''ve not got an arm64 guest kernel
handy.
I''m happy for this to go in so it can have my ack as tools maintainer.
Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>
Ian.
Stefano Stabellini
2013-Apr-24 15:48 UTC
Re: [PATCH 1/4] arm: mark vcpus as initialised when they have been
On Fri, 12 Apr 2013, Ian Campbell wrote:> I noticed this because XEN_DOMCTL_getvcpucontext won''t return anything for a > VCPU which isn''t initialised. > > Signed-off-by: Ian Campbell <ian.campbell@citrix.com>I had the same change in one of my "guest smp" patches. Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>> xen/arch/arm/domain.c | 2 ++ > xen/arch/arm/domain_build.c | 1 + > 2 files changed, 3 insertions(+), 0 deletions(-) > > diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c > index e308813..04be3d6 100644 > --- a/xen/arch/arm/domain.c > +++ b/xen/arch/arm/domain.c > @@ -557,6 +557,8 @@ int arch_set_info_guest( > v->arch.ttbr1 = ctxt->ttbr1; > v->arch.ttbcr = ctxt->ttbcr; > > + v->is_initialised = 1; > + > if ( ctxt->flags & VGCF_online ) > clear_bit(_VPF_down, &v->pause_flags); > else > diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c > index a6d8e9d..17aadcf 100644 > --- a/xen/arch/arm/domain_build.c > +++ b/xen/arch/arm/domain_build.c > @@ -412,6 +412,7 @@ int construct_dom0(struct domain *d) > > discard_initial_modules(); > > + v->is_initialised = 1; > clear_bit(_VPF_down, &v->pause_flags); > > memset(regs, 0, sizeof(*regs)); > -- > 1.7.9.1 >
Ian Campbell
2013-Apr-24 16:19 UTC
Re: [PATCH 1/4] arm: mark vcpus as initialised when they have been
On Wed, 2013-04-24 at 16:48 +0100, Stefano Stabellini wrote:> On Fri, 12 Apr 2013, Ian Campbell wrote: > > I noticed this because XEN_DOMCTL_getvcpucontext won''t return anything for a > > VCPU which isn''t initialised. > > > > Signed-off-by: Ian Campbell <ian.campbell@citrix.com> > > I had the same change in one of my "guest smp" patches. > > > Acked-by: Stefano Stabellini <stefano.stabellini@eu.citrix.com>Applied, thanks.
On Fri, 2013-04-12 at 16:15 +0100, Ian Jackson wrote:> Ian Campbell writes ("[PATCH 0/4] arm: xenctx support"): > > This is the last remaining part of "arm: tools: build for arm64 and > > enable cross-compiling for both arm32 and arm64", specifically the > > xenctx bit. Since that posting I''ve split out the ia64 cleanup + a > > whitespace cleanup and made xenctx actually do something useful on ARM. > > > > I''ve runtime tested on arm32 but only build tested on arm64 since you > > can''t trace dom0 and I''ve not got an arm64 guest kernel handy. > > I''m happy for this to go in so it can have my ack as tools maintainer. > > Acked-by: Ian Jackson <ian.jackson@eu.citrix.com>Thanks, I applied the tools bit of the series with this and Jan''s ack on #2. Ian.