thr3ads.net - Xen devel - [PATCH 2/3] vpmu intel: Use PMU defines instead of numerals and bit masks [Mar 2013]

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Dietmar Hahn

2013-Mar-27 14:13 UTC

[PATCH 2/3] vpmu intel: Use PMU defines instead of numerals and bit masks

This patch uses the new defines in Intel vPMU to replace existing numerals and
bit masks.
Thanks,
Dietmar.

Signed-off-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>


Index: xen-unstable.hg/xen/arch/x86/hvm/vmx/vpmu_core2.c
==================================================================---
xen-unstable.hg.orig/xen/arch/x86/hvm/vmx/vpmu_core2.c
+++ xen-unstable.hg/xen/arch/x86/hvm/vmx/vpmu_core2.c
@@ -39,6 +39,23 @@
 #include <asm/hvm/vmx/vpmu_core2.h>
 
 /*
+ * See Intel SDM Vol 2a Instruction Set Referenc for CPUID instruction.
+ * cpuid 0xa - Architectural Performance Monitoring Leaf
+ * Register eax
+ */
+#define X86_FEATURE_PMU_VER_OFF   0  /* Version ID */
+#define FEATURE_PMU_VER_BITS      8  /* 8 bits 0..7 */
+#define X86_FEATURE_NUM_GEN_OFF   8  /* Number of general pmu registers */
+#define FEATURE_NUM_GEN_BITS      8  /* 8 bits 8..15 */
+#define X86_FEATURE_GEN_WIDTH_OFF 16 /* Width of general pmu registers */
+#define FEATURE_GEN_WIDTH_BITS    8  /* 8 bits 16..23 */
+/* Register edx */
+#define X86_FEATURE_NUM_FIX_OFF   0  /* Number of fixed pmu registers */
+#define FEATURE_NUM_FIX_BITS      5  /* 5 bits 0..4 */
+#define X86_FEATURE_FIX_WIDTH_OFF 5  /* Width of fixed pmu registers */
+#define FEATURE_FIX_WIDTH_BITS    8  /* 8 bits 5..12 */
+
+/*
  * QUIRK to workaround an issue on Nehalem processors currently seen
  * on family 6 cpus E5520 (model 26) and X7542 (model 46).
  * The issue leads to endless PMC interrupt loops on the processor.
@@ -130,14 +147,18 @@ static const struct pmumsr core2_ctrls  };
 static int arch_pmc_cnt;
 
+/*
+ * Read the number of general counters via CPUID.EAX[0xa].EAX[8..15]
+ */
 static int core2_get_pmc_count(void)
 {
     u32 eax, ebx, ecx, edx;
 
     if ( arch_pmc_cnt == 0 )
     {
+        u32 mask = ((1 << FEATURE_NUM_GEN_BITS) - 1) <<
X86_FEATURE_NUM_GEN_OFF;
         cpuid(0xa, &eax, &ebx, &ecx, &edx);
-        arch_pmc_cnt = (eax & 0xff00) >> 8;
+        arch_pmc_cnt = (eax & mask) >> X86_FEATURE_NUM_GEN_OFF;
     }
 
     return arch_pmc_cnt;
@@ -153,9 +174,11 @@ static u64 core2_calc_intial_glb_ctrl_ms
 /* edx bits 5-12: Bit width of fixed-function performance counters  */
 static int core2_get_bitwidth_fix_count(void)
 {
-    u32 eax, ebx, ecx, edx;
+    u32 eax, ebx, ecx, edx, mask;
+
+    mask = ((1 << FEATURE_FIX_WIDTH_BITS) - 1) <<
X86_FEATURE_FIX_WIDTH_OFF;
     cpuid(0xa, &eax, &ebx, &ecx, &edx);
-    return ((edx & 0x1fe0) >> 5);
+    return ((edx & mask) >> X86_FEATURE_FIX_WIDTH_OFF);
 }
 
 static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)
@@ -731,23 +754,6 @@ struct arch_vpmu_ops core2_vpmu_ops = {
     .arch_vpmu_load = core2_vpmu_load
 };
 
-/*
- * See Intel SDM Vol 2a Instruction Set Referenc for CPUID instruction.
- * cpuid 0xa - Architectural Performance Monitoring Leaf
- * Register eax
- */
-#define X86_FEATURE_PMU_VER_OFF   0  /* Version ID */
-#define FEATURE_PMU_VER_BITS      8  /* 8 bits 0..7 */
-#define X86_FEATURE_NUM_GEN_OFF   8  /* Number of general pmu registers */
-#define FEATURE_NUM_GEN_BITS      8  /* 8 bits 8..15 */
-#define X86_FEATURE_GEN_WIDTH_OFF 16 /* Width of general pmu registers */
-#define FEATURE_GEN_WIDTH_BITS    8  /* 8 bits 16..23 */
-/* Register edx */
-#define X86_FEATURE_NUM_FIX_OFF   0  /* Number of fixed pmu registers */
-#define FEATURE_NUM_FIX_BITS      5  /* 5 bits 0..4 */
-#define X86_FEATURE_FIX_WIDTH_OFF 5  /* Width of fixed pmu registers */
-#define FEATURE_FIX_WIDTH_BITS    8  /* 8 bits 5..12 */
-
 static void core2_no_vpmu_do_cpuid(unsigned int input,
                                 unsigned int *eax, unsigned int *ebx,
                                 unsigned int *ecx, unsigned int *edx)

-- 
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Konrad Rzeszutek Wilk

2013-Mar-27 15:25 UTC

head link

Re: [PATCH 2/3] vpmu intel: Use PMU defines instead of numerals and bit masks

On Wed, Mar 27, 2013 at 03:13:13PM +0100, Dietmar Hahn
wrote:> This patch uses the new defines in Intel vPMU to replace existing numerals
and
> bit masks.
> Thanks,
> Dietmar.
> 
> Signed-off-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com>
> 
> 
> Index: xen-unstable.hg/xen/arch/x86/hvm/vmx/vpmu_core2.c
> ==================================================================> ---
xen-unstable.hg.orig/xen/arch/x86/hvm/vmx/vpmu_core2.c
> +++ xen-unstable.hg/xen/arch/x86/hvm/vmx/vpmu_core2.c
> @@ -39,6 +39,23 @@
>  #include <asm/hvm/vmx/vpmu_core2.h>
>  
>  /*
> + * See Intel SDM Vol 2a Instruction Set Referenc for CPUID instruction.
> + * cpuid 0xa - Architectural Performance Monitoring Leaf
Chapter ?
> + * Register eax
> + */
> +#define X86_FEATURE_PMU_VER_OFF   0  /* Version ID */
> +#define FEATURE_PMU_VER_BITS      8  /* 8 bits 0..7 */
> +#define X86_FEATURE_NUM_GEN_OFF   8  /* Number of general pmu registers */
> +#define FEATURE_NUM_GEN_BITS      8  /* 8 bits 8..15 */
> +#define X86_FEATURE_GEN_WIDTH_OFF 16 /* Width of general pmu registers */
> +#define FEATURE_GEN_WIDTH_BITS    8  /* 8 bits 16..23 */
> +/* Register edx */
> +#define X86_FEATURE_NUM_FIX_OFF   0  /* Number of fixed pmu registers */
> +#define FEATURE_NUM_FIX_BITS      5  /* 5 bits 0..4 */
> +#define X86_FEATURE_FIX_WIDTH_OFF 5  /* Width of fixed pmu registers */
> +#define FEATURE_FIX_WIDTH_BITS    8  /* 8 bits 5..12 */
I think the ''X86_FEATURE'' and ''FEATURE''
could be just chopped off?
Then it is ''PMU_VER_BITS'' or ''NUM_GEN_OFF''. 
Perhaps also have the
mask in there?

That way you can could do:

PMU_VERSION_SHIFT
PMU_VERSION_MASK

And just use those in the logic below.

And for the other:

PMU_GENERAL_NR_SHIFT
PMU_GENERAL_NR_MASK
and
PMU_FIXED_NR_SHIFT
PMU_FIXED_NR_MASK?

PMU_FIXED_WIDTH_SHIFT
... and so on.
> +
> +/*
>   * QUIRK to workaround an issue on Nehalem processors currently seen
>   * on family 6 cpus E5520 (model 26) and X7542 (model 46).
>   * The issue leads to endless PMC interrupt loops on the processor.
> @@ -130,14 +147,18 @@ static const struct pmumsr core2_ctrls >  };
>  static int arch_pmc_cnt;
>  
> +/*
> + * Read the number of general counters via CPUID.EAX[0xa].EAX[8..15]
> + */
>  static int core2_get_pmc_count(void)
>  {
>      u32 eax, ebx, ecx, edx;
>  
>      if ( arch_pmc_cnt == 0 )
>      {
> +        u32 mask = ((1 << FEATURE_NUM_GEN_BITS) - 1) <<
X86_FEATURE_NUM_GEN_OFF;
>          cpuid(0xa, &eax, &ebx, &ecx, &edx);
> -        arch_pmc_cnt = (eax & 0xff00) >> 8;
> +        arch_pmc_cnt = (eax & mask) >> X86_FEATURE_NUM_GEN_OFF;
>      }
>  
>      return arch_pmc_cnt;
> @@ -153,9 +174,11 @@ static u64 core2_calc_intial_glb_ctrl_ms
>  /* edx bits 5-12: Bit width of fixed-function performance counters  */
>  static int core2_get_bitwidth_fix_count(void)
>  {
> -    u32 eax, ebx, ecx, edx;
> +    u32 eax, ebx, ecx, edx, mask;
> +
> +    mask = ((1 << FEATURE_FIX_WIDTH_BITS) - 1) <<
X86_FEATURE_FIX_WIDTH_OFF;
>      cpuid(0xa, &eax, &ebx, &ecx, &edx);
> -    return ((edx & 0x1fe0) >> 5);
> +    return ((edx & mask) >> X86_FEATURE_FIX_WIDTH_OFF);
>  }
>  
>  static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)
> @@ -731,23 +754,6 @@ struct arch_vpmu_ops core2_vpmu_ops = {
>      .arch_vpmu_load = core2_vpmu_load
>  };
>  
> -/*
> - * See Intel SDM Vol 2a Instruction Set Referenc for CPUID instruction.
> - * cpuid 0xa - Architectural Performance Monitoring Leaf
> - * Register eax
> - */
> -#define X86_FEATURE_PMU_VER_OFF   0  /* Version ID */
> -#define FEATURE_PMU_VER_BITS      8  /* 8 bits 0..7 */
> -#define X86_FEATURE_NUM_GEN_OFF   8  /* Number of general pmu registers */
> -#define FEATURE_NUM_GEN_BITS      8  /* 8 bits 8..15 */
> -#define X86_FEATURE_GEN_WIDTH_OFF 16 /* Width of general pmu registers */
> -#define FEATURE_GEN_WIDTH_BITS    8  /* 8 bits 16..23 */
> -/* Register edx */
> -#define X86_FEATURE_NUM_FIX_OFF   0  /* Number of fixed pmu registers */
> -#define FEATURE_NUM_FIX_BITS      5  /* 5 bits 0..4 */
> -#define X86_FEATURE_FIX_WIDTH_OFF 5  /* Width of fixed pmu registers */
> -#define FEATURE_FIX_WIDTH_BITS    8  /* 8 bits 5..12 */
> -
>  static void core2_no_vpmu_do_cpuid(unsigned int input,
>                                  unsigned int *eax, unsigned int *ebx,
>                                  unsigned int *ecx, unsigned int *edx)
> 
> -- 
> Company details: http://ts.fujitsu.com/imprint.html
> Index: xen-unstable.hg/xen/arch/x86/hvm/vmx/vpmu_core2.c
> ==================================================================> ---
xen-unstable.hg.orig/xen/arch/x86/hvm/vmx/vpmu_core2.c
> +++ xen-unstable.hg/xen/arch/x86/hvm/vmx/vpmu_core2.c
> @@ -39,6 +39,23 @@
>  #include <asm/hvm/vmx/vpmu_core2.h>
>  
>  /*
> + * See Intel SDM Vol 2a Instruction Set Referenc for CPUID instruction.
> + * cpuid 0xa - Architectural Performance Monitoring Leaf
> + * Register eax
> + */
> +#define X86_FEATURE_PMU_VER_OFF   0  /* Version ID */
> +#define FEATURE_PMU_VER_BITS      8  /* 8 bits 0..7 */
> +#define X86_FEATURE_NUM_GEN_OFF   8  /* Number of general pmu registers */
> +#define FEATURE_NUM_GEN_BITS      8  /* 8 bits 8..15 */
> +#define X86_FEATURE_GEN_WIDTH_OFF 16 /* Width of general pmu registers */
> +#define FEATURE_GEN_WIDTH_BITS    8  /* 8 bits 16..23 */
> +/* Register edx */
> +#define X86_FEATURE_NUM_FIX_OFF   0  /* Number of fixed pmu registers */
> +#define FEATURE_NUM_FIX_BITS      5  /* 5 bits 0..4 */
> +#define X86_FEATURE_FIX_WIDTH_OFF 5  /* Width of fixed pmu registers */
> +#define FEATURE_FIX_WIDTH_BITS    8  /* 8 bits 5..12 */
> +
> +/*
>   * QUIRK to workaround an issue on Nehalem processors currently seen
>   * on family 6 cpus E5520 (model 26) and X7542 (model 46).
>   * The issue leads to endless PMC interrupt loops on the processor.
> @@ -130,14 +147,18 @@ static const struct pmumsr core2_ctrls >  };
>  static int arch_pmc_cnt;
>  
> +/*
> + * Read the number of general counters via CPUID.EAX[0xa].EAX[8..15]
> + */
>  static int core2_get_pmc_count(void)
>  {
>      u32 eax, ebx, ecx, edx;
>  
>      if ( arch_pmc_cnt == 0 )
>      {
> +        u32 mask = ((1 << FEATURE_NUM_GEN_BITS) - 1) <<
X86_FEATURE_NUM_GEN_OFF;
>          cpuid(0xa, &eax, &ebx, &ecx, &edx);
> -        arch_pmc_cnt = (eax & 0xff00) >> 8;
> +        arch_pmc_cnt = (eax & mask) >> X86_FEATURE_NUM_GEN_OFF;
>      }
>  
>      return arch_pmc_cnt;
> @@ -153,9 +174,11 @@ static u64 core2_calc_intial_glb_ctrl_ms
>  /* edx bits 5-12: Bit width of fixed-function performance counters  */
>  static int core2_get_bitwidth_fix_count(void)
>  {
> -    u32 eax, ebx, ecx, edx;
> +    u32 eax, ebx, ecx, edx, mask;
> +
> +    mask = ((1 << FEATURE_FIX_WIDTH_BITS) - 1) <<
X86_FEATURE_FIX_WIDTH_OFF;
>      cpuid(0xa, &eax, &ebx, &ecx, &edx);
> -    return ((edx & 0x1fe0) >> 5);
> +    return ((edx & mask) >> X86_FEATURE_FIX_WIDTH_OFF);
>  }
>  
>  static int is_core2_vpmu_msr(u32 msr_index, int *type, int *index)
> @@ -731,23 +754,6 @@ struct arch_vpmu_ops core2_vpmu_ops = {
>      .arch_vpmu_load = core2_vpmu_load
>  };
>  
> -/*
> - * See Intel SDM Vol 2a Instruction Set Referenc for CPUID instruction.
> - * cpuid 0xa - Architectural Performance Monitoring Leaf
> - * Register eax
> - */
> -#define X86_FEATURE_PMU_VER_OFF   0  /* Version ID */
> -#define FEATURE_PMU_VER_BITS      8  /* 8 bits 0..7 */
> -#define X86_FEATURE_NUM_GEN_OFF   8  /* Number of general pmu registers */
> -#define FEATURE_NUM_GEN_BITS      8  /* 8 bits 8..15 */
> -#define X86_FEATURE_GEN_WIDTH_OFF 16 /* Width of general pmu registers */
> -#define FEATURE_GEN_WIDTH_BITS    8  /* 8 bits 16..23 */
> -/* Register edx */
> -#define X86_FEATURE_NUM_FIX_OFF   0  /* Number of fixed pmu registers */
> -#define FEATURE_NUM_FIX_BITS      5  /* 5 bits 0..4 */
> -#define X86_FEATURE_FIX_WIDTH_OFF 5  /* Width of fixed pmu registers */
> -#define FEATURE_FIX_WIDTH_BITS    8  /* 8 bits 5..12 */
> -
>  static void core2_no_vpmu_do_cpuid(unsigned int input,
>                                  unsigned int *eax, unsigned int *ebx,
>                                  unsigned int *ecx, unsigned int *edx)
> _______________________________________________
> Xen-devel mailing list
> Xen-devel@lists.xen.org
> http://lists.xen.org/xen-devel

Dietmar Hahn

2013-Mar-28 12:50 UTC

head link

Re: [PATCH 2/3] vpmu intel: Use PMU defines instead of numerals and bit masks

Am Mittwoch 27 März 2013, 11:25:41 schrieb Konrad Rzeszutek
Wilk:> On Wed, Mar 27, 2013 at 03:13:13PM +0100, Dietmar Hahn wrote:
> >  
> >  /*
> > + * See Intel SDM Vol 2a Instruction Set Referenc for CPUID
instruction.
> > + * cpuid 0xa - Architectural Performance Monitoring Leaf
> 
> Chapter ?
OK.
> 
> > + * Register eax
> > + */
> > +#define X86_FEATURE_PMU_VER_OFF   0  /* Version ID */
> > +#define FEATURE_PMU_VER_BITS      8  /* 8 bits 0..7 */
> > +#define X86_FEATURE_NUM_GEN_OFF   8  /* Number of general pmu
registers */
> > +#define FEATURE_NUM_GEN_BITS      8  /* 8 bits 8..15 */
> > +#define X86_FEATURE_GEN_WIDTH_OFF 16 /* Width of general pmu
registers */
> > +#define FEATURE_GEN_WIDTH_BITS    8  /* 8 bits 16..23 */
> > +/* Register edx */
> > +#define X86_FEATURE_NUM_FIX_OFF   0  /* Number of fixed pmu registers
*/
> > +#define FEATURE_NUM_FIX_BITS      5  /* 5 bits 0..4 */
> > +#define X86_FEATURE_FIX_WIDTH_OFF 5  /* Width of fixed pmu registers
*/
> > +#define FEATURE_FIX_WIDTH_BITS    8  /* 8 bits 5..12 */
> 
> I think the 'X86_FEATURE' and 'FEATURE' could be just
chopped off?
> Then it is 'PMU_VER_BITS' or 'NUM_GEN_OFF'.  Perhaps also
have the
> mask in there?
> 
> That way you can could do:
> 
> PMU_VERSION_SHIFT
> PMU_VERSION_MASK
> 
> And just use those in the logic below.
> 
> And for the other:
> 
> PMU_GENERAL_NR_SHIFT
> PMU_GENERAL_NR_MASK
> and
> PMU_FIXED_NR_SHIFT
> PMU_FIXED_NR_MASK?
> 
> PMU_FIXED_WIDTH_SHIFT
> ... and so on.
Yes, this is much better. Will send another version.
Thanks.

Dietmar


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Xen devel - Mar 2013 - [PATCH 2/3] vpmu intel: Use PMU defines instead of numerals and bit masks

[PATCH 2/3] vpmu intel: Use PMU defines instead of numerals and bit masks

Re: [PATCH 2/3] vpmu intel: Use PMU defines instead of numerals and bit masks

Re: [PATCH 2/3] vpmu intel: Use PMU defines instead of numerals and bit masks