Ian Campbell
2013-Jan-28 10:51 UTC
SMAP feature causing kernel alignment faults due to setting EFLAGS.AC
This appears to be the case in the recent messages in Debian bug #660425 [0] (thread starts at [1] and continues at [2]). SMAP uses EFLAGS.AC in kernel mode to indicate whether accesses to usermode pages should fault or not, which gets confused because under 64-bit Xen kernel == ring3. The obvious fix would be to clear SMAP from the cpuid features (probably in kernel as well as hypervosr) but might we want to do something more advanced? Not sure what, actually implementing PV SMAP would likely require a third set of pagetables with only the kernel mappings... Ian. [0] http://bugs.debian.org/660425 [1] http://lists.debian.org/debian-kernel/2012/12/msg00520.html [2] http://lists.debian.org/debian-kernel/2013/01/msg00464.html
Jan Beulich
2013-Jan-28 11:37 UTC
Re: SMAP feature causing kernel alignment faults due to setting EFLAGS.AC
>>> On 28.01.13 at 11:51, Ian Campbell <Ian.Campbell@citrix.com> wrote: > This appears to be the case in the recent messages in Debian bug #660425 > [0] (thread starts at [1] and continues at [2]). > > SMAP uses EFLAGS.AC in kernel mode to indicate whether accesses to > usermode pages should fault or not, which gets confused because under > 64-bit Xen kernel == ring3. The obvious fix would be to clear SMAP from > the cpuid features (probably in kernel as well as hypervosr) but might > we want to do something more advanced? Not sure what, actually > implementing PV SMAP would likely require a third set of pagetables with > only the kernel mappings...Clearing the feature bit in the (64-bit) kernel is certainly appropriate; whether doing so in the hypervisor is too I''m not sure - that would particularly depend on whether we want to implement a PV variant of it (which I''d expect to suck performance-wise, since the instructions [CLAC/STAC] would need emulation too, yet they necessarily sit in fast paths). For 32-bit PV guests the situation is slightly better in that at least we wouldn''t need another set of page tables. And maybe (if we think the feature is worthwhile) we could even talk Intel into allowing CLAC/STAC in rings 1 and 2. Jan