Hi, these 2 patches add BTS (Branch Trace Store) functionality of Intel Core2 cpus to the vpmu. This feature gets switched on if the cpu is generally supported from the vpmu and if the cpu supports the DS (Debug Store) bit in the cpuid.eax[0x1].edx[21] and if BTS is supported in the MSR_IA32_MISC_ENABLE. If the cpu supports CPL-qualified BTS in the cpuid, this is also supported here. The interface of the struct arch_vpmu_ops was extended with a new function pointer do_cpuid. The function gets called in vmx_cpuid_intercept() allowing the vpmu handling to switch on the DS bit in the guest. If this is not wanted the user must configure this bit in the guest configuration file with the command "cpuid=..." xen/arch/x86/hvm/vmx/vmx.c | 2 + xen/arch/x86/hvm/vmx/vpmu_core2.c | 7 + xen/arch/x86/hvm/vpmu.c | 10 + xen/include/asm-x86/hvm/vpmu.h | 5 + xen/arch/x86/hvm/vmx/vmx.c | 12 +- xen/arch/x86/hvm/vmx/vpmu_core2.c | 156 +++++++++++++++++++++++++----- xen/include/asm-x86/hvm/vmx/vpmu_core2.h | 1 + xen/include/asm-x86/hvm/vpmu.h | 3 + xen/include/asm-x86/msr-index.h | 5 + 9 files changed, 172 insertions(+), 29 deletions(-) Thanks. Dietmar. -- Company details: http://ts.fujitsu.com/imprint.html