arm: implement miscellaneous stuffs
xen/arch/arm/xen/arch_domain.c | 6 ++++++
xen/arch/arm/xen/cache-v7.S | 4 ++--
xen/arch/arm/xen/mm.c | 2 ++
xen/arch/arm/xen/setup.c | 1 +
xen/arch/arm/xen/start.S | 9 +++++++++
5 files changed, 20 insertions(+), 2 deletions(-)
Signed-off-by: Jaemin Ryu <jm77.ryu@samsung.com>
diff -r 5488e4ff45be xen/arch/arm/xen/arch_domain.c
--- a/xen/arch/arm/xen/arch_domain.c Sun Feb 12 15:13:29 2012 +0900
+++ b/xen/arch/arm/xen/arch_domain.c Sun Feb 12 15:48:57 2012 +0900
@@ -199,6 +199,12 @@ void context_switch(struct vcpu *prev, s
ASSERT(prev != next);
ASSERT(vcpu_runnable(next));
+ if (!is_idle_domain(next->domain)) {
+ set_ttbr(next->arch.ctx.ttbr0);
+ cpu_flush_tlb_all();
+ /* TODO : CPU exclusive monitor should be cleared. */
+ }
+
prev = switch_to(prev, &prev->arch.ctx,
&next->arch.ctx);
}
diff -r 5488e4ff45be xen/arch/arm/xen/cache-v7.S
--- a/xen/arch/arm/xen/cache-v7.S Sun Feb 12 15:13:29 2012 +0900
+++ b/xen/arch/arm/xen/cache-v7.S Sun Feb 12 15:48:57 2012 +0900
@@ -61,7 +61,7 @@ ENTRY(cpu_flush_cache_all)
ENTRY(cpu_flush_cache_range)
mrc p15, 1, r3, c0, c0, 0 @ read CSIDR
and r3, r3, #7 @ cache line size encoding
- mov r3, #16 @ size offset
+ mov r2, #16 @ size offset
mov r2, r2, lsl r3 @ actual cache line size
1:
mcr p15, 0, r0, c7, c14, 1 @ clean & invalidate D line / unified line
@@ -74,7 +74,7 @@ 1:
ENTRY(cpu_clean_cache_range)
mrc p15, 1, r3, c0, c0, 0 @ read CSIDR
and r3, r3, #7 @ cache line size encoding
- mov r3, #16 @ size offset
+ mov r2, #16 @ size offset
mov r2, r2, lsl r3 @ actual cache line size
1:
diff -r 5488e4ff45be xen/arch/arm/xen/mm.c
--- a/xen/arch/arm/xen/mm.c Sun Feb 12 15:13:29 2012 +0900
+++ b/xen/arch/arm/xen/mm.c Sun Feb 12 15:48:57 2012 +0900
@@ -266,6 +266,8 @@ unsigned long alloc_page_tables(l1e_t *l
return 0;
}
+ cpu_clean_cache_range(page, page + PAGE_SIZE);
+
wire_page_tables(l1e, page);
return page;
diff -r 5488e4ff45be xen/arch/arm/xen/setup.c
--- a/xen/arch/arm/xen/setup.c Sun Feb 12 15:13:29 2012 +0900
+++ b/xen/arch/arm/xen/setup.c Sun Feb 12 15:48:57 2012 +0900
@@ -195,6 +195,7 @@ static void idle_domain_init(void)
/* idle vcpu is allocated by scheduler_init() */
v = idle_vcpu[0];
+ VCPU_REG(v, ttbr0) = get_ttbr();
set_current_vcpu(v);
}
diff -r 5488e4ff45be xen/arch/arm/xen/start.S
--- a/xen/arch/arm/xen/start.S Sun Feb 12 15:13:29 2012 +0900
+++ b/xen/arch/arm/xen/start.S Sun Feb 12 15:48:57 2012 +0900
@@ -128,6 +128,11 @@ 3:
mcr p15, 0, r5, c10, c2, 0
mcr p15, 0, r6, c10, c2, 1
+ @ Setup Exception Vector Table
+ ldr ip, =exception_vector_table
+ mcr VBAR(ip)
+
+
@ Turn on MMU
ldr r0, =(SCTLR_TRE | SCTLR_SW | SCTLR_Z | SCTLR_I | SCTLR_C | SCTLR_A |
SCTLR_M)
mcr SCTLR(r0)
@@ -219,6 +224,10 @@ ENTRY(slave_cpu_start)
mcr p15, 0, r5, c10, c2, 0
mcr p15, 0, r6, c10, c2, 1
+ @ Setup Exception Vector Table
+ ldr ip, =exception_vector_table
+ mcr VBAR(ip)
+
@ Turn on MMU
ldr r0, =(SCTLR_TRE | SCTLR_SW | SCTLR_Z | SCTLR_I | SCTLR_C | SCTLR_A |
SCTLR_M)
mcr SCTLR(r0)
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