X86: expose Intel new features to pv/hvm
Intel recently release some new features, including
FMA/AVX2/BMI1/BMI2/LZCNT/MOVBE.
Refer to http://software.intel.com/file/36945
This patch expose these new features to pv and hvm.
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
# HG changeset patch
# Parent 4815be3af73cd22d8225754ef5fff0ca03759ad7
diff -r 4815be3af73c tools/libxc/xc_cpufeature.h
--- a/tools/libxc/xc_cpufeature.h Thu Sep 15 15:26:07 2011 +0100
+++ b/tools/libxc/xc_cpufeature.h Thu Nov 17 17:54:17 2011 +0800
@@ -74,6 +74,7 @@
#define X86_FEATURE_TM2 8 /* Thermal Monitor 2 */
#define X86_FEATURE_SSSE3 9 /* Supplemental Streaming SIMD Exts-3 */
#define X86_FEATURE_CID 10 /* Context ID */
+#define X86_FEATURE_FMA 12 /* Fused Multiply Add */
#define X86_FEATURE_CX16 13 /* CMPXCHG16B */
#define X86_FEATURE_XTPR 14 /* Send Task Priority Messages */
#define X86_FEATURE_PDCM 15 /* Perf/Debug Capability MSR */
@@ -81,6 +82,7 @@
#define X86_FEATURE_SSE4_1 19 /* Streaming SIMD Extensions 4.1 */
#define X86_FEATURE_SSE4_2 20 /* Streaming SIMD Extensions 4.2 */
#define X86_FEATURE_X2APIC 21 /* x2APIC */
+#define X86_FEATURE_MOVBE 22 /* movbe instruction */
#define X86_FEATURE_POPCNT 23 /* POPCNT instruction */
#define X86_FEATURE_TSC_DEADLINE 24 /* "tdt" TSC Deadline Timer */
#define X86_FEATURE_AES 25 /* AES acceleration instructions */
@@ -125,7 +127,10 @@
/* Intel-defined CPU features, CPUID level 0x00000007:0 (ebx) */
#define X86_FEATURE_FSGSBASE 0 /* {RD,WR}{FS,GS}BASE instructions */
+#define X86_FEATURE_BMI1 3 /* 1st group bit manipulation extensions */
+#define X86_FEATURE_AVX2 5 /* AVX2 instructions */
#define X86_FEATURE_SMEP 7 /* Supervisor Mode Execution Protection */
+#define X86_FEATURE_BMI2 8 /* 2nd group bit manipulation extensions */
#define X86_FEATURE_ERMS 9 /* Enhanced REP MOVSB/STOSB */
#endif /* __LIBXC_CPUFEATURE_H */
diff -r 4815be3af73c tools/libxc/xc_cpuid_x86.c
--- a/tools/libxc/xc_cpuid_x86.c Thu Sep 15 15:26:07 2011 +0100
+++ b/tools/libxc/xc_cpuid_x86.c Thu Nov 17 17:54:17 2011 +0800
@@ -196,7 +196,8 @@ static void intel_xc_cpuid_policy(
int is_64bit = hypervisor_is_64bit(xch) && is_pae;
/* Only a few features are advertised in Intel''s 0x80000001.
*/
- regs[2] &= (is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0);
+ regs[2] &= (is_64bit ? bitmaskof(X86_FEATURE_LAHF_LM) : 0) |
+ bitmaskof(X86_FEATURE_ABM);
regs[3] &= ((is_pae ? bitmaskof(X86_FEATURE_NX) : 0) |
(is_64bit ? bitmaskof(X86_FEATURE_LM) : 0) |
(is_64bit ? bitmaskof(X86_FEATURE_SYSCALL) : 0) |
@@ -308,9 +309,11 @@ static void xc_cpuid_hvm_policy(
regs[2] &= (bitmaskof(X86_FEATURE_XMM3) |
bitmaskof(X86_FEATURE_PCLMULQDQ) |
bitmaskof(X86_FEATURE_SSSE3) |
+ bitmaskof(X86_FEATURE_FMA) |
bitmaskof(X86_FEATURE_CX16) |
bitmaskof(X86_FEATURE_SSE4_1) |
bitmaskof(X86_FEATURE_SSE4_2) |
+ bitmaskof(X86_FEATURE_MOVBE) |
bitmaskof(X86_FEATURE_POPCNT) |
bitmaskof(X86_FEATURE_AES) |
bitmaskof(X86_FEATURE_F16C) |
@@ -355,7 +358,10 @@ static void xc_cpuid_hvm_policy(
case 0x00000007: /* Intel-defined CPU features */
if ( input[1] == 0 ) {
- regs[1] &= (bitmaskof(X86_FEATURE_SMEP) |
+ regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
+ bitmaskof(X86_FEATURE_AVX2) |
+ bitmaskof(X86_FEATURE_SMEP) |
+ bitmaskof(X86_FEATURE_BMI2) |
bitmaskof(X86_FEATURE_ERMS) |
bitmaskof(X86_FEATURE_FSGSBASE));
} else
@@ -481,8 +487,11 @@ static void xc_cpuid_pv_policy(
case 0x00000007:
if ( input[1] == 0 )
- regs[1] &= (bitmaskof(X86_FEATURE_FSGSBASE) |
- bitmaskof(X86_FEATURE_ERMS));
+ regs[1] &= (bitmaskof(X86_FEATURE_BMI1) |
+ bitmaskof(X86_FEATURE_AVX2) |
+ bitmaskof(X86_FEATURE_BMI2) |
+ bitmaskof(X86_FEATURE_ERMS) |
+ bitmaskof(X86_FEATURE_FSGSBASE));
else
regs[1] = 0;
regs[0] = regs[2] = regs[3] = 0;
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