Hi, I''ve been reading the code in xen/arch/x86/mm/hap and got some questions: 1. Are they the support for intel ept? If so, where is the support for amd rvi? 2. I read the intel manual, it says EPT paging is similar to IA-32e mode which has 4 level page. So, if the xen is running under 32bit PAE mode, is the ept paging still 4 levels? by the way, is dom0 always 32bit pae? 3.EPT is used for GPA->HPA, so is the case of p2m(if I remember correctly), what''s the relationship between them? why do we need p2m when we use hap? 4.Can I use ept to control access to some of the guest pages? Thanks. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
> Hi, I've been reading the code in xen/arch/x86/mm/hap and got some questions:> 1. Are they the support for intel ept? If so, where is the support for amd rvi?hap stands for hardware assisted paging and is an abstract layer for both EPT and NPT (i.e. rvi). You should find some arch specific hooks there too.> 2. I read the intel manual, it says EPT paging is similar to IA-32e mode which has 4 level page. So, if the xen is running under 32bit PAE mode, is the ept paging still 4 levels?They are orthogonal. EPT will be activated only when CPU runs in non-root operation while Xen itself runs in root operation.> by the way, is dom0 always 32bit pae?No, it can be x86_64.> 3.EPT is used for GPA->HPA, so is the case of p2m(if I remember correctly), what's the relationship between them? why do we need p2m when we use hap?p2m is a common virtualization term no matter you use software paging (shadow/vTLB) or hardware assisted paging (EPT/NPT). As you see, software paging obviously needs p2m. Hardware assisted paging incorporates the concept of p2m into hardware, but it's still initialized by software. Xen needs to use p2m for guest MMIO emulation even with ept.> 4.Can I use ept to control access to some of the guest pages?Yes, each guest page has R(Read)/W(Write)/X(eXecution) permission bits in its corresponding EPT entry. Thanks! -Xin _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Hi, At 15:52 +0800 on 09 Jun (1307634772), YAO wrote:> Hi, I''ve been reading the code in xen/arch/x86/mm/hap and got some > questions: > > 1. Are they the support for intel ept? If so, where is the support for amd > rvi?They are the generic support for hardware-assisted paging, i.e. EPT or RVI. RVI is called NPT in the Xen code (and in the AMD manuals).> 2. I read the intel manual, it says EPT paging is similar to IA-32e mode > which has 4 level page. So, if the xen is running under 32bit PAE mode, is > the ept paging still 4 levels?Yes.> by the way, is dom0 always 32bit pae?No.> 3.EPT is used for GPA->HPA, so is the case of p2m(if I remember correctly), > what''s the relationship between them? why do we need p2m when we use hap?Xen needs to be able to look up gfn->mfn for its own purposes, and the p2m contains other informatio. like typing. When a domain is using HAP, its p2m table is stored in the form that the CPU expects for the EPT/RVI table, so there''s no wasted effort or space.> 4.Can I use ept to control access to some of the guest pages?Yes. Have a look at the mem_event domctls for a way to do this from dom0 with callbacks when the guest violates the access controls. Tim. -- Tim Deegan <Tim.Deegan@citrix.com> Principal Software Engineer, Xen Platform Team Citrix Systems UK Ltd. (Company #02937203, SL9 0BG) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel