Fix cpuidle bug
Before invoking C3, bus master disable / flush cache should be the last step;
After resume from C3, bus master enable should be the first step;
Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>
diff -r 9d6da64267ed xen/arch/x86/acpi/cpu_idle.c
--- a/xen/arch/x86/acpi/cpu_idle.c Sun Mar 06 17:28:48 2022 +0800
+++ b/xen/arch/x86/acpi/cpu_idle.c Mon Mar 07 05:31:46 2022 +0800
@@ -457,6 +457,19 @@ static void acpi_processor_idle(void)
case ACPI_STATE_C3:
/*
+ * Before invoking C3, be aware that TSC/APIC timer may be
+ * stopped by H/W. Without carefully handling of TSC/APIC stop issues,
+ * deep C state can''t work correctly.
+ */
+ /* preparing APIC stop */
+ lapic_timer_off();
+
+ /* Get start time (ticks) */
+ t1 = get_tick();
+ /* Trace cpu idle entry */
+ TRACE_4D(TRC_PM_IDLE_ENTRY, cx->idx, t1, exp, pred);
+
+ /*
* disable bus master
* bm_check implies we need ARB_DIS
* !bm_check implies we need cache flush
@@ -485,20 +498,18 @@ static void acpi_processor_idle(void)
ACPI_FLUSH_CPU_CACHE();
}
- /*
- * Before invoking C3, be aware that TSC/APIC timer may be
- * stopped by H/W. Without carefully handling of TSC/APIC stop issues,
- * deep C state can''t work correctly.
- */
- /* preparing APIC stop */
- lapic_timer_off();
-
- /* Get start time (ticks) */
- t1 = get_tick();
- /* Trace cpu idle entry */
- TRACE_4D(TRC_PM_IDLE_ENTRY, cx->idx, t1, exp, pred);
/* Invoke C3 */
acpi_idle_do_entry(cx);
+
+ if ( power->flags.bm_check && power->flags.bm_control )
+ {
+ /* Enable bus master arbitration */
+ spin_lock(&c3_cpu_status.lock);
+ acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
+ c3_cpu_status.count--;
+ spin_unlock(&c3_cpu_status.lock);
+ }
+
/* Get end time (ticks) */
t2 = get_tick();
@@ -508,15 +519,6 @@ static void acpi_processor_idle(void)
/* Trace cpu idle exit */
TRACE_6D(TRC_PM_IDLE_EXIT, cx->idx, t2,
irq_traced[0], irq_traced[1], irq_traced[2], irq_traced[3]);
-
- if ( power->flags.bm_check && power->flags.bm_control )
- {
- /* Enable bus master arbitration */
- spin_lock(&c3_cpu_status.lock);
- if ( c3_cpu_status.count-- == num_online_cpus() )
- acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0);
- spin_unlock(&c3_cpu_status.lock);
- }
/* Re-enable interrupts */
local_irq_enable();
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Is this for 4.0 and 4.1 branches as well? -- Keir On 10/03/2011 08:37, "Liu, Jinsong" <jinsong.liu@intel.com> wrote:> Fix cpuidle bug > > Before invoking C3, bus master disable / flush cache should be the last step; > After resume from C3, bus master enable should be the first step; > > Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> > > diff -r 9d6da64267ed xen/arch/x86/acpi/cpu_idle.c > --- a/xen/arch/x86/acpi/cpu_idle.c Sun Mar 06 17:28:48 2022 +0800 > +++ b/xen/arch/x86/acpi/cpu_idle.c Mon Mar 07 05:31:46 2022 +0800 > @@ -457,6 +457,19 @@ static void acpi_processor_idle(void) > > case ACPI_STATE_C3: > /* > + * Before invoking C3, be aware that TSC/APIC timer may be > + * stopped by H/W. Without carefully handling of TSC/APIC stop > issues, > + * deep C state can''t work correctly. > + */ > + /* preparing APIC stop */ > + lapic_timer_off(); > + > + /* Get start time (ticks) */ > + t1 = get_tick(); > + /* Trace cpu idle entry */ > + TRACE_4D(TRC_PM_IDLE_ENTRY, cx->idx, t1, exp, pred); > + > + /* > * disable bus master > * bm_check implies we need ARB_DIS > * !bm_check implies we need cache flush > @@ -485,20 +498,18 @@ static void acpi_processor_idle(void) > ACPI_FLUSH_CPU_CACHE(); > } > > - /* > - * Before invoking C3, be aware that TSC/APIC timer may be > - * stopped by H/W. Without carefully handling of TSC/APIC stop > issues, > - * deep C state can''t work correctly. > - */ > - /* preparing APIC stop */ > - lapic_timer_off(); > - > - /* Get start time (ticks) */ > - t1 = get_tick(); > - /* Trace cpu idle entry */ > - TRACE_4D(TRC_PM_IDLE_ENTRY, cx->idx, t1, exp, pred); > /* Invoke C3 */ > acpi_idle_do_entry(cx); > + > + if ( power->flags.bm_check && power->flags.bm_control ) > + { > + /* Enable bus master arbitration */ > + spin_lock(&c3_cpu_status.lock); > + acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); > + c3_cpu_status.count--; > + spin_unlock(&c3_cpu_status.lock); > + } > + > /* Get end time (ticks) */ > t2 = get_tick(); > > @@ -508,15 +519,6 @@ static void acpi_processor_idle(void) > /* Trace cpu idle exit */ > TRACE_6D(TRC_PM_IDLE_EXIT, cx->idx, t2, > irq_traced[0], irq_traced[1], irq_traced[2], irq_traced[3]); > - > - if ( power->flags.bm_check && power->flags.bm_control ) > - { > - /* Enable bus master arbitration */ > - spin_lock(&c3_cpu_status.lock); > - if ( c3_cpu_status.count-- == num_online_cpus() ) > - acpi_set_register(ACPI_BITREG_ARB_DISABLE, 0); > - spin_unlock(&c3_cpu_status.lock); > - } > > /* Re-enable interrupts */ > local_irq_enable();_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Liu, Jinsong wrote on 2011-03-10:> Fix cpuidle bug > > Before invoking C3, bus master disable / flush cache should be the > last step; After resume from C3, bus master enable should be the first > step; > > Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>Acked-by: Wei Gang <gang.wei@intel.com> Jimmy _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Keir Fraser wrote on 2011-03-10:> Is this for 4.0 and 4.1 branches as well?I think checking it into unstable tree & 4.1 branch is enough. No specific bug found related to it yet. Jimmy> > -- Keir > On 10/03/2011 08:37, "Liu, Jinsong" <jinsong.liu@intel.com> wrote: > >> Fix cpuidle bug >> >> Before invoking C3, bus master disable / flush cache should be the >> last step; After resume from C3, bus master enable should be the >> first step; >> >> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Yes, it didn''t harm current platform, but logically it need update. Thank, Jinsong Wei, Gang wrote:> Keir Fraser wrote on 2011-03-10: >> Is this for 4.0 and 4.1 branches as well? > > I think checking it into unstable tree & 4.1 branch is enough. No > specific bug found related to it yet. > > Jimmy > >> >> -- Keir >> On 10/03/2011 08:37, "Liu, Jinsong" <jinsong.liu@intel.com> wrote: >> >>> Fix cpuidle bug >>> >>> Before invoking C3, bus master disable / flush cache should be the >>> last step; After resume from C3, bus master enable should be the >>> first step; >>> >>> Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com>_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel