Wei Wang2
2010-Dec-03 16:03 UTC
[Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation
This is the implementation. Thanks, We Signed-off-by: Wei Wang <wei.wang2@amd.com> -- Legal Information: Advanced Micro Devices GmbH Sitz: Dornach, Gemeinde Aschheim, Landkreis München Registergericht München, HRB Nr. 43632 Geschäftsführer: Alberto Bozzo, Andrew Bowd _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Kay, Allen M
2010-Dec-07 00:47 UTC
RE: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation
Hi Wei, My understanding is that both EPT/NPT already supports 2M and 1G page sizes. If this is true and if NPT supports the same page table format as AMD iommu, shouldn''t iommu 2M and 1G support just a matter of pointing iommu page table pointer to NPT page table of the same guest OS thus sharing the same page table between NPT and AMD iommu? This should save a lot code changes in iommu code. We just need to flush iommu page table in IOTLB at appropriate places. Allen -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Wei Wang2 Sent: Friday, December 03, 2010 8:04 AM To: xen-devel@lists.xensource.com Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation This is the implementation. Thanks, We Signed-off-by: Wei Wang <wei.wang2@amd.com> -- Legal Information: Advanced Micro Devices GmbH Sitz: Dornach, Gemeinde Aschheim, Landkreis München Registergericht München, HRB Nr. 43632 Geschäftsführer: Alberto Bozzo, Andrew Bowd _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Wei Wang2
2010-Dec-07 11:20 UTC
Re: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation
Hi Allen, Actually, each amd iommu pde entry uses bit 9-11 to encode next page table level, but these bits are also used as AVL bits by p2m table to encode different page types...So, it might not be quite easy to share NPT table with amd iommu unless we change p2m table encoding for this first. Thanks, Wei On Tuesday 07 December 2010 01:47:22 Kay, Allen M wrote:> Hi Wei, > > My understanding is that both EPT/NPT already supports 2M and 1G page > sizes. If this is true and if NPT supports the same page table format as > AMD iommu, shouldn''t iommu 2M and 1G support just a matter of pointing > iommu page table pointer to NPT page table of the same guest OS thus > sharing the same page table between NPT and AMD iommu? > > This should save a lot code changes in iommu code. We just need to flush > iommu page table in IOTLB at appropriate places. > > Allen > > -----Original Message----- > From: xen-devel-bounces@lists.xensource.com > [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Wei Wang2 Sent: > Friday, December 03, 2010 8:04 AM > To: xen-devel@lists.xensource.com > Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - > implementation > > This is the implementation. > > Thanks, > We > Signed-off-by: Wei Wang <wei.wang2@amd.com> > -- > Legal Information: > Advanced Micro Devices GmbH > Sitz: Dornach, Gemeinde Aschheim, > Landkreis München Registergericht München, HRB Nr. 43632 > Geschäftsführer: > Alberto Bozzo, Andrew Bowd_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Keir Fraser
2010-Dec-07 18:00 UTC
Re: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation
Cc''ing Tim -- he could advise how plausible it is to find other available bits to move the p2m types to. Also I''m not sure whether the p2m tables ever get used as host pagetables these days (e.g., when guest has CR0.PG=0). That could affect how difficult it is to mess with the p2m format. If it''s possible, though, it''s probably worth pursuing. Sharing the tables uses less memory, and could be less complicated code too. -- Keir On 07/12/2010 11:20, "Wei Wang2" <wei.wang2@amd.com> wrote:> Hi Allen, > Actually, each amd iommu pde entry uses bit 9-11 to encode next page table > level, but these bits are also used as AVL bits by p2m table to encode > different page types...So, it might not be quite easy to share NPT table with > amd iommu unless we change p2m table encoding for this first. > Thanks, > Wei > > On Tuesday 07 December 2010 01:47:22 Kay, Allen M wrote: >> Hi Wei, >> >> My understanding is that both EPT/NPT already supports 2M and 1G page >> sizes. If this is true and if NPT supports the same page table format as >> AMD iommu, shouldn''t iommu 2M and 1G support just a matter of pointing >> iommu page table pointer to NPT page table of the same guest OS thus >> sharing the same page table between NPT and AMD iommu? >> >> This should save a lot code changes in iommu code. We just need to flush >> iommu page table in IOTLB at appropriate places. >> >> Allen >> >> -----Original Message----- >> From: xen-devel-bounces@lists.xensource.com >> [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Wei Wang2 Sent: >> Friday, December 03, 2010 8:04 AM >> To: xen-devel@lists.xensource.com >> Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - >> implementation >> >> This is the implementation. >> >> Thanks, >> We >> Signed-off-by: Wei Wang <wei.wang2@amd.com> >> -- >> Legal Information: >> Advanced Micro Devices GmbH >> Sitz: Dornach, Gemeinde Aschheim, >> Landkreis München Registergericht München, HRB Nr. 43632 >> Geschäftsführer: >> Alberto Bozzo, Andrew Bowd > > > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Kay, Allen M
2010-Dec-07 18:21 UTC
RE: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation
FYI. We are currently testing a patch that sharing EPT and VT-d page tables on newer systems where both EPT and VT-d has the same page table format. There is very little change in VT-d specific code. We just need to do IOTLB flushes in appropriate places to support this. -----Original Message----- From: Keir Fraser [mailto:keir.xen@gmail.com] On Behalf Of Keir Fraser Sent: Tuesday, December 07, 2010 10:01 AM To: Wei Wang2; Kay, Allen M Cc: xen-devel@lists.xensource.com; Tim Deegan Subject: Re: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation Cc''ing Tim -- he could advise how plausible it is to find other available bits to move the p2m types to. Also I''m not sure whether the p2m tables ever get used as host pagetables these days (e.g., when guest has CR0.PG=0). That could affect how difficult it is to mess with the p2m format. If it''s possible, though, it''s probably worth pursuing. Sharing the tables uses less memory, and could be less complicated code too. -- Keir On 07/12/2010 11:20, "Wei Wang2" <wei.wang2@amd.com> wrote:> Hi Allen, > Actually, each amd iommu pde entry uses bit 9-11 to encode next page table > level, but these bits are also used as AVL bits by p2m table to encode > different page types...So, it might not be quite easy to share NPT table with > amd iommu unless we change p2m table encoding for this first. > Thanks, > Wei > > On Tuesday 07 December 2010 01:47:22 Kay, Allen M wrote: >> Hi Wei, >> >> My understanding is that both EPT/NPT already supports 2M and 1G page >> sizes. If this is true and if NPT supports the same page table format as >> AMD iommu, shouldn''t iommu 2M and 1G support just a matter of pointing >> iommu page table pointer to NPT page table of the same guest OS thus >> sharing the same page table between NPT and AMD iommu? >> >> This should save a lot code changes in iommu code. We just need to flush >> iommu page table in IOTLB at appropriate places. >> >> Allen >> >> -----Original Message----- >> From: xen-devel-bounces@lists.xensource.com >> [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Wei Wang2 Sent: >> Friday, December 03, 2010 8:04 AM >> To: xen-devel@lists.xensource.com >> Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - >> implementation >> >> This is the implementation. >> >> Thanks, >> We >> Signed-off-by: Wei Wang <wei.wang2@amd.com> >> -- >> Legal Information: >> Advanced Micro Devices GmbH >> Sitz: Dornach, Gemeinde Aschheim, >> Landkreis München Registergericht München, HRB Nr. 43632 >> Geschäftsführer: >> Alberto Bozzo, Andrew Bowd > > > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Tim Deegan
2010-Dec-08 10:03 UTC
Re: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation
Hi, At 18:00 +0000 on 07 Dec (1291744845), Keir Fraser wrote:> Cc''ing Tim -- he could advise how plausible it is to find other available > bits to move the p2m types to.PAE Xen we need to use bits 9-11 because there are no other bits available. On 64-bit we could just shift all the type bits up by three; I think there''s plenty of space above bit 52 for all the types we need. Even on PAE we really only need to store a p2m type in leaf nodes (l1 entries and superpage entries) so bits 9-11 are free on internal nodes. I don''t understand why the iommu tables have a level stored in every entry, though - is that a hardware requirement?> Also I''m not sure whether the p2m tables ever > get used as host pagetables these days (e.g., when guest has CR0.PG=0). That > could affect how difficult it is to mess with the p2m format.They never get used for PG=0 any more, we have a page in the firmware with a 1-1 4GB mapping instead. But they do get used as pagetables in order to use a linear mapping to read the p2m quickly.> If it''s possible, though, it''s probably worth pursuing. Sharing the tables > uses less memory, and could be less complicated code too.Yep, sounds like a great idea. Cheers, Tim.> On 07/12/2010 11:20, "Wei Wang2" <wei.wang2@amd.com> wrote: > > > Hi Allen, > > Actually, each amd iommu pde entry uses bit 9-11 to encode next page table > > level, but these bits are also used as AVL bits by p2m table to encode > > different page types...So, it might not be quite easy to share NPT table with > > amd iommu unless we change p2m table encoding for this first. > > Thanks, > > Wei > > > > On Tuesday 07 December 2010 01:47:22 Kay, Allen M wrote: > >> Hi Wei, > >> > >> My understanding is that both EPT/NPT already supports 2M and 1G page > >> sizes. If this is true and if NPT supports the same page table format as > >> AMD iommu, shouldn''t iommu 2M and 1G support just a matter of pointing > >> iommu page table pointer to NPT page table of the same guest OS thus > >> sharing the same page table between NPT and AMD iommu? > >> > >> This should save a lot code changes in iommu code. We just need to flush > >> iommu page table in IOTLB at appropriate places. > >> > >> Allen > >> > >> -----Original Message----- > >> From: xen-devel-bounces@lists.xensource.com > >> [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Wei Wang2 Sent: > >> Friday, December 03, 2010 8:04 AM > >> To: xen-devel@lists.xensource.com > >> Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - > >> implementation > >> > >> This is the implementation. > >> > >> Thanks, > >> We > >> Signed-off-by: Wei Wang <wei.wang2@amd.com> > >> -- > >> Legal Information: > >> Advanced Micro Devices GmbH > >> Sitz: Dornach, Gemeinde Aschheim, > >> Landkreis München Registergericht München, HRB Nr. 43632 > >> Geschäftsführer: > >> Alberto Bozzo, Andrew Bowd > > > > > > > > > > _______________________________________________ > > Xen-devel mailing list > > Xen-devel@lists.xensource.com > > http://lists.xensource.com/xen-devel > >-- Tim Deegan <Tim.Deegan@citrix.com> Principal Software Engineer, Xen Platform Team Citrix Systems UK Ltd. (Company #02937203, SL9 0BG) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Wei Wang2
2010-Dec-08 13:02 UTC
Re: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation
On Wednesday 08 December 2010 11:03:18 Tim Deegan wrote:> Hi, > > At 18:00 +0000 on 07 Dec (1291744845), Keir Fraser wrote: > > Cc''ing Tim -- he could advise how plausible it is to find other available > > bits to move the p2m types to. > > PAE Xen we need to use bits 9-11 because there are no other bits > available. On 64-bit we could just shift all the type bits up by three; > I think there''s plenty of space above bit 52 for all the types we need. > > Even on PAE we really only need to store a p2m type in leaf nodes (l1 > entries and superpage entries) so bits 9-11 are free on internal nodes. > I don''t understand why the iommu tables have a level stored in every > entry, though - is that a hardware requirement?Hi Tim, AMD IOMMU supports "skip level" feature, which allows hardware to skip page table walks if io address contains long string of 0 bits. To do this, iommu page table encodes the level of lower page table directly in bit 9- 11 of every pde entry. Therefore, to share p2m table with iommu, either p2m code or iommu code has to maintain bit 9- bit 11 in p2m entries as "next level" field. Also even in leaf entries, amd iommu hardware requires the content of "next level" field to be ''0'' or ''7''. So, in order to be more compatible with iommu, we should at least use ''0'' or ''7'' in bit 9- bit 11 to represent p2m type for normal guest ram in the case of PAE. Thanks, Wei> > > Also I''m not sure whether the p2m tables ever > > get used as host pagetables these days (e.g., when guest has CR0.PG=0). > > That could affect how difficult it is to mess with the p2m format. > > They never get used for PG=0 any more, we have a page in the firmware > with a 1-1 4GB mapping instead. But they do get used as pagetables in > order to use a linear mapping to read the p2m quickly. > > > If it''s possible, though, it''s probably worth pursuing. Sharing the > > tables uses less memory, and could be less complicated code too. > > Yep, sounds like a great idea. > > Cheers, > > Tim. > > > On 07/12/2010 11:20, "Wei Wang2" <wei.wang2@amd.com> wrote: > > > Hi Allen, > > > Actually, each amd iommu pde entry uses bit 9-11 to encode next page > > > table level, but these bits are also used as AVL bits by p2m table to > > > encode different page types...So, it might not be quite easy to share > > > NPT table with amd iommu unless we change p2m table encoding for this > > > first. > > > Thanks, > > > Wei > > > > > > On Tuesday 07 December 2010 01:47:22 Kay, Allen M wrote: > > >> Hi Wei, > > >> > > >> My understanding is that both EPT/NPT already supports 2M and 1G page > > >> sizes. If this is true and if NPT supports the same page table format > > >> as AMD iommu, shouldn''t iommu 2M and 1G support just a matter of > > >> pointing iommu page table pointer to NPT page table of the same guest > > >> OS thus sharing the same page table between NPT and AMD iommu? > > >> > > >> This should save a lot code changes in iommu code. We just need to > > >> flush iommu page table in IOTLB at appropriate places. > > >> > > >> Allen > > >> > > >> -----Original Message----- > > >> From: xen-devel-bounces@lists.xensource.com > > >> [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Wei Wang2 > > >> Sent: Friday, December 03, 2010 8:04 AM > > >> To: xen-devel@lists.xensource.com > > >> Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - > > >> implementation > > >> > > >> This is the implementation. > > >> > > >> Thanks, > > >> We > > >> Signed-off-by: Wei Wang <wei.wang2@amd.com> > > >> -- > > >> Legal Information: > > >> Advanced Micro Devices GmbH > > >> Sitz: Dornach, Gemeinde Aschheim, > > >> Landkreis München Registergericht München, HRB Nr. 43632 > > >> Geschäftsführer: > > >> Alberto Bozzo, Andrew Bowd > > > > > > _______________________________________________ > > > Xen-devel mailing list > > > Xen-devel@lists.xensource.com > > > http://lists.xensource.com/xen-devel_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Tim Deegan
2010-Dec-08 13:11 UTC
Re: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - implementation
At 13:02 +0000 on 08 Dec (1291813359), Wei Wang2 wrote:> AMD IOMMU supports "skip level" feature, which allows hardware to skip page > table walks if io address contains long string of 0 bits. To do this, iommu > page table encodes the level of lower page table directly in bit 9- 11 of > every pde entry. Therefore, to share p2m table with iommu, either p2m code or > iommu code has to maintain bit 9- bit 11 in p2m entries as "next level" > field.Oh, nice! Thanks for clarifying.> Also even in leaf entries, amd iommu hardware requires the content of "next > level" field to be ''0'' or ''7''. So, in order to be more compatible with iommu, > we should at least use ''0'' or ''7'' in bit 9- bit 11 to represent p2m type for > normal guest ram in the case of PAE.That''s not going to be enough; there are more than two types of memory that are marked as ''present'' in the p2m. I think that we just can''t have IOMMU and p2m sharing a pagetable on PAE builds. I don''t think that having IOMMU support be 64-bit only would be too terrible, though. A number of other features are 64-bit only, and the 64-bit hypervisor is generally better anyway. Are there going to be many machines with IOMMUs that don''t have 64-bit processors? Cheers, Tim.> > > Also I''m not sure whether the p2m tables ever > > > get used as host pagetables these days (e.g., when guest has CR0.PG=0). > > > That could affect how difficult it is to mess with the p2m format. > > > > They never get used for PG=0 any more, we have a page in the firmware > > with a 1-1 4GB mapping instead. But they do get used as pagetables in > > order to use a linear mapping to read the p2m quickly. > > > > > If it''s possible, though, it''s probably worth pursuing. Sharing the > > > tables uses less memory, and could be less complicated code too. > > > > Yep, sounds like a great idea. > > > > Cheers, > > > > Tim. > > > > > On 07/12/2010 11:20, "Wei Wang2" <wei.wang2@amd.com> wrote: > > > > Hi Allen, > > > > Actually, each amd iommu pde entry uses bit 9-11 to encode next page > > > > table level, but these bits are also used as AVL bits by p2m table to > > > > encode different page types...So, it might not be quite easy to share > > > > NPT table with amd iommu unless we change p2m table encoding for this > > > > first. > > > > Thanks, > > > > Wei > > > > > > > > On Tuesday 07 December 2010 01:47:22 Kay, Allen M wrote: > > > >> Hi Wei, > > > >> > > > >> My understanding is that both EPT/NPT already supports 2M and 1G page > > > >> sizes. If this is true and if NPT supports the same page table format > > > >> as AMD iommu, shouldn''t iommu 2M and 1G support just a matter of > > > >> pointing iommu page table pointer to NPT page table of the same guest > > > >> OS thus sharing the same page table between NPT and AMD iommu? > > > >> > > > >> This should save a lot code changes in iommu code. We just need to > > > >> flush iommu page table in IOTLB at appropriate places. > > > >> > > > >> Allen > > > >> > > > >> -----Original Message----- > > > >> From: xen-devel-bounces@lists.xensource.com > > > >> [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Wei Wang2 > > > >> Sent: Friday, December 03, 2010 8:04 AM > > > >> To: xen-devel@lists.xensource.com > > > >> Subject: [Xen-devel] [PATCH 4/4] amd iommu: Large io page support - > > > >> implementation > > > >> > > > >> This is the implementation. > > > >> > > > >> Thanks, > > > >> We > > > >> Signed-off-by: Wei Wang <wei.wang2@amd.com> > > > >> -- > > > >> Legal Information: > > > >> Advanced Micro Devices GmbH > > > >> Sitz: Dornach, Gemeinde Aschheim, > > > >> Landkreis München Registergericht München, HRB Nr. 43632 > > > >> Geschäftsführer: > > > >> Alberto Bozzo, Andrew Bowd > > > > > > > > _______________________________________________ > > > > Xen-devel mailing list > > > > Xen-devel@lists.xensource.com > > > > http://lists.xensource.com/xen-devel > > >-- Tim Deegan <Tim.Deegan@citrix.com> Principal Software Engineer, Xen Platform Team Citrix Systems UK Ltd. (Company #02937203, SL9 0BG) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Kay, Allen M
2010-Dec-08 18:38 UTC
[Xen-devel] [RFC][PATCH][VTD] EPT/VT-d page table sharing
Attached is EPT/VT-d page table sharing patch I mentioned earlier. Basic idea is to leverage 2MB and 1GB page size support in EPT by having VT-d using the same page tables as EPT. When EPT page table changes, flush VT-d IOTLB cache. We are still further testing this patch but would appreciate feedbacks. Signed-off-by: Weidong Han <weidong.han@intel.com> Signed-off-by: Allen Kay <allen.m.kay@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Tim Deegan
2010-Dec-09 10:12 UTC
[Xen-devel] Re: [RFC][PATCH][VTD] EPT/VT-d page table sharing
At 18:38 +0000 on 08 Dec (1291833518), Kay, Allen M wrote:> Attached is EPT/VT-d page table sharing patch I mentioned earlier. Basic idea is to leverage 2MB and 1GB page size support in EPT by having VT-d using the same page tables as EPT. When EPT page table changes, flush VT-d IOTLB cache. > > We are still further testing this patch but would appreciate feedbacks.Looks good! Two minor nits: - the path through iommu_set_pgd where the feature gets turned on is a bit confusing. It would be cleaner to have the global flag enabled as part of the general machine init. - while you''re moving the p2m bits into avail2, could you rename the avail2 field to p2mt or similar? It would make the rest of the code clearer. Cheers, Tim.> Signed-off-by: Weidong Han <weidong.han@intel.com> > Signed-off-by: Allen Kay <allen.m.kay@intel.com>-- Tim Deegan <Tim.Deegan@citrix.com> Principal Software Engineer, Xen Platform Team Citrix Systems UK Ltd. (Company #02937203, SL9 0BG) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Kay, Allen M
2010-Dec-11 02:01 UTC
[Xen-devel] RE: [RFC][PATCH][VTD] EPT/VT-d page table sharing
Hi Tim, Thanks for your feedback. In attached updated patch, I have: 1) moved setting of iommu_hap_pt_share flag to init_vtd_hw(). This function initialized other vt-d specific features. Let me know if you know of a better place. 2) rename avail2 field to sa_p2mt. Let me know if you have any additional comments. Allen -----Original Message----- From: Tim Deegan [mailto:Tim.Deegan@citrix.com] Sent: Thursday, December 09, 2010 2:13 AM To: Kay, Allen M Cc: Wei Wang2; Keir Fraser; Han, Weidong; xen-devel@lists.xensource.com Subject: Re: [RFC][PATCH][VTD] EPT/VT-d page table sharing At 18:38 +0000 on 08 Dec (1291833518), Kay, Allen M wrote:> Attached is EPT/VT-d page table sharing patch I mentioned earlier. Basic idea is to leverage 2MB and 1GB page size support in EPT by having VT-d using the same page tables as EPT. When EPT page table changes, flush VT-d IOTLB cache. > > We are still further testing this patch but would appreciate feedbacks.Looks good! Two minor nits: - the path through iommu_set_pgd where the feature gets turned on is a bit confusing. It would be cleaner to have the global flag enabled as part of the general machine init. - while you''re moving the p2m bits into avail2, could you rename the avail2 field to p2mt or similar? It would make the rest of the code clearer. Cheers, Tim.> Signed-off-by: Weidong Han <weidong.han@intel.com> > Signed-off-by: Allen Kay <allen.m.kay@intel.com>-- Tim Deegan <Tim.Deegan@citrix.com> Principal Software Engineer, Xen Platform Team Citrix Systems UK Ltd. (Company #02937203, SL9 0BG) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Ian Campbell
2010-Dec-21 17:08 UTC
Re: [Xen-devel] RE: [RFC][PATCH][VTD] EPT/VT-d page table sharing
On Sat, 2010-12-11 at 02:01 +0000, Kay, Allen M wrote:> Hi Tim, > > Thanks for your feedback. In attached updated patch, I have: > > 1) moved setting of iommu_hap_pt_share flag to init_vtd_hw(). This function initialized other vt-d specific features. Let me know if you know of a better place. > 2) rename avail2 field to sa_p2mt. > > Let me know if you have any additional comments.Hi Allen, This change appears to be responsible for the recent failures to boot xen-unstable on Intel hardware, which is stopping the regression test runs. The symptom is a hang just before the hypervisor scrubs the pages. e.g. http://www.chiark.greenend.org.uk/~xensrcts/logs/3470/test-amd64-i386-rhel6hvm-intel/ was successful while http://www.chiark.greenend.org.uk/~xensrcts/logs/3863/test-amd64-i386-rhel6hvm-intel/ was not. Booting with "sharept=0" resolves the boot failure. It''s been quite a long time (~2 weeks) since we last had a test case (not all down to this issue) so unless you have a quick fix I propose the temporary workaround below. Thanks, Ian. EPT/VT-d: disable page sharing by default. Currently sharing these page tables causes a hang on boot on some hardware. Disable by default until this is resolved. Signed-off-by: Ian Campbell <ian.campbell@citrix.com> diff -r ff1b80ccecd9 xen/drivers/passthrough/vtd/iommu.c --- a/xen/drivers/passthrough/vtd/iommu.c Fri Dec 17 16:12:37 2010 +0000 +++ b/xen/drivers/passthrough/vtd/iommu.c Tue Dec 21 16:24:34 2010 +0000 @@ -45,7 +45,7 @@ #define nr_ioapics iosapic_get_nr_iosapics() #endif -static int sharept = 1; +static int sharept = 0; boolean_param("sharept", sharept); int nr_iommus; _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel