Yuji Shimada
2009-Feb-17 09:20 UTC
[Xen-devel] [PATCH] ioemu: Cleanup the code of PCI passthrough.
This patch cleanups the code of PCI passthrough.
- Use LIST_FOREACH(). Don''t use lh_first, le_next directly.
- Use pci_{read, write}_block instead of "switch(len) case [124]
pci_{read, write}_{byte, word, long}();".
- Eliminate duplicate codes using PT_MEARGE_VALUE macro.
- Define PCI_ERR_* macro in pass-through.h if libpci is old.
- Remove the unreasonable loop from pt_aer_reg_{save,restore}.
- Enable pt_aer_reg_{save,restore}, even if libpci is old.
- Fix ro_mask and remove unnecessary pt_xxx_reg_write functions.
- Add "Error:" or "Warning:" to messages.
- Remove verbose messages.
Thanks,
--
Yuji Shimada.
Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.j>
diff --git a/hw/pass-through.c b/hw/pass-through.c
index c2a6ec1..1de0162 100644
--- a/hw/pass-through.c
+++ b/hw/pass-through.c
@@ -126,18 +126,6 @@ static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev,
static int pt_pmcsr_reg_write(struct pt_dev *ptdev,
struct pt_reg_tbl *cfg_entry,
uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
-static int pt_devctrl_reg_write(struct pt_dev *ptdev,
- struct pt_reg_tbl *cfg_entry,
- uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
-static int pt_linkctrl_reg_write(struct pt_dev *ptdev,
- struct pt_reg_tbl *cfg_entry,
- uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
-static int pt_devctrl2_reg_write(struct pt_dev *ptdev,
- struct pt_reg_tbl *cfg_entry,
- uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
-static int pt_linkctrl2_reg_write(struct pt_dev *ptdev,
- struct pt_reg_tbl *cfg_entry,
- uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
static int pt_msgctrl_reg_write(struct pt_dev *ptdev,
struct pt_reg_tbl *cfg_entry,
uint16_t *value, uint16_t dev_value, uint16_t valid_mask);
@@ -413,7 +401,7 @@ static struct pt_reg_info_tbl pt_emu_reg_pm_tbl[] = {
.offset = PCI_PM_CTRL,
.size = 2,
.init_val = 0x0008,
- .ro_mask = 0x60FC,
+ .ro_mask = 0xE1FC,
.emu_mask = 0x8100,
.init = pt_pmcsr_reg_init,
.u.w.read = pt_word_reg_read,
@@ -494,11 +482,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = {
.offset = PCI_EXP_DEVCTL,
.size = 2,
.init_val = 0x2810,
- .ro_mask = 0x0000,
+ .ro_mask = 0x8400,
.emu_mask = 0xFFFF,
.init = pt_common_reg_init,
.u.w.read = pt_word_reg_read,
- .u.w.write = pt_devctrl_reg_write,
+ .u.w.write = pt_word_reg_write,
.u.w.restore = pt_word_reg_restore,
},
/* Link Control reg */
@@ -506,11 +494,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = {
.offset = PCI_EXP_LNKCTL,
.size = 2,
.init_val = 0x0000,
- .ro_mask = 0x0000,
+ .ro_mask = 0xFC34,
.emu_mask = 0xFFFF,
.init = pt_linkctrl_reg_init,
.u.w.read = pt_word_reg_read,
- .u.w.write = pt_linkctrl_reg_write,
+ .u.w.write = pt_word_reg_write,
.u.w.restore = pt_word_reg_restore,
},
/* Device Control 2 reg */
@@ -518,11 +506,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = {
.offset = 0x28,
.size = 2,
.init_val = 0x0000,
- .ro_mask = 0x0000,
+ .ro_mask = 0xFFE0,
.emu_mask = 0xFFFF,
.init = pt_devctrl2_reg_init,
.u.w.read = pt_word_reg_read,
- .u.w.write = pt_devctrl2_reg_write,
+ .u.w.write = pt_word_reg_write,
.u.w.restore = pt_word_reg_restore,
},
/* Link Control 2 reg */
@@ -530,11 +518,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = {
.offset = 0x30,
.size = 2,
.init_val = 0x0000,
- .ro_mask = 0x0000,
+ .ro_mask = 0xE040,
.emu_mask = 0xFFFF,
.init = pt_linkctrl2_reg_init,
.u.w.read = pt_word_reg_read,
- .u.w.write = pt_linkctrl2_reg_write,
+ .u.w.write = pt_word_reg_write,
.u.w.restore = pt_word_reg_restore,
},
{
@@ -1051,8 +1039,7 @@ struct pt_reg_grp_tbl* pt_find_reg_grp(
struct pt_reg_grp_tbl* reg_grp_entry = NULL;
/* find register group entry */
- for (reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first; reg_grp_entry;
- reg_grp_entry = reg_grp_entry->entries.le_next)
+ LIST_FOREACH(reg_grp_entry, &ptdev->reg_grp_tbl_head, entries)
{
/* check address */
if ((reg_grp_entry->base_offset <= address) &&
@@ -1075,8 +1062,7 @@ struct pt_reg_tbl* pt_find_reg(
uint32_t real_offset = 0;
/* find register entry */
- for (reg_entry = reg_grp->reg_tbl_head.lh_first; reg_entry;
- reg_entry = reg_entry->entries.le_next)
+ LIST_FOREACH(reg_entry, ®_grp->reg_tbl_head, entries)
{
reg = reg_entry->reg;
real_offset = (reg_grp->base_offset + reg->offset);
@@ -1140,7 +1126,7 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t
address, uint32_t val,
/* check offset range */
if (address >= 0xFF)
{
- PT_LOG("Failed to write register with offset exceeding FFh. "
+ PT_LOG("Error: Failed to write register with offset exceeding FFh.
"
"[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
(d->devfn & 0x7),
address, len);
@@ -1150,7 +1136,7 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t
address, uint32_t val,
/* check write size */
if ((len != 1) && (len != 2) && (len != 4))
{
- PT_LOG("Failed to write register with invalid access length.
"
+ PT_LOG("Error: Failed to write register with invalid access
length. "
"[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
(d->devfn & 0x7),
address, len);
@@ -1160,8 +1146,8 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t
address, uint32_t val,
/* check offset alignment */
if (address & (len-1))
{
- PT_LOG("Failed to write register with invalid access size
alignment. "
- "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
+ PT_LOG("Error: Failed to write register with invalid access size
"
+ "alignment. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
(d->devfn & 0x7),
address, len);
goto exit;
@@ -1172,8 +1158,8 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t
address, uint32_t val,
if ((index >= 0) && (val > 0 && val < PT_BAR_ALLF)
&&
(assigned_device->bases[index].bar_flag == PT_BAR_FLAG_UNUSED))
{
- PT_LOG("Guest attempt to set address to unused Base Address
Register. "
- "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
+ PT_LOG("Warning: Guest attempt to set address to unused Base
Address "
+ "Register. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
(d->devfn & 0x7), address, len);
}
@@ -1194,7 +1180,7 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t
address, uint32_t val,
if (reg_grp->grp_type == GRP_TYPE_HARDWIRED)
{
/* ignore silently */
- PT_LOG("Access to 0 Hardwired register. "
+ PT_LOG("Warning: Access to 0 Hardwired register. "
"[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
(d->devfn & 0x7), address, len);
@@ -1203,28 +1189,14 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t
address, uint32_t val,
}
/* read I/O device register value */
- switch (len) {
- case 1:
- read_val = pci_read_byte(pci_dev, address);
- break;
- case 2:
- read_val = pci_read_word(pci_dev, address);
- break;
- case 4:
- read_val = pci_read_long(pci_dev, address);
- break;
- }
+ ret = pci_read_block(pci_dev, address, (uint8_t *)&read_val, len);
- /* check libpci result */
- valid_mask = (0xFFFFFFFF >> ((4 - len) << 3));
- if ((read_val & valid_mask) == valid_mask)
+ if (!ret)
{
- PT_LOG("Warning: Return ALL F from libpci read. "
- "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
- pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
(d->devfn & 0x7),
- address, len);
+ PT_LOG("Error: pci_read_block failed. return value[%d].\n",
ret);
+ memset((uint8_t *)&read_val, 0xff, len);
}
-
+
/* pass directly to libpci for passthrough type register group */
if (reg_grp_entry == NULL)
goto out;
@@ -1303,17 +1277,10 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t
address, uint32_t val,
val >>= ((address & 3) << 3);
out:
- switch (len){
- case 1:
- pci_write_byte(pci_dev, address, val);
- break;
- case 2:
- pci_write_word(pci_dev, address, val);
- break;
- case 4:
- pci_write_long(pci_dev, address, val);
- break;
- }
+ ret = pci_write_block(pci_dev, address, (uint8_t *)&val, len);
+
+ if (!ret)
+ PT_LOG("Error: pci_write_block failed. return value[%d].\n",
ret);
if (pm_state->flags & PT_FLAG_TRANSITING)
/* set QEMUTimer */
@@ -1329,7 +1298,7 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t
address, int len)
struct pt_dev *assigned_device = (struct pt_dev *)d;
struct pci_dev *pci_dev = assigned_device->pci_dev;
struct pt_pm_info *pm_state = assigned_device->pm_state;
- uint32_t val = 0xFFFFFFFF;
+ uint32_t val = 0;
struct pt_reg_grp_tbl *reg_grp_entry = NULL;
struct pt_reg_grp_info_tbl *reg_grp = NULL;
struct pt_reg_tbl *reg_entry = NULL;
@@ -1344,7 +1313,7 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t
address, int len)
/* check offset range */
if (address >= 0xFF)
{
- PT_LOG("Failed to read register with offset exceeding FFh. "
+ PT_LOG("Error: Failed to read register with offset exceeding FFh.
"
"[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
(d->devfn & 0x7),
address, len);
@@ -1354,7 +1323,7 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t
address, int len)
/* check read size */
if ((len != 1) && (len != 2) && (len != 4))
{
- PT_LOG("Failed to read register with invalid access length. "
+ PT_LOG("Error: Failed to read register with invalid access length.
"
"[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
(d->devfn & 0x7),
address, len);
@@ -1364,8 +1333,8 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t
address, int len)
/* check offset alignment */
if (address & (len-1))
{
- PT_LOG("Failed to read register with invalid access size
alignment. "
- "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
+ PT_LOG("Error: Failed to read register with invalid access size
"
+ "alignment. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
(d->devfn & 0x7),
address, len);
goto exit;
@@ -1393,26 +1362,12 @@ static uint32_t pt_pci_read_config(PCIDevice *d,
uint32_t address, int len)
}
/* read I/O device register value */
- switch (len) {
- case 1:
- val = pci_read_byte(pci_dev, address);
- break;
- case 2:
- val = pci_read_word(pci_dev, address);
- break;
- case 4:
- val = pci_read_long(pci_dev, address);
- break;
- }
+ ret = pci_read_block(pci_dev, address, (uint8_t *)&val, len);
- /* check libpci result */
- valid_mask = (0xFFFFFFFF >> ((4 - len) << 3));
- if ((val & valid_mask) == valid_mask)
+ if (!ret)
{
- PT_LOG("Warning: Return ALL F from libpci read. "
- "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n",
- pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F),
(d->devfn & 0x7),
- address, len);
+ PT_LOG("Error: pci_read_block failed. return value[%d].\n",
ret);
+ memset((uint8_t *)&val, 0xff, len);
}
/* just return the I/O device register value for
@@ -1514,7 +1471,7 @@ static void pt_libpci_fixup(struct pci_dev *dev)
fp = fopen(path, "r");
if ( !fp )
{
- PT_LOG("Can''t open %s: %s\n", path,
strerror(errno));
+ PT_LOG("Error: Can''t open %s: %s\n", path,
strerror(errno));
return;
}
@@ -1522,7 +1479,7 @@ static void pt_libpci_fixup(struct pci_dev *dev)
{
if ( fscanf(fp, "%llx %llx %llx", &start, &end,
&flags) != 3 )
{
- PT_LOG("Syntax error in %s\n", path);
+ PT_LOG("Error: Syntax error in %s\n", path);
break;
}
@@ -1800,8 +1757,8 @@ static void pt_bar_mapping(struct pt_dev *ptdev, int
io_enable, int mem_enable)
/* check overlapped address */
ret = pt_chk_bar_overlap(dev->bus, dev->devfn, r_addr, r_size);
if (ret > 0)
-
PT_LOG("ptdev[%02x:%02x.%x][Region:%d][Address:%08xh][Size:%08xh] "
- "is overlapped.\n", pci_bus_num(dev->bus),
+ PT_LOG("Warning:
ptdev[%02x:%02x.%x][Region:%d][Address:%08xh]"
+ "[Size:%08xh] is overlapped.\n",
pci_bus_num(dev->bus),
(dev->devfn >> 3) & 0x1F, (dev->devfn &
0x7),
i, r_addr, r_size);
@@ -1841,68 +1798,51 @@ int check_power_state(struct pt_dev *ptdev)
return 0;
}
-/* save AER register */
-static void pt_aer_reg_save(struct pt_dev *ptdev)
+/* save AER one register */
+static void aer_save_one_register(struct pt_dev *ptdev, int offset)
{
PCIDevice *d = &ptdev->dev;
uint32_t aer_base = ptdev->pm_state->aer_base;
- int i = 0;
- /* Root Port and Root Complex Event Collector need size expansion */
- int aer_size = 0x2c;
-#ifdef PCI_ERR_UNCOR_MASK
- for (i=0; i < aer_size; i+=4)
- {
- switch (i) {
- /* after reset, following register values should be restored.
- * So, save them.
- */
- case PCI_ERR_UNCOR_MASK:
- case PCI_ERR_UNCOR_SEVER:
- case PCI_ERR_COR_MASK:
- case PCI_ERR_CAP:
- *(uint32_t*)(d->config + (aer_base + i))
- = pci_read_long(ptdev->pci_dev, (aer_base + i));
- break;
- default:
- break;
- }
- }
-#endif
+ *(uint32_t*)(d->config + (aer_base + offset))
+ = pci_read_long(ptdev->pci_dev, (aer_base + offset));
}
-/* restore AER register */
-static void pt_aer_reg_restore(struct pt_dev *ptdev)
+/* save AER registers */
+static void pt_aer_reg_save(struct pt_dev *ptdev)
+{
+ /* after reset, following register values should be restored.
+ * So, save them.
+ */
+ aer_save_one_register(ptdev, PCI_ERR_UNCOR_MASK);
+ aer_save_one_register(ptdev, PCI_ERR_UNCOR_SEVER);
+ aer_save_one_register(ptdev, PCI_ERR_COR_MASK);
+ aer_save_one_register(ptdev, PCI_ERR_CAP);
+}
+
+/* restore AER one register */
+static void aer_restore_one_register(struct pt_dev *ptdev, int offset)
{
PCIDevice *d = &ptdev->dev;
uint32_t aer_base = ptdev->pm_state->aer_base;
- int i = 0;
uint32_t config = 0;
- /* Root Port and Root Complex Event Collector need size expansion */
- int aer_size = 0x2c;
-#ifdef PCI_ERR_UNCOR_MASK
- for (i=0; i < aer_size; i+=4)
- {
- switch (i) {
- /* the following registers should be reconfigured to correct values
- * after reset. restore them.
- */
- case PCI_ERR_UNCOR_MASK:
- case PCI_ERR_UNCOR_SEVER:
- case PCI_ERR_COR_MASK:
- case PCI_ERR_CAP:
- config = *(uint32_t*)(d->config + (aer_base + i));
- pci_write_long(ptdev->pci_dev, (aer_base + i), config);
- break;
- /* other registers should not be reconfigured after reset
- * if there is no reason
- */
- default:
- break;
- }
- }
-#endif
+ config = *(uint32_t*)(d->config + (aer_base + offset));
+ pci_write_long(ptdev->pci_dev, (aer_base + offset), config);
+}
+
+/* restore AER registers */
+static void pt_aer_reg_restore(struct pt_dev *ptdev)
+{
+ /* the following registers should be reconfigured to correct values
+ * after reset. restore them.
+ * other registers should not be reconfigured after reset
+ * if there is no reason
+ */
+ aer_restore_one_register(ptdev, PCI_ERR_UNCOR_MASK);
+ aer_restore_one_register(ptdev, PCI_ERR_UNCOR_SEVER);
+ aer_restore_one_register(ptdev, PCI_ERR_COR_MASK);
+ aer_restore_one_register(ptdev, PCI_ERR_CAP);
}
/* reset Interrupt and I/O resource */
@@ -2115,7 +2055,7 @@ static int pt_config_reg_init(struct pt_dev *ptdev,
reg_entry = qemu_mallocz(sizeof(struct pt_reg_tbl));
if (reg_entry == NULL)
{
- PT_LOG("Failed to allocate memory.\n");
+ PT_LOG("Error: Failed to allocate memory.\n");
err = -1;
goto out;
}
@@ -2171,7 +2111,7 @@ static int pt_config_init(struct pt_dev *ptdev)
reg_grp_entry = qemu_mallocz(sizeof(struct pt_reg_grp_tbl));
if (reg_grp_entry == NULL)
{
- PT_LOG("Failed to allocate memory.\n");
+ PT_LOG("Error: Failed to allocate memory.\n");
err = -1;
goto out;
}
@@ -2239,10 +2179,10 @@ static void pt_config_delete(struct pt_dev *ptdev)
}
/* free all register group entry */
- while ((reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first) != NULL)
+ while((reg_grp_entry = LIST_FIRST(&ptdev->reg_grp_tbl_head)) !=
NULL)
{
/* free all register entry */
- while ((reg_entry = reg_grp_entry->reg_tbl_head.lh_first) != NULL)
+ while((reg_entry = LIST_FIRST(®_grp_entry->reg_tbl_head)) !=
NULL)
{
LIST_REMOVE(reg_entry, entries);
qemu_free(reg_entry);
@@ -2624,7 +2564,7 @@ static uint8_t pt_msi_size_init(struct pt_dev *ptdev,
if ( !ptdev->msi )
{
/* exit I/O emulator */
- PT_LOG("error allocation pt_msi_info. I/O emulator exit.\n");
+ PT_LOG("Error: Allocating pt_msi_info failed. I/O emulator
exit.\n");
exit(1);
}
memset(ptdev->msi, 0, sizeof(struct pt_msi_info));
@@ -2754,8 +2694,7 @@ static int pt_byte_reg_read(struct pt_dev *ptdev,
/* emulate byte register */
valid_emu_mask = reg->emu_mask & valid_mask;
- *value = ((*value & ~valid_emu_mask) |
- (cfg_entry->data & valid_emu_mask));
+ *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
return 0;
}
@@ -2770,8 +2709,7 @@ static int pt_word_reg_read(struct pt_dev *ptdev,
/* emulate word register */
valid_emu_mask = reg->emu_mask & valid_mask;
- *value = ((*value & ~valid_emu_mask) |
- (cfg_entry->data & valid_emu_mask));
+ *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
return 0;
}
@@ -2786,8 +2724,7 @@ static int pt_long_reg_read(struct pt_dev *ptdev,
/* emulate long register */
valid_emu_mask = reg->emu_mask & valid_mask;
- *value = ((*value & ~valid_emu_mask) |
- (cfg_entry->data & valid_emu_mask));
+ *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
return 0;
}
@@ -2833,8 +2770,7 @@ static int pt_bar_reg_read(struct pt_dev *ptdev,
/* emulate BAR */
valid_emu_mask = bar_emu_mask & valid_mask;
- *value = ((*value & ~valid_emu_mask) |
- (cfg_entry->data & valid_emu_mask));
+ *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask);
return 0;
}
@@ -2850,13 +2786,11 @@ static int pt_byte_reg_write(struct pt_dev *ptdev,
/* modify emulate register */
writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* create value for writing to I/O device register */
throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) |
- (dev_value & ~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
return 0;
}
@@ -2872,13 +2806,11 @@ static int pt_word_reg_write(struct pt_dev *ptdev,
/* modify emulate register */
writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* create value for writing to I/O device register */
throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) |
- (dev_value & ~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
return 0;
}
@@ -2894,13 +2826,11 @@ static int pt_long_reg_write(struct pt_dev *ptdev,
/* modify emulate register */
writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* create value for writing to I/O device register */
throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) |
- (dev_value & ~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
return 0;
}
@@ -2917,12 +2847,11 @@ static int pt_cmd_reg_write(struct pt_dev *ptdev,
/* modify emulate register */
writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* create value for writing to I/O device register */
throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) | (dev_value &
~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
/* mapping BAR */
pt_bar_mapping(ptdev, wr_value & PCI_COMMAND_IO,
@@ -2988,8 +2917,7 @@ static int pt_bar_reg_write(struct pt_dev *ptdev,
/* modify emulate register */
writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* check whether we need to update the virtual region address or not */
switch (ptdev->bases[index].bar_flag)
@@ -3007,7 +2935,8 @@ static int pt_bar_reg_write(struct pt_dev *ptdev,
if ((last_addr >= 0x10000) &&
(cfg_entry->data != (PT_BAR_ALLF & ~bar_ro_mask)))
{
- PT_LOG("Guest attempt to set Base Address over the 64KB.
"
+ PT_LOG("Warning: Guest attempt to set Base Address "
+ "over the 64KB. "
"[%02x:%02x.%x][Offset:%02xh][Address:%08xh][Size:%08xh]\n",
pci_bus_num(d->bus),
((d->devfn >> 3) & 0x1F), (d->devfn &
0x7),
@@ -3023,7 +2952,7 @@ static int pt_bar_reg_write(struct pt_dev *ptdev,
{
if (cfg_entry->data != (PT_BAR_ALLF & ~bar_ro_mask))
{
- PT_LOG("Guest attempt to set high MMIO Base Address.
"
+ PT_LOG("Warning: Guest attempt to set high MMIO Base
Address. "
"Ignore mapping. "
"[%02x:%02x.%x][Offset:%02xh][High
Address:%08xh]\n",
pci_bus_num(d->bus),
@@ -3066,8 +2995,7 @@ static int pt_bar_reg_write(struct pt_dev *ptdev,
exit:
/* create value for writing to I/O device register */
throughable_mask = ~bar_emu_mask & valid_mask;
- *value = ((*value & throughable_mask) |
- (dev_value & ~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
return 0;
}
@@ -3099,16 +3027,14 @@ static int pt_exp_rom_bar_reg_write(struct pt_dev
*ptdev,
/* modify emulate register */
writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* update the corresponding virtual region address */
r->addr = cfg_entry->data;
/* create value for writing to I/O device register */
throughable_mask = ~bar_emu_mask & valid_mask;
- *value = ((*value & throughable_mask) |
- (dev_value & ~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
return 0;
}
@@ -3122,22 +3048,16 @@ static int pt_pmcsr_reg_write(struct pt_dev *ptdev,
PCIDevice *d = &ptdev->dev;
uint16_t writable_mask = 0;
uint16_t throughable_mask = 0;
- uint16_t pmcsr_mask = (PCI_PM_CTRL_PME_ENABLE |
- PCI_PM_CTRL_DATA_SEL_MASK |
- PCI_PM_CTRL_PME_STATUS);
struct pt_pm_info *pm_state = ptdev->pm_state;
uint16_t read_val = 0;
/* modify emulate register */
- writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask
& ~pmcsr_mask;
-
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* create value for writing to I/O device register */
throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) |
- (dev_value & ~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
/* set I/O device power state */
pm_state->cur_state = (dev_value & PCI_PM_CTRL_STATE_MASK);
@@ -3236,101 +3156,6 @@ static int pt_pmcsr_reg_write(struct pt_dev *ptdev,
return 0;
}
-/* write Device Control register */
-static int pt_devctrl_reg_write(struct pt_dev *ptdev,
- struct pt_reg_tbl *cfg_entry,
- uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
-{
- struct pt_reg_info_tbl *reg = cfg_entry->reg;
- uint16_t writable_mask = 0;
- uint16_t throughable_mask = 0;
- uint16_t devctrl_mask = (PCI_EXP_DEVCTL_AUX_PME | 0x8000);
-
- /* modify emulate register */
- writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask
& ~devctrl_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
-
- /* create value for writing to I/O device register */
- throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) |
- (dev_value & ~throughable_mask));
-
- return 0;
-}
-
-/* write Link Control register */
-static int pt_linkctrl_reg_write(struct pt_dev *ptdev,
- struct pt_reg_tbl *cfg_entry,
- uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
-{
- struct pt_reg_info_tbl *reg = cfg_entry->reg;
- uint16_t writable_mask = 0;
- uint16_t throughable_mask = 0;
- uint16_t linkctrl_mask = (0x04 | PCI_EXP_LNKCTL_DISABLE |
- PCI_EXP_LNKCTL_RETRAIN |
- 0x0400 | 0x0800 | 0xF000);
-
- /* modify emulate register */
- writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask
& ~linkctrl_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
-
- /* create value for writing to I/O device register */
- throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) |
- (dev_value & ~throughable_mask));
-
- return 0;
-}
-
-/* write Device Control2 register */
-static int pt_devctrl2_reg_write(struct pt_dev *ptdev,
- struct pt_reg_tbl *cfg_entry,
- uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
-{
- struct pt_reg_info_tbl *reg = cfg_entry->reg;
- uint16_t writable_mask = 0;
- uint16_t throughable_mask = 0;
- uint16_t devctrl2_mask = 0xFFE0;
-
- /* modify emulate register */
- writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask
& ~devctrl2_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
-
- /* create value for writing to I/O device register */
- throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) |
- (dev_value & ~throughable_mask));
-
- return 0;
-}
-
-/* write Link Control2 register */
-static int pt_linkctrl2_reg_write(struct pt_dev *ptdev,
- struct pt_reg_tbl *cfg_entry,
- uint16_t *value, uint16_t dev_value, uint16_t valid_mask)
-{
- struct pt_reg_info_tbl *reg = cfg_entry->reg;
- uint16_t writable_mask = 0;
- uint16_t throughable_mask = 0;
- uint16_t linkctrl2_mask = (0x0040 | 0xE000);
-
- /* modify emulate register */
- writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask
&
- ~linkctrl2_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
-
- /* create value for writing to I/O device register */
- throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) |
- (dev_value & ~throughable_mask));
-
- return 0;
-}
-
/* write Message Control register */
static int pt_msgctrl_reg_write(struct pt_dev *ptdev,
struct pt_reg_tbl *cfg_entry,
@@ -3346,22 +3171,19 @@ static int pt_msgctrl_reg_write(struct pt_dev *ptdev,
/* Currently no support for multi-vector */
if ((*value & PCI_MSI_FLAGS_QSIZE) != 0x0)
- PT_LOG("try to set more than 1 vector ctrl %x\n", *value);
+ PT_LOG("Warning: try to set more than 1 vector ctrl %x\n",
*value);
/* modify emulate register */
writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* update the msi_info too */
ptdev->msi->flags |= cfg_entry->data &
~(MSI_FLAG_UNINIT | PT_MSI_MAPPED | PCI_MSI_FLAGS_ENABLE);
- PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl,
cfg_entry->data);
-
/* create value for writing to I/O device register */
val = *value;
throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) | (dev_value &
~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
/* update MSI */
if (val & PCI_MSI_FLAGS_ENABLE)
@@ -3420,16 +3242,13 @@ static int pt_msgaddr32_reg_write(struct pt_dev *ptdev,
/* modify emulate register */
writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* update the msi_info too */
ptdev->msi->addr_lo = cfg_entry->data;
- PT_LOG("old_addr_lo:%08xh new_addr_lo:%08xh\n", old_addr,
cfg_entry->data);
-
/* create value for writing to I/O device register */
throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) | (dev_value &
~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
/* update MSI */
if (cfg_entry->data != old_addr)
@@ -3455,22 +3274,19 @@ static int pt_msgaddr64_reg_write(struct pt_dev *ptdev,
if (!(ptdev->msi->flags & PCI_MSI_FLAGS_64BIT))
{
/* exit I/O emulator */
- PT_LOG("why comes to Upper Address without 64 bit
support??\n");
+ PT_LOG("Error: why comes to Upper Address without 64 bit
support??\n");
return -1;
}
/* modify emulate register */
writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* update the msi_info too */
ptdev->msi->addr_hi = cfg_entry->data;
- PT_LOG("old_addr_hi:%08xh new_addr_hi:%08xh\n", old_addr,
cfg_entry->data);
-
/* create value for writing to I/O device register */
throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) | (dev_value &
~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
/* update MSI */
if (cfg_entry->data != old_addr)
@@ -3506,16 +3322,13 @@ static int pt_msgdata_reg_write(struct pt_dev *ptdev,
/* modify emulate register */
writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
/* update the msi_info too */
ptdev->msi->data = cfg_entry->data;
- PT_LOG("old_data:%04xh new_data:%04xh\n", old_data,
cfg_entry->data);
-
/* create value for writing to I/O device register */
throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) | (dev_value &
~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
/* update MSI */
if (cfg_entry->data != old_data)
@@ -3539,14 +3352,11 @@ static int pt_msixctrl_reg_write(struct pt_dev *ptdev,
/* modify emulate register */
writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask;
- cfg_entry->data = ((*value & writable_mask) |
- (cfg_entry->data & ~writable_mask));
+ cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data,
writable_mask);
- PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl,
cfg_entry->data);
-
/* create value for writing to I/O device register */
throughable_mask = ~reg->emu_mask & valid_mask;
- *value = ((*value & throughable_mask) | (dev_value &
~throughable_mask));
+ *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask);
/* update MSI-X */
if ((*value & PCI_MSIX_ENABLE) && !(*value &
PCI_MSIX_MASK))
@@ -3979,7 +3789,7 @@ int pt_init(PCIBus *e_bus, const char *direct_pci)
pci_access = pci_alloc();
if ( pci_access == NULL )
{
- PT_LOG("pci_access is NULL\n");
+ PT_LOG("Error: pci_access is NULL\n");
return -1;
}
pci_init(pci_access);
diff --git a/hw/pass-through.h b/hw/pass-through.h
index b44b9d7..2b2dbd2 100644
--- a/hw/pass-through.h
+++ b/hw/pass-through.h
@@ -86,6 +86,26 @@
#define PCI_EXP_TYPE_ROOT_EC 0xa
#endif
+#ifndef PCI_ERR_UNCOR_MASK
+/* Uncorrectable Error Mask */
+#define PCI_ERR_UNCOR_MASK 8
+#endif
+
+#ifndef PCI_ERR_UNCOR_SEVER
+/* Uncorrectable Error Severity */
+#define PCI_ERR_UNCOR_SEVER 12
+#endif
+
+#ifndef PCI_ERR_COR_MASK
+/* Correctable Error Mask */
+#define PCI_ERR_COR_MASK 20
+#endif
+
+#ifndef PCI_ERR_CAP
+/* Advanced Error Capabilities */
+#define PCI_ERR_CAP 24
+#endif
+
#ifndef PCI_EXT_CAP_ID
/* Extended Capabilities (PCI-X 2.0 and PCI Express) */
#define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
diff --git a/hw/pt-msi.c b/hw/pt-msi.c
index bdd1b38..6b0aaa1 100644
--- a/hw/pt-msi.c
+++ b/hw/pt-msi.c
@@ -68,7 +68,7 @@ int pt_msi_setup(struct pt_dev *dev)
if ( !(dev->msi->flags & MSI_FLAG_UNINIT) )
{
- PT_LOG("setup physical after initialized?? \n");
+ PT_LOG("Error: setup physical after initialized?? \n");
return -1;
}
@@ -76,13 +76,13 @@ int pt_msi_setup(struct pt_dev *dev)
dev->pci_dev->dev << 3 |
dev->pci_dev->func,
dev->pci_dev->bus, 0, 0) )
{
- PT_LOG("error map msi\n");
+ PT_LOG("Error: Mapping of MSI failed.\n");
return -1;
}
if ( pirq < 0 )
{
- PT_LOG("invalid pirq number\n");
+ PT_LOG("Error: Invalid pirq number\n");
return -1;
}
@@ -125,7 +125,7 @@ int pt_msi_update(struct pt_dev *d)
addr = (uint64_t)d->msi->addr_hi << 32 | d->msi->addr_lo;
gflags = __get_msi_gflags(d->msi->data, addr);
- PT_LOG("now update msi with pirq %x gvec %x\n",
d->msi->pirq, gvec);
+ PT_LOG("Update msi with pirq %x gvec %x\n", d->msi->pirq,
gvec);
return xc_domain_update_msi_irq(xc_handle, domid, gvec,
d->msi->pirq, gflags);
}
@@ -295,19 +295,19 @@ static int pt_msix_update_one(struct pt_dev *dev, int
entry_nr)
dev->msix->table_base);
if ( ret )
{
- PT_LOG("error map msix entry %x\n", entry_nr);
+ PT_LOG("Error: Mapping msix entry %x\n", entry_nr);
return ret;
}
entry->pirq = pirq;
}
- PT_LOG("now update msix entry %x with pirq %x gvec %x\n",
+ PT_LOG("Update msix entry %x with pirq %x gvec %x\n",
entry_nr, pirq, gvec);
ret = xc_domain_update_msi_irq(xc_handle, domid, gvec, pirq, gflags);
if ( ret )
{
- PT_LOG("error update msix irq info for entry %d\n",
entry_nr);
+ PT_LOG("Error: Updating msix irq info for entry %d\n",
entry_nr);
return ret;
}
@@ -378,7 +378,7 @@ void pt_msix_disable(struct pt_dev *dev)
static void pci_msix_invalid_write(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
- PT_LOG("invalid write to MSI-X table, \
+ PT_LOG("Error: Invalid write to MSI-X table, \
only dword access is allowed.\n");
}
@@ -391,8 +391,8 @@ static void pci_msix_writel(void *opaque, target_phys_addr_t
addr, uint32_t val)
if ( addr % 4 )
{
- PT_LOG("unaligned dword access to MSI-X table, addr
%016"PRIx64"\n",
- addr);
+ PT_LOG("Error: Unaligned dword access to MSI-X table, \
+ addr %016"PRIx64"\n", addr);
return;
}
@@ -402,8 +402,8 @@ static void pci_msix_writel(void *opaque, target_phys_addr_t
addr, uint32_t val)
if ( offset != 3 && msix->enabled &&
!(entry->io_mem[3] & 0x1) )
{
- PT_LOG("can not update msix entry %d since MSI-X is already \
- function now.\n", entry_nr);
+ PT_LOG("Error: Can''t update msix entry %d since MSI-X is
already \
+ function.\n", entry_nr);
return;
}
@@ -427,7 +427,7 @@ static CPUWriteMemoryFunc *pci_msix_write[] = {
static uint32_t pci_msix_invalid_read(void *opaque, target_phys_addr_t addr)
{
- PT_LOG("invalid read to MSI-X table, \
+ PT_LOG("Error: Invalid read to MSI-X table, \
only dword access is allowed.\n");
return 0;
}
@@ -440,8 +440,8 @@ static uint32_t pci_msix_readl(void *opaque,
target_phys_addr_t addr)
if ( addr % 4 )
{
- PT_LOG("unaligned dword access to MSI-X table, addr
%016"PRIx64"\n",
- addr);
+ PT_LOG("Error: Unaligned dword access to MSI-X table, \
+ addr %016"PRIx64"\n", addr);
return 0;
}
@@ -504,7 +504,7 @@ int pt_msix_init(struct pt_dev *dev, int pos)
if ( id != PCI_CAP_ID_MSIX )
{
- PT_LOG("error id %x pos %x\n", id, pos);
+ PT_LOG("Error: Invalid id %x pos %x\n", id, pos);
return -1;
}
@@ -516,7 +516,7 @@ int pt_msix_init(struct pt_dev *dev, int pos)
+ total_entries*sizeof(struct msix_entry_info));
if ( !dev->msix )
{
- PT_LOG("error allocation pt_msix_info\n");
+ PT_LOG("Error: Allocating pt_msix_info failed.\n");
return -1;
}
memset(dev->msix, 0, sizeof(struct pt_msix_info)
@@ -538,7 +538,7 @@ int pt_msix_init(struct pt_dev *dev, int pos)
fd = open("/dev/mem", O_RDWR);
if ( fd == -1 )
{
- PT_LOG("Can''t open /dev/mem: %s\n",
strerror(errno));
+ PT_LOG("Error: Can''t open /dev/mem: %s\n",
strerror(errno));
goto error_out;
}
dev->msix->phys_iomem_base = mmap(0, total_entries * 16,
@@ -546,7 +546,7 @@ int pt_msix_init(struct pt_dev *dev, int pos)
fd, dev->msix->table_base + table_off);
if ( dev->msix->phys_iomem_base == MAP_FAILED )
{
- PT_LOG("Can''t map physical MSI-X table: %s\n",
strerror(errno));
+ PT_LOG("Error: Can''t map physical MSI-X table:
%s\n", strerror(errno));
close(fd);
goto error_out;
}
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
Ian Jackson
2009-Feb-19 17:13 UTC
[Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.
Yuji Shimada writes ("[PATCH] ioemu: Cleanup the code of PCI
passthrough."):> This patch cleanups the code of PCI passthrough.
Thanks but this doesn''t apply to the current qemu-xen-unstable head
(commit 200a4ece52fa37d6b884b52c47e3d56b9c1c7563)
Some of these changes, for example this one:> - Use LIST_FOREACH(). Don''t use lh_first, le_next directly.
seem to have been applied already for example in
8c771eb6294afc5b3754a9e3de51568d4e5986c2
Can you refresh and resend the patch, please ?
Thanks,
Ian.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
Yuji Shimada
2009-Feb-20 04:55 UTC
Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.
On Thu, 19 Feb 2009 17:13:42 +0000 Ian Jackson <Ian.Jackson@eu.citrix.com> wrote:> Yuji Shimada writes ("[PATCH] ioemu: Cleanup the code of PCI passthrough."): > > This patch cleanups the code of PCI passthrough. > > Thanks but this doesn''t apply to the current qemu-xen-unstable head > (commit 200a4ece52fa37d6b884b52c47e3d56b9c1c7563) > > Some of these changes, for example this one: > > - Use LIST_FOREACH(). Don''t use lh_first, le_next directly. > seem to have been applied already for example in > 8c771eb6294afc5b3754a9e3de51568d4e5986c2 > > Can you refresh and resend the patch, please ?My patch was created for commit 200a4ece52fa37d6b884b52c47e3d56b9c1c7563. But I found the patch has a trailing whitespace. This might prevent the patch from applying. I removed a trailing whitespace from the patch and attach it to this mail. If the patch doesn''t apply to the current qemu-xen-unstable head, Could you send error messages? The patch cleanups the code of PCI passthrough. - Use LIST_FOREACH(). Don''t use lh_first, le_next directly. - Use pci_{read, write}_block instead of "switch(len) case [124] pci_{read, write}_{byte, word, long}();". - Eliminate duplicate codes using PT_MEARGE_VALUE macro. - Define PCI_ERR_* macro in pass-through.h if libpci is old. - Remove the unreasonable loop from pt_aer_reg_{save,restore}. - Enable pt_aer_reg_{save,restore}, even if libpci is old. - Fix ro_mask and remove unnecessary pt_xxx_reg_write functions. - Add "Error:" or "Warning:" to messages. - Remove verbose messages. Thanks, -- Yuji Shimada. Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.j> diff --git a/hw/pass-through.c b/hw/pass-through.c index c2a6ec1..1de0162 100644 --- a/hw/pass-through.c +++ b/hw/pass-through.c @@ -126,18 +126,6 @@ static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev, static int pt_pmcsr_reg_write(struct pt_dev *ptdev, struct pt_reg_tbl *cfg_entry, uint16_t *value, uint16_t dev_value, uint16_t valid_mask); -static int pt_devctrl_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask); -static int pt_linkctrl_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask); -static int pt_devctrl2_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask); -static int pt_linkctrl2_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask); static int pt_msgctrl_reg_write(struct pt_dev *ptdev, struct pt_reg_tbl *cfg_entry, uint16_t *value, uint16_t dev_value, uint16_t valid_mask); @@ -413,7 +401,7 @@ static struct pt_reg_info_tbl pt_emu_reg_pm_tbl[] = { .offset = PCI_PM_CTRL, .size = 2, .init_val = 0x0008, - .ro_mask = 0x60FC, + .ro_mask = 0xE1FC, .emu_mask = 0x8100, .init = pt_pmcsr_reg_init, .u.w.read = pt_word_reg_read, @@ -494,11 +482,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = { .offset = PCI_EXP_DEVCTL, .size = 2, .init_val = 0x2810, - .ro_mask = 0x0000, + .ro_mask = 0x8400, .emu_mask = 0xFFFF, .init = pt_common_reg_init, .u.w.read = pt_word_reg_read, - .u.w.write = pt_devctrl_reg_write, + .u.w.write = pt_word_reg_write, .u.w.restore = pt_word_reg_restore, }, /* Link Control reg */ @@ -506,11 +494,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = { .offset = PCI_EXP_LNKCTL, .size = 2, .init_val = 0x0000, - .ro_mask = 0x0000, + .ro_mask = 0xFC34, .emu_mask = 0xFFFF, .init = pt_linkctrl_reg_init, .u.w.read = pt_word_reg_read, - .u.w.write = pt_linkctrl_reg_write, + .u.w.write = pt_word_reg_write, .u.w.restore = pt_word_reg_restore, }, /* Device Control 2 reg */ @@ -518,11 +506,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = { .offset = 0x28, .size = 2, .init_val = 0x0000, - .ro_mask = 0x0000, + .ro_mask = 0xFFE0, .emu_mask = 0xFFFF, .init = pt_devctrl2_reg_init, .u.w.read = pt_word_reg_read, - .u.w.write = pt_devctrl2_reg_write, + .u.w.write = pt_word_reg_write, .u.w.restore = pt_word_reg_restore, }, /* Link Control 2 reg */ @@ -530,11 +518,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = { .offset = 0x30, .size = 2, .init_val = 0x0000, - .ro_mask = 0x0000, + .ro_mask = 0xE040, .emu_mask = 0xFFFF, .init = pt_linkctrl2_reg_init, .u.w.read = pt_word_reg_read, - .u.w.write = pt_linkctrl2_reg_write, + .u.w.write = pt_word_reg_write, .u.w.restore = pt_word_reg_restore, }, { @@ -1051,8 +1039,7 @@ struct pt_reg_grp_tbl* pt_find_reg_grp( struct pt_reg_grp_tbl* reg_grp_entry = NULL; /* find register group entry */ - for (reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first; reg_grp_entry; - reg_grp_entry = reg_grp_entry->entries.le_next) + LIST_FOREACH(reg_grp_entry, &ptdev->reg_grp_tbl_head, entries) { /* check address */ if ((reg_grp_entry->base_offset <= address) && @@ -1075,8 +1062,7 @@ struct pt_reg_tbl* pt_find_reg( uint32_t real_offset = 0; /* find register entry */ - for (reg_entry = reg_grp->reg_tbl_head.lh_first; reg_entry; - reg_entry = reg_entry->entries.le_next) + LIST_FOREACH(reg_entry, ®_grp->reg_tbl_head, entries) { reg = reg_entry->reg; real_offset = (reg_grp->base_offset + reg->offset); @@ -1140,7 +1126,7 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, /* check offset range */ if (address >= 0xFF) { - PT_LOG("Failed to write register with offset exceeding FFh. " + PT_LOG("Error: Failed to write register with offset exceeding FFh. " "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); @@ -1150,7 +1136,7 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, /* check write size */ if ((len != 1) && (len != 2) && (len != 4)) { - PT_LOG("Failed to write register with invalid access length. " + PT_LOG("Error: Failed to write register with invalid access length. " "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); @@ -1160,8 +1146,8 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, /* check offset alignment */ if (address & (len-1)) { - PT_LOG("Failed to write register with invalid access size alignment. " - "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", + PT_LOG("Error: Failed to write register with invalid access size " + "alignment. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); goto exit; @@ -1172,8 +1158,8 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, if ((index >= 0) && (val > 0 && val < PT_BAR_ALLF) && (assigned_device->bases[index].bar_flag == PT_BAR_FLAG_UNUSED)) { - PT_LOG("Guest attempt to set address to unused Base Address Register. " - "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", + PT_LOG("Warning: Guest attempt to set address to unused Base Address " + "Register. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); } @@ -1194,7 +1180,7 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, if (reg_grp->grp_type == GRP_TYPE_HARDWIRED) { /* ignore silently */ - PT_LOG("Access to 0 Hardwired register. " + PT_LOG("Warning: Access to 0 Hardwired register. " "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); @@ -1203,28 +1189,14 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, } /* read I/O device register value */ - switch (len) { - case 1: - read_val = pci_read_byte(pci_dev, address); - break; - case 2: - read_val = pci_read_word(pci_dev, address); - break; - case 4: - read_val = pci_read_long(pci_dev, address); - break; - } + ret = pci_read_block(pci_dev, address, (uint8_t *)&read_val, len); - /* check libpci result */ - valid_mask = (0xFFFFFFFF >> ((4 - len) << 3)); - if ((read_val & valid_mask) == valid_mask) + if (!ret) { - PT_LOG("Warning: Return ALL F from libpci read. " - "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", - pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), - address, len); + PT_LOG("Error: pci_read_block failed. return value[%d].\n", ret); + memset((uint8_t *)&read_val, 0xff, len); } - + /* pass directly to libpci for passthrough type register group */ if (reg_grp_entry == NULL) goto out; @@ -1303,17 +1277,10 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, val >>= ((address & 3) << 3); out: - switch (len){ - case 1: - pci_write_byte(pci_dev, address, val); - break; - case 2: - pci_write_word(pci_dev, address, val); - break; - case 4: - pci_write_long(pci_dev, address, val); - break; - } + ret = pci_write_block(pci_dev, address, (uint8_t *)&val, len); + + if (!ret) + PT_LOG("Error: pci_write_block failed. return value[%d].\n", ret); if (pm_state->flags & PT_FLAG_TRANSITING) /* set QEMUTimer */ @@ -1329,7 +1298,7 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len) struct pt_dev *assigned_device = (struct pt_dev *)d; struct pci_dev *pci_dev = assigned_device->pci_dev; struct pt_pm_info *pm_state = assigned_device->pm_state; - uint32_t val = 0xFFFFFFFF; + uint32_t val = 0; struct pt_reg_grp_tbl *reg_grp_entry = NULL; struct pt_reg_grp_info_tbl *reg_grp = NULL; struct pt_reg_tbl *reg_entry = NULL; @@ -1344,7 +1313,7 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len) /* check offset range */ if (address >= 0xFF) { - PT_LOG("Failed to read register with offset exceeding FFh. " + PT_LOG("Error: Failed to read register with offset exceeding FFh. " "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); @@ -1354,7 +1323,7 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len) /* check read size */ if ((len != 1) && (len != 2) && (len != 4)) { - PT_LOG("Failed to read register with invalid access length. " + PT_LOG("Error: Failed to read register with invalid access length. " "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); @@ -1364,8 +1333,8 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len) /* check offset alignment */ if (address & (len-1)) { - PT_LOG("Failed to read register with invalid access size alignment. " - "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", + PT_LOG("Error: Failed to read register with invalid access size " + "alignment. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); goto exit; @@ -1393,26 +1362,12 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len) } /* read I/O device register value */ - switch (len) { - case 1: - val = pci_read_byte(pci_dev, address); - break; - case 2: - val = pci_read_word(pci_dev, address); - break; - case 4: - val = pci_read_long(pci_dev, address); - break; - } + ret = pci_read_block(pci_dev, address, (uint8_t *)&val, len); - /* check libpci result */ - valid_mask = (0xFFFFFFFF >> ((4 - len) << 3)); - if ((val & valid_mask) == valid_mask) + if (!ret) { - PT_LOG("Warning: Return ALL F from libpci read. " - "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", - pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), - address, len); + PT_LOG("Error: pci_read_block failed. return value[%d].\n", ret); + memset((uint8_t *)&val, 0xff, len); } /* just return the I/O device register value for @@ -1514,7 +1471,7 @@ static void pt_libpci_fixup(struct pci_dev *dev) fp = fopen(path, "r"); if ( !fp ) { - PT_LOG("Can''t open %s: %s\n", path, strerror(errno)); + PT_LOG("Error: Can''t open %s: %s\n", path, strerror(errno)); return; } @@ -1522,7 +1479,7 @@ static void pt_libpci_fixup(struct pci_dev *dev) { if ( fscanf(fp, "%llx %llx %llx", &start, &end, &flags) != 3 ) { - PT_LOG("Syntax error in %s\n", path); + PT_LOG("Error: Syntax error in %s\n", path); break; } @@ -1800,8 +1757,8 @@ static void pt_bar_mapping(struct pt_dev *ptdev, int io_enable, int mem_enable) /* check overlapped address */ ret = pt_chk_bar_overlap(dev->bus, dev->devfn, r_addr, r_size); if (ret > 0) - PT_LOG("ptdev[%02x:%02x.%x][Region:%d][Address:%08xh][Size:%08xh] " - "is overlapped.\n", pci_bus_num(dev->bus), + PT_LOG("Warning: ptdev[%02x:%02x.%x][Region:%d][Address:%08xh]" + "[Size:%08xh] is overlapped.\n", pci_bus_num(dev->bus), (dev->devfn >> 3) & 0x1F, (dev->devfn & 0x7), i, r_addr, r_size); @@ -1841,68 +1798,51 @@ int check_power_state(struct pt_dev *ptdev) return 0; } -/* save AER register */ -static void pt_aer_reg_save(struct pt_dev *ptdev) +/* save AER one register */ +static void aer_save_one_register(struct pt_dev *ptdev, int offset) { PCIDevice *d = &ptdev->dev; uint32_t aer_base = ptdev->pm_state->aer_base; - int i = 0; - /* Root Port and Root Complex Event Collector need size expansion */ - int aer_size = 0x2c; -#ifdef PCI_ERR_UNCOR_MASK - for (i=0; i < aer_size; i+=4) - { - switch (i) { - /* after reset, following register values should be restored. - * So, save them. - */ - case PCI_ERR_UNCOR_MASK: - case PCI_ERR_UNCOR_SEVER: - case PCI_ERR_COR_MASK: - case PCI_ERR_CAP: - *(uint32_t*)(d->config + (aer_base + i)) - = pci_read_long(ptdev->pci_dev, (aer_base + i)); - break; - default: - break; - } - } -#endif + *(uint32_t*)(d->config + (aer_base + offset)) + = pci_read_long(ptdev->pci_dev, (aer_base + offset)); } -/* restore AER register */ -static void pt_aer_reg_restore(struct pt_dev *ptdev) +/* save AER registers */ +static void pt_aer_reg_save(struct pt_dev *ptdev) +{ + /* after reset, following register values should be restored. + * So, save them. + */ + aer_save_one_register(ptdev, PCI_ERR_UNCOR_MASK); + aer_save_one_register(ptdev, PCI_ERR_UNCOR_SEVER); + aer_save_one_register(ptdev, PCI_ERR_COR_MASK); + aer_save_one_register(ptdev, PCI_ERR_CAP); +} + +/* restore AER one register */ +static void aer_restore_one_register(struct pt_dev *ptdev, int offset) { PCIDevice *d = &ptdev->dev; uint32_t aer_base = ptdev->pm_state->aer_base; - int i = 0; uint32_t config = 0; - /* Root Port and Root Complex Event Collector need size expansion */ - int aer_size = 0x2c; -#ifdef PCI_ERR_UNCOR_MASK - for (i=0; i < aer_size; i+=4) - { - switch (i) { - /* the following registers should be reconfigured to correct values - * after reset. restore them. - */ - case PCI_ERR_UNCOR_MASK: - case PCI_ERR_UNCOR_SEVER: - case PCI_ERR_COR_MASK: - case PCI_ERR_CAP: - config = *(uint32_t*)(d->config + (aer_base + i)); - pci_write_long(ptdev->pci_dev, (aer_base + i), config); - break; - /* other registers should not be reconfigured after reset - * if there is no reason - */ - default: - break; - } - } -#endif + config = *(uint32_t*)(d->config + (aer_base + offset)); + pci_write_long(ptdev->pci_dev, (aer_base + offset), config); +} + +/* restore AER registers */ +static void pt_aer_reg_restore(struct pt_dev *ptdev) +{ + /* the following registers should be reconfigured to correct values + * after reset. restore them. + * other registers should not be reconfigured after reset + * if there is no reason + */ + aer_restore_one_register(ptdev, PCI_ERR_UNCOR_MASK); + aer_restore_one_register(ptdev, PCI_ERR_UNCOR_SEVER); + aer_restore_one_register(ptdev, PCI_ERR_COR_MASK); + aer_restore_one_register(ptdev, PCI_ERR_CAP); } /* reset Interrupt and I/O resource */ @@ -2115,7 +2055,7 @@ static int pt_config_reg_init(struct pt_dev *ptdev, reg_entry = qemu_mallocz(sizeof(struct pt_reg_tbl)); if (reg_entry == NULL) { - PT_LOG("Failed to allocate memory.\n"); + PT_LOG("Error: Failed to allocate memory.\n"); err = -1; goto out; } @@ -2171,7 +2111,7 @@ static int pt_config_init(struct pt_dev *ptdev) reg_grp_entry = qemu_mallocz(sizeof(struct pt_reg_grp_tbl)); if (reg_grp_entry == NULL) { - PT_LOG("Failed to allocate memory.\n"); + PT_LOG("Error: Failed to allocate memory.\n"); err = -1; goto out; } @@ -2239,10 +2179,10 @@ static void pt_config_delete(struct pt_dev *ptdev) } /* free all register group entry */ - while ((reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first) != NULL) + while((reg_grp_entry = LIST_FIRST(&ptdev->reg_grp_tbl_head)) != NULL) { /* free all register entry */ - while ((reg_entry = reg_grp_entry->reg_tbl_head.lh_first) != NULL) + while((reg_entry = LIST_FIRST(®_grp_entry->reg_tbl_head)) != NULL) { LIST_REMOVE(reg_entry, entries); qemu_free(reg_entry); @@ -2624,7 +2564,7 @@ static uint8_t pt_msi_size_init(struct pt_dev *ptdev, if ( !ptdev->msi ) { /* exit I/O emulator */ - PT_LOG("error allocation pt_msi_info. I/O emulator exit.\n"); + PT_LOG("Error: Allocating pt_msi_info failed. I/O emulator exit.\n"); exit(1); } memset(ptdev->msi, 0, sizeof(struct pt_msi_info)); @@ -2754,8 +2694,7 @@ static int pt_byte_reg_read(struct pt_dev *ptdev, /* emulate byte register */ valid_emu_mask = reg->emu_mask & valid_mask; - *value = ((*value & ~valid_emu_mask) | - (cfg_entry->data & valid_emu_mask)); + *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); return 0; } @@ -2770,8 +2709,7 @@ static int pt_word_reg_read(struct pt_dev *ptdev, /* emulate word register */ valid_emu_mask = reg->emu_mask & valid_mask; - *value = ((*value & ~valid_emu_mask) | - (cfg_entry->data & valid_emu_mask)); + *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); return 0; } @@ -2786,8 +2724,7 @@ static int pt_long_reg_read(struct pt_dev *ptdev, /* emulate long register */ valid_emu_mask = reg->emu_mask & valid_mask; - *value = ((*value & ~valid_emu_mask) | - (cfg_entry->data & valid_emu_mask)); + *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); return 0; } @@ -2833,8 +2770,7 @@ static int pt_bar_reg_read(struct pt_dev *ptdev, /* emulate BAR */ valid_emu_mask = bar_emu_mask & valid_mask; - *value = ((*value & ~valid_emu_mask) | - (cfg_entry->data & valid_emu_mask)); + *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); return 0; } @@ -2850,13 +2786,11 @@ static int pt_byte_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); return 0; } @@ -2872,13 +2806,11 @@ static int pt_word_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); return 0; } @@ -2894,13 +2826,11 @@ static int pt_long_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); return 0; } @@ -2917,12 +2847,11 @@ static int pt_cmd_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* mapping BAR */ pt_bar_mapping(ptdev, wr_value & PCI_COMMAND_IO, @@ -2988,8 +2917,7 @@ static int pt_bar_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* check whether we need to update the virtual region address or not */ switch (ptdev->bases[index].bar_flag) @@ -3007,7 +2935,8 @@ static int pt_bar_reg_write(struct pt_dev *ptdev, if ((last_addr >= 0x10000) && (cfg_entry->data != (PT_BAR_ALLF & ~bar_ro_mask))) { - PT_LOG("Guest attempt to set Base Address over the 64KB. " + PT_LOG("Warning: Guest attempt to set Base Address " + "over the 64KB. " "[%02x:%02x.%x][Offset:%02xh][Address:%08xh][Size:%08xh]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), @@ -3023,7 +2952,7 @@ static int pt_bar_reg_write(struct pt_dev *ptdev, { if (cfg_entry->data != (PT_BAR_ALLF & ~bar_ro_mask)) { - PT_LOG("Guest attempt to set high MMIO Base Address. " + PT_LOG("Warning: Guest attempt to set high MMIO Base Address. " "Ignore mapping. " "[%02x:%02x.%x][Offset:%02xh][High Address:%08xh]\n", pci_bus_num(d->bus), @@ -3066,8 +2995,7 @@ static int pt_bar_reg_write(struct pt_dev *ptdev, exit: /* create value for writing to I/O device register */ throughable_mask = ~bar_emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); return 0; } @@ -3099,16 +3027,14 @@ static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* update the corresponding virtual region address */ r->addr = cfg_entry->data; /* create value for writing to I/O device register */ throughable_mask = ~bar_emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); return 0; } @@ -3122,22 +3048,16 @@ static int pt_pmcsr_reg_write(struct pt_dev *ptdev, PCIDevice *d = &ptdev->dev; uint16_t writable_mask = 0; uint16_t throughable_mask = 0; - uint16_t pmcsr_mask = (PCI_PM_CTRL_PME_ENABLE | - PCI_PM_CTRL_DATA_SEL_MASK | - PCI_PM_CTRL_PME_STATUS); struct pt_pm_info *pm_state = ptdev->pm_state; uint16_t read_val = 0; /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~pmcsr_mask; - - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* set I/O device power state */ pm_state->cur_state = (dev_value & PCI_PM_CTRL_STATE_MASK); @@ -3236,101 +3156,6 @@ static int pt_pmcsr_reg_write(struct pt_dev *ptdev, return 0; } -/* write Device Control register */ -static int pt_devctrl_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask) -{ - struct pt_reg_info_tbl *reg = cfg_entry->reg; - uint16_t writable_mask = 0; - uint16_t throughable_mask = 0; - uint16_t devctrl_mask = (PCI_EXP_DEVCTL_AUX_PME | 0x8000); - - /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~devctrl_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); - - /* create value for writing to I/O device register */ - throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); - - return 0; -} - -/* write Link Control register */ -static int pt_linkctrl_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask) -{ - struct pt_reg_info_tbl *reg = cfg_entry->reg; - uint16_t writable_mask = 0; - uint16_t throughable_mask = 0; - uint16_t linkctrl_mask = (0x04 | PCI_EXP_LNKCTL_DISABLE | - PCI_EXP_LNKCTL_RETRAIN | - 0x0400 | 0x0800 | 0xF000); - - /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~linkctrl_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); - - /* create value for writing to I/O device register */ - throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); - - return 0; -} - -/* write Device Control2 register */ -static int pt_devctrl2_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask) -{ - struct pt_reg_info_tbl *reg = cfg_entry->reg; - uint16_t writable_mask = 0; - uint16_t throughable_mask = 0; - uint16_t devctrl2_mask = 0xFFE0; - - /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~devctrl2_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); - - /* create value for writing to I/O device register */ - throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); - - return 0; -} - -/* write Link Control2 register */ -static int pt_linkctrl2_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask) -{ - struct pt_reg_info_tbl *reg = cfg_entry->reg; - uint16_t writable_mask = 0; - uint16_t throughable_mask = 0; - uint16_t linkctrl2_mask = (0x0040 | 0xE000); - - /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & - ~linkctrl2_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); - - /* create value for writing to I/O device register */ - throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); - - return 0; -} - /* write Message Control register */ static int pt_msgctrl_reg_write(struct pt_dev *ptdev, struct pt_reg_tbl *cfg_entry, @@ -3346,22 +3171,19 @@ static int pt_msgctrl_reg_write(struct pt_dev *ptdev, /* Currently no support for multi-vector */ if ((*value & PCI_MSI_FLAGS_QSIZE) != 0x0) - PT_LOG("try to set more than 1 vector ctrl %x\n", *value); + PT_LOG("Warning: try to set more than 1 vector ctrl %x\n", *value); /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* update the msi_info too */ ptdev->msi->flags |= cfg_entry->data & ~(MSI_FLAG_UNINIT | PT_MSI_MAPPED | PCI_MSI_FLAGS_ENABLE); - PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl, cfg_entry->data); - /* create value for writing to I/O device register */ val = *value; throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* update MSI */ if (val & PCI_MSI_FLAGS_ENABLE) @@ -3420,16 +3242,13 @@ static int pt_msgaddr32_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* update the msi_info too */ ptdev->msi->addr_lo = cfg_entry->data; - PT_LOG("old_addr_lo:%08xh new_addr_lo:%08xh\n", old_addr, cfg_entry->data); - /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* update MSI */ if (cfg_entry->data != old_addr) @@ -3455,22 +3274,19 @@ static int pt_msgaddr64_reg_write(struct pt_dev *ptdev, if (!(ptdev->msi->flags & PCI_MSI_FLAGS_64BIT)) { /* exit I/O emulator */ - PT_LOG("why comes to Upper Address without 64 bit support??\n"); + PT_LOG("Error: why comes to Upper Address without 64 bit support??\n"); return -1; } /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* update the msi_info too */ ptdev->msi->addr_hi = cfg_entry->data; - PT_LOG("old_addr_hi:%08xh new_addr_hi:%08xh\n", old_addr, cfg_entry->data); - /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* update MSI */ if (cfg_entry->data != old_addr) @@ -3506,16 +3322,13 @@ static int pt_msgdata_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* update the msi_info too */ ptdev->msi->data = cfg_entry->data; - PT_LOG("old_data:%04xh new_data:%04xh\n", old_data, cfg_entry->data); - /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* update MSI */ if (cfg_entry->data != old_data) @@ -3539,14 +3352,11 @@ static int pt_msixctrl_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); - PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl, cfg_entry->data); - /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* update MSI-X */ if ((*value & PCI_MSIX_ENABLE) && !(*value & PCI_MSIX_MASK)) @@ -3979,7 +3789,7 @@ int pt_init(PCIBus *e_bus, const char *direct_pci) pci_access = pci_alloc(); if ( pci_access == NULL ) { - PT_LOG("pci_access is NULL\n"); + PT_LOG("Error: pci_access is NULL\n"); return -1; } pci_init(pci_access); diff --git a/hw/pass-through.h b/hw/pass-through.h index b44b9d7..2b2dbd2 100644 --- a/hw/pass-through.h +++ b/hw/pass-through.h @@ -86,6 +86,26 @@ #define PCI_EXP_TYPE_ROOT_EC 0xa #endif +#ifndef PCI_ERR_UNCOR_MASK +/* Uncorrectable Error Mask */ +#define PCI_ERR_UNCOR_MASK 8 +#endif + +#ifndef PCI_ERR_UNCOR_SEVER +/* Uncorrectable Error Severity */ +#define PCI_ERR_UNCOR_SEVER 12 +#endif + +#ifndef PCI_ERR_COR_MASK +/* Correctable Error Mask */ +#define PCI_ERR_COR_MASK 20 +#endif + +#ifndef PCI_ERR_CAP +/* Advanced Error Capabilities */ +#define PCI_ERR_CAP 24 +#endif + #ifndef PCI_EXT_CAP_ID /* Extended Capabilities (PCI-X 2.0 and PCI Express) */ #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) diff --git a/hw/pt-msi.c b/hw/pt-msi.c index bdd1b38..6b0aaa1 100644 --- a/hw/pt-msi.c +++ b/hw/pt-msi.c @@ -68,7 +68,7 @@ int pt_msi_setup(struct pt_dev *dev) if ( !(dev->msi->flags & MSI_FLAG_UNINIT) ) { - PT_LOG("setup physical after initialized?? \n"); + PT_LOG("Error: setup physical after initialized?? \n"); return -1; } @@ -76,13 +76,13 @@ int pt_msi_setup(struct pt_dev *dev) dev->pci_dev->dev << 3 | dev->pci_dev->func, dev->pci_dev->bus, 0, 0) ) { - PT_LOG("error map msi\n"); + PT_LOG("Error: Mapping of MSI failed.\n"); return -1; } if ( pirq < 0 ) { - PT_LOG("invalid pirq number\n"); + PT_LOG("Error: Invalid pirq number\n"); return -1; } @@ -125,7 +125,7 @@ int pt_msi_update(struct pt_dev *d) addr = (uint64_t)d->msi->addr_hi << 32 | d->msi->addr_lo; gflags = __get_msi_gflags(d->msi->data, addr); - PT_LOG("now update msi with pirq %x gvec %x\n", d->msi->pirq, gvec); + PT_LOG("Update msi with pirq %x gvec %x\n", d->msi->pirq, gvec); return xc_domain_update_msi_irq(xc_handle, domid, gvec, d->msi->pirq, gflags); } @@ -295,19 +295,19 @@ static int pt_msix_update_one(struct pt_dev *dev, int entry_nr) dev->msix->table_base); if ( ret ) { - PT_LOG("error map msix entry %x\n", entry_nr); + PT_LOG("Error: Mapping msix entry %x\n", entry_nr); return ret; } entry->pirq = pirq; } - PT_LOG("now update msix entry %x with pirq %x gvec %x\n", + PT_LOG("Update msix entry %x with pirq %x gvec %x\n", entry_nr, pirq, gvec); ret = xc_domain_update_msi_irq(xc_handle, domid, gvec, pirq, gflags); if ( ret ) { - PT_LOG("error update msix irq info for entry %d\n", entry_nr); + PT_LOG("Error: Updating msix irq info for entry %d\n", entry_nr); return ret; } @@ -378,7 +378,7 @@ void pt_msix_disable(struct pt_dev *dev) static void pci_msix_invalid_write(void *opaque, target_phys_addr_t addr, uint32_t val) { - PT_LOG("invalid write to MSI-X table, \ + PT_LOG("Error: Invalid write to MSI-X table, \ only dword access is allowed.\n"); } @@ -391,8 +391,8 @@ static void pci_msix_writel(void *opaque, target_phys_addr_t addr, uint32_t val) if ( addr % 4 ) { - PT_LOG("unaligned dword access to MSI-X table, addr %016"PRIx64"\n", - addr); + PT_LOG("Error: Unaligned dword access to MSI-X table, \ + addr %016"PRIx64"\n", addr); return; } @@ -402,8 +402,8 @@ static void pci_msix_writel(void *opaque, target_phys_addr_t addr, uint32_t val) if ( offset != 3 && msix->enabled && !(entry->io_mem[3] & 0x1) ) { - PT_LOG("can not update msix entry %d since MSI-X is already \ - function now.\n", entry_nr); + PT_LOG("Error: Can''t update msix entry %d since MSI-X is already \ + function.\n", entry_nr); return; } @@ -427,7 +427,7 @@ static CPUWriteMemoryFunc *pci_msix_write[] = { static uint32_t pci_msix_invalid_read(void *opaque, target_phys_addr_t addr) { - PT_LOG("invalid read to MSI-X table, \ + PT_LOG("Error: Invalid read to MSI-X table, \ only dword access is allowed.\n"); return 0; } @@ -440,8 +440,8 @@ static uint32_t pci_msix_readl(void *opaque, target_phys_addr_t addr) if ( addr % 4 ) { - PT_LOG("unaligned dword access to MSI-X table, addr %016"PRIx64"\n", - addr); + PT_LOG("Error: Unaligned dword access to MSI-X table, \ + addr %016"PRIx64"\n", addr); return 0; } @@ -504,7 +504,7 @@ int pt_msix_init(struct pt_dev *dev, int pos) if ( id != PCI_CAP_ID_MSIX ) { - PT_LOG("error id %x pos %x\n", id, pos); + PT_LOG("Error: Invalid id %x pos %x\n", id, pos); return -1; } @@ -516,7 +516,7 @@ int pt_msix_init(struct pt_dev *dev, int pos) + total_entries*sizeof(struct msix_entry_info)); if ( !dev->msix ) { - PT_LOG("error allocation pt_msix_info\n"); + PT_LOG("Error: Allocating pt_msix_info failed.\n"); return -1; } memset(dev->msix, 0, sizeof(struct pt_msix_info) @@ -538,7 +538,7 @@ int pt_msix_init(struct pt_dev *dev, int pos) fd = open("/dev/mem", O_RDWR); if ( fd == -1 ) { - PT_LOG("Can''t open /dev/mem: %s\n", strerror(errno)); + PT_LOG("Error: Can''t open /dev/mem: %s\n", strerror(errno)); goto error_out; } dev->msix->phys_iomem_base = mmap(0, total_entries * 16, @@ -546,7 +546,7 @@ int pt_msix_init(struct pt_dev *dev, int pos) fd, dev->msix->table_base + table_off); if ( dev->msix->phys_iomem_base == MAP_FAILED ) { - PT_LOG("Can''t map physical MSI-X table: %s\n", strerror(errno)); + PT_LOG("Error: Can''t map physical MSI-X table: %s\n", strerror(errno)); close(fd); goto error_out; } _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Yuji Shimada
2009-Feb-23 01:40 UTC
Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.
On Fri, 20 Feb 2009 13:55:06 +0900 Yuji Shimada <shimada-yxb@necst.nec.co.jp> wrote:> On Thu, 19 Feb 2009 17:13:42 +0000 > Ian Jackson <Ian.Jackson@eu.citrix.com> wrote: > > > Yuji Shimada writes ("[PATCH] ioemu: Cleanup the code of PCI passthrough."): > > > This patch cleanups the code of PCI passthrough. > > > > Thanks but this doesn''t apply to the current qemu-xen-unstable head > > (commit 200a4ece52fa37d6b884b52c47e3d56b9c1c7563) > > > > Some of these changes, for example this one: > > > - Use LIST_FOREACH(). Don''t use lh_first, le_next directly. > > seem to have been applied already for example in > > 8c771eb6294afc5b3754a9e3de51568d4e5986c2 > > > > Can you refresh and resend the patch, please ? > > My patch was created for commit 200a4ece52fa37d6b884b52c47e3d56b9c1c7563. > But I found the patch has a trailing whitespace. This might prevent > the patch from applying. I removed a trailing whitespace from the > patch and attach it to this mail. > > If the patch doesn''t apply to the current qemu-xen-unstable head, > Could you send error messages?I found "git apply" command did not apply my patch, while "patch" command applied it. I re-created my patch, and I tested that "git apply" command applied it. I attach it to this mail. Could you try to apply it? The patch cleanups the code of PCI passthrough. - Use LIST_FOREACH(). Don''t use lh_first, le_next directly. - Use pci_{read, write}_block instead of "switch(len) case [124] pci_{read, write}_{byte, word, long}();". - Eliminate duplicate codes using PT_MEARGE_VALUE macro. - Define PCI_ERR_* macro in pass-through.h if libpci is old. - Remove the unreasonable loop from pt_aer_reg_{save,restore}. - Enable pt_aer_reg_{save,restore}, even if libpci is old. - Fix ro_mask and remove unnecessary pt_xxx_reg_write functions. - Add "Error:" or "Warning:" to messages. - Remove verbose messages. Thanks, -- Yuji Shimada. Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp> diff --git a/hw/pass-through.c b/hw/pass-through.c index c2a6ec1..855f69c 100644 --- a/hw/pass-through.c +++ b/hw/pass-through.c @@ -126,18 +126,6 @@ static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev, static int pt_pmcsr_reg_write(struct pt_dev *ptdev, struct pt_reg_tbl *cfg_entry, uint16_t *value, uint16_t dev_value, uint16_t valid_mask); -static int pt_devctrl_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask); -static int pt_linkctrl_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask); -static int pt_devctrl2_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask); -static int pt_linkctrl2_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask); static int pt_msgctrl_reg_write(struct pt_dev *ptdev, struct pt_reg_tbl *cfg_entry, uint16_t *value, uint16_t dev_value, uint16_t valid_mask); @@ -413,7 +401,7 @@ static struct pt_reg_info_tbl pt_emu_reg_pm_tbl[] = { .offset = PCI_PM_CTRL, .size = 2, .init_val = 0x0008, - .ro_mask = 0x60FC, + .ro_mask = 0xE1FC, .emu_mask = 0x8100, .init = pt_pmcsr_reg_init, .u.w.read = pt_word_reg_read, @@ -494,11 +482,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = { .offset = PCI_EXP_DEVCTL, .size = 2, .init_val = 0x2810, - .ro_mask = 0x0000, + .ro_mask = 0x8400, .emu_mask = 0xFFFF, .init = pt_common_reg_init, .u.w.read = pt_word_reg_read, - .u.w.write = pt_devctrl_reg_write, + .u.w.write = pt_word_reg_write, .u.w.restore = pt_word_reg_restore, }, /* Link Control reg */ @@ -506,11 +494,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = { .offset = PCI_EXP_LNKCTL, .size = 2, .init_val = 0x0000, - .ro_mask = 0x0000, + .ro_mask = 0xFC34, .emu_mask = 0xFFFF, .init = pt_linkctrl_reg_init, .u.w.read = pt_word_reg_read, - .u.w.write = pt_linkctrl_reg_write, + .u.w.write = pt_word_reg_write, .u.w.restore = pt_word_reg_restore, }, /* Device Control 2 reg */ @@ -518,11 +506,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = { .offset = 0x28, .size = 2, .init_val = 0x0000, - .ro_mask = 0x0000, + .ro_mask = 0xFFE0, .emu_mask = 0xFFFF, .init = pt_devctrl2_reg_init, .u.w.read = pt_word_reg_read, - .u.w.write = pt_devctrl2_reg_write, + .u.w.write = pt_word_reg_write, .u.w.restore = pt_word_reg_restore, }, /* Link Control 2 reg */ @@ -530,11 +518,11 @@ static struct pt_reg_info_tbl pt_emu_reg_pcie_tbl[] = { .offset = 0x30, .size = 2, .init_val = 0x0000, - .ro_mask = 0x0000, + .ro_mask = 0xE040, .emu_mask = 0xFFFF, .init = pt_linkctrl2_reg_init, .u.w.read = pt_word_reg_read, - .u.w.write = pt_linkctrl2_reg_write, + .u.w.write = pt_word_reg_write, .u.w.restore = pt_word_reg_restore, }, { @@ -1051,8 +1039,7 @@ struct pt_reg_grp_tbl* pt_find_reg_grp( struct pt_reg_grp_tbl* reg_grp_entry = NULL; /* find register group entry */ - for (reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first; reg_grp_entry; - reg_grp_entry = reg_grp_entry->entries.le_next) + LIST_FOREACH(reg_grp_entry, &ptdev->reg_grp_tbl_head, entries) { /* check address */ if ((reg_grp_entry->base_offset <= address) && @@ -1075,8 +1062,7 @@ struct pt_reg_tbl* pt_find_reg( uint32_t real_offset = 0; /* find register entry */ - for (reg_entry = reg_grp->reg_tbl_head.lh_first; reg_entry; - reg_entry = reg_entry->entries.le_next) + LIST_FOREACH(reg_entry, ®_grp->reg_tbl_head, entries) { reg = reg_entry->reg; real_offset = (reg_grp->base_offset + reg->offset); @@ -1140,7 +1126,7 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, /* check offset range */ if (address >= 0xFF) { - PT_LOG("Failed to write register with offset exceeding FFh. " + PT_LOG("Error: Failed to write register with offset exceeding FFh. " "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); @@ -1150,7 +1136,7 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, /* check write size */ if ((len != 1) && (len != 2) && (len != 4)) { - PT_LOG("Failed to write register with invalid access length. " + PT_LOG("Error: Failed to write register with invalid access length. " "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); @@ -1160,8 +1146,8 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, /* check offset alignment */ if (address & (len-1)) { - PT_LOG("Failed to write register with invalid access size alignment. " - "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", + PT_LOG("Error: Failed to write register with invalid access size " + "alignment. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); goto exit; @@ -1172,8 +1158,8 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, if ((index >= 0) && (val > 0 && val < PT_BAR_ALLF) && (assigned_device->bases[index].bar_flag == PT_BAR_FLAG_UNUSED)) { - PT_LOG("Guest attempt to set address to unused Base Address Register. " - "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", + PT_LOG("Warning: Guest attempt to set address to unused Base Address " + "Register. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); } @@ -1194,7 +1180,7 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, if (reg_grp->grp_type == GRP_TYPE_HARDWIRED) { /* ignore silently */ - PT_LOG("Access to 0 Hardwired register. " + PT_LOG("Warning: Access to 0 Hardwired register. " "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); @@ -1203,28 +1189,14 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, } /* read I/O device register value */ - switch (len) { - case 1: - read_val = pci_read_byte(pci_dev, address); - break; - case 2: - read_val = pci_read_word(pci_dev, address); - break; - case 4: - read_val = pci_read_long(pci_dev, address); - break; - } + ret = pci_read_block(pci_dev, address, (uint8_t *)&read_val, len); - /* check libpci result */ - valid_mask = (0xFFFFFFFF >> ((4 - len) << 3)); - if ((read_val & valid_mask) == valid_mask) + if (!ret) { - PT_LOG("Warning: Return ALL F from libpci read. " - "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", - pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), - address, len); + PT_LOG("Error: pci_read_block failed. return value[%d].\n", ret); + memset((uint8_t *)&read_val, 0xff, len); } - + /* pass directly to libpci for passthrough type register group */ if (reg_grp_entry == NULL) goto out; @@ -1303,17 +1275,10 @@ static void pt_pci_write_config(PCIDevice *d, uint32_t address, uint32_t val, val >>= ((address & 3) << 3); out: - switch (len){ - case 1: - pci_write_byte(pci_dev, address, val); - break; - case 2: - pci_write_word(pci_dev, address, val); - break; - case 4: - pci_write_long(pci_dev, address, val); - break; - } + ret = pci_write_block(pci_dev, address, (uint8_t *)&val, len); + + if (!ret) + PT_LOG("Error: pci_write_block failed. return value[%d].\n", ret); if (pm_state->flags & PT_FLAG_TRANSITING) /* set QEMUTimer */ @@ -1329,7 +1294,7 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len) struct pt_dev *assigned_device = (struct pt_dev *)d; struct pci_dev *pci_dev = assigned_device->pci_dev; struct pt_pm_info *pm_state = assigned_device->pm_state; - uint32_t val = 0xFFFFFFFF; + uint32_t val = 0; struct pt_reg_grp_tbl *reg_grp_entry = NULL; struct pt_reg_grp_info_tbl *reg_grp = NULL; struct pt_reg_tbl *reg_entry = NULL; @@ -1344,7 +1309,7 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len) /* check offset range */ if (address >= 0xFF) { - PT_LOG("Failed to read register with offset exceeding FFh. " + PT_LOG("Error: Failed to read register with offset exceeding FFh. " "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); @@ -1354,7 +1319,7 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len) /* check read size */ if ((len != 1) && (len != 2) && (len != 4)) { - PT_LOG("Failed to read register with invalid access length. " + PT_LOG("Error: Failed to read register with invalid access length. " "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); @@ -1364,8 +1329,8 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len) /* check offset alignment */ if (address & (len-1)) { - PT_LOG("Failed to read register with invalid access size alignment. " - "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", + PT_LOG("Error: Failed to read register with invalid access size " + "alignment. [%02x:%02x.%x][Offset:%02xh][Length:%d]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), address, len); goto exit; @@ -1393,26 +1358,12 @@ static uint32_t pt_pci_read_config(PCIDevice *d, uint32_t address, int len) } /* read I/O device register value */ - switch (len) { - case 1: - val = pci_read_byte(pci_dev, address); - break; - case 2: - val = pci_read_word(pci_dev, address); - break; - case 4: - val = pci_read_long(pci_dev, address); - break; - } + ret = pci_read_block(pci_dev, address, (uint8_t *)&val, len); - /* check libpci result */ - valid_mask = (0xFFFFFFFF >> ((4 - len) << 3)); - if ((val & valid_mask) == valid_mask) + if (!ret) { - PT_LOG("Warning: Return ALL F from libpci read. " - "[%02x:%02x.%x][Offset:%02xh][Length:%d]\n", - pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), - address, len); + PT_LOG("Error: pci_read_block failed. return value[%d].\n", ret); + memset((uint8_t *)&val, 0xff, len); } /* just return the I/O device register value for @@ -1514,7 +1465,7 @@ static void pt_libpci_fixup(struct pci_dev *dev) fp = fopen(path, "r"); if ( !fp ) { - PT_LOG("Can''t open %s: %s\n", path, strerror(errno)); + PT_LOG("Error: Can''t open %s: %s\n", path, strerror(errno)); return; } @@ -1522,7 +1473,7 @@ static void pt_libpci_fixup(struct pci_dev *dev) { if ( fscanf(fp, "%llx %llx %llx", &start, &end, &flags) != 3 ) { - PT_LOG("Syntax error in %s\n", path); + PT_LOG("Error: Syntax error in %s\n", path); break; } @@ -1800,8 +1751,8 @@ static void pt_bar_mapping(struct pt_dev *ptdev, int io_enable, int mem_enable) /* check overlapped address */ ret = pt_chk_bar_overlap(dev->bus, dev->devfn, r_addr, r_size); if (ret > 0) - PT_LOG("ptdev[%02x:%02x.%x][Region:%d][Address:%08xh][Size:%08xh] " - "is overlapped.\n", pci_bus_num(dev->bus), + PT_LOG("Warning: ptdev[%02x:%02x.%x][Region:%d][Address:%08xh]" + "[Size:%08xh] is overlapped.\n", pci_bus_num(dev->bus), (dev->devfn >> 3) & 0x1F, (dev->devfn & 0x7), i, r_addr, r_size); @@ -1841,68 +1792,51 @@ int check_power_state(struct pt_dev *ptdev) return 0; } -/* save AER register */ -static void pt_aer_reg_save(struct pt_dev *ptdev) +/* save AER one register */ +static void aer_save_one_register(struct pt_dev *ptdev, int offset) { PCIDevice *d = &ptdev->dev; uint32_t aer_base = ptdev->pm_state->aer_base; - int i = 0; - /* Root Port and Root Complex Event Collector need size expansion */ - int aer_size = 0x2c; -#ifdef PCI_ERR_UNCOR_MASK - for (i=0; i < aer_size; i+=4) - { - switch (i) { - /* after reset, following register values should be restored. - * So, save them. - */ - case PCI_ERR_UNCOR_MASK: - case PCI_ERR_UNCOR_SEVER: - case PCI_ERR_COR_MASK: - case PCI_ERR_CAP: - *(uint32_t*)(d->config + (aer_base + i)) - = pci_read_long(ptdev->pci_dev, (aer_base + i)); - break; - default: - break; - } - } -#endif + *(uint32_t*)(d->config + (aer_base + offset)) + = pci_read_long(ptdev->pci_dev, (aer_base + offset)); } -/* restore AER register */ -static void pt_aer_reg_restore(struct pt_dev *ptdev) +/* save AER registers */ +static void pt_aer_reg_save(struct pt_dev *ptdev) +{ + /* after reset, following register values should be restored. + * So, save them. + */ + aer_save_one_register(ptdev, PCI_ERR_UNCOR_MASK); + aer_save_one_register(ptdev, PCI_ERR_UNCOR_SEVER); + aer_save_one_register(ptdev, PCI_ERR_COR_MASK); + aer_save_one_register(ptdev, PCI_ERR_CAP); +} + +/* restore AER one register */ +static void aer_restore_one_register(struct pt_dev *ptdev, int offset) { PCIDevice *d = &ptdev->dev; uint32_t aer_base = ptdev->pm_state->aer_base; - int i = 0; uint32_t config = 0; - /* Root Port and Root Complex Event Collector need size expansion */ - int aer_size = 0x2c; -#ifdef PCI_ERR_UNCOR_MASK - for (i=0; i < aer_size; i+=4) - { - switch (i) { - /* the following registers should be reconfigured to correct values - * after reset. restore them. - */ - case PCI_ERR_UNCOR_MASK: - case PCI_ERR_UNCOR_SEVER: - case PCI_ERR_COR_MASK: - case PCI_ERR_CAP: - config = *(uint32_t*)(d->config + (aer_base + i)); - pci_write_long(ptdev->pci_dev, (aer_base + i), config); - break; - /* other registers should not be reconfigured after reset - * if there is no reason - */ - default: - break; - } - } -#endif + config = *(uint32_t*)(d->config + (aer_base + offset)); + pci_write_long(ptdev->pci_dev, (aer_base + offset), config); +} + +/* restore AER registers */ +static void pt_aer_reg_restore(struct pt_dev *ptdev) +{ + /* the following registers should be reconfigured to correct values + * after reset. restore them. + * other registers should not be reconfigured after reset + * if there is no reason + */ + aer_restore_one_register(ptdev, PCI_ERR_UNCOR_MASK); + aer_restore_one_register(ptdev, PCI_ERR_UNCOR_SEVER); + aer_restore_one_register(ptdev, PCI_ERR_COR_MASK); + aer_restore_one_register(ptdev, PCI_ERR_CAP); } /* reset Interrupt and I/O resource */ @@ -2115,7 +2049,7 @@ static int pt_config_reg_init(struct pt_dev *ptdev, reg_entry = qemu_mallocz(sizeof(struct pt_reg_tbl)); if (reg_entry == NULL) { - PT_LOG("Failed to allocate memory.\n"); + PT_LOG("Error: Failed to allocate memory.\n"); err = -1; goto out; } @@ -2171,7 +2105,7 @@ static int pt_config_init(struct pt_dev *ptdev) reg_grp_entry = qemu_mallocz(sizeof(struct pt_reg_grp_tbl)); if (reg_grp_entry == NULL) { - PT_LOG("Failed to allocate memory.\n"); + PT_LOG("Error: Failed to allocate memory.\n"); err = -1; goto out; } @@ -2239,10 +2173,10 @@ static void pt_config_delete(struct pt_dev *ptdev) } /* free all register group entry */ - while ((reg_grp_entry = ptdev->reg_grp_tbl_head.lh_first) != NULL) + while((reg_grp_entry = LIST_FIRST(&ptdev->reg_grp_tbl_head)) != NULL) { /* free all register entry */ - while ((reg_entry = reg_grp_entry->reg_tbl_head.lh_first) != NULL) + while((reg_entry = LIST_FIRST(®_grp_entry->reg_tbl_head)) != NULL) { LIST_REMOVE(reg_entry, entries); qemu_free(reg_entry); @@ -2624,7 +2558,7 @@ static uint8_t pt_msi_size_init(struct pt_dev *ptdev, if ( !ptdev->msi ) { /* exit I/O emulator */ - PT_LOG("error allocation pt_msi_info. I/O emulator exit.\n"); + PT_LOG("Error: Allocating pt_msi_info failed. I/O emulator exit.\n"); exit(1); } memset(ptdev->msi, 0, sizeof(struct pt_msi_info)); @@ -2754,8 +2688,7 @@ static int pt_byte_reg_read(struct pt_dev *ptdev, /* emulate byte register */ valid_emu_mask = reg->emu_mask & valid_mask; - *value = ((*value & ~valid_emu_mask) | - (cfg_entry->data & valid_emu_mask)); + *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); return 0; } @@ -2770,8 +2703,7 @@ static int pt_word_reg_read(struct pt_dev *ptdev, /* emulate word register */ valid_emu_mask = reg->emu_mask & valid_mask; - *value = ((*value & ~valid_emu_mask) | - (cfg_entry->data & valid_emu_mask)); + *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); return 0; } @@ -2786,8 +2718,7 @@ static int pt_long_reg_read(struct pt_dev *ptdev, /* emulate long register */ valid_emu_mask = reg->emu_mask & valid_mask; - *value = ((*value & ~valid_emu_mask) | - (cfg_entry->data & valid_emu_mask)); + *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); return 0; } @@ -2833,8 +2764,7 @@ static int pt_bar_reg_read(struct pt_dev *ptdev, /* emulate BAR */ valid_emu_mask = bar_emu_mask & valid_mask; - *value = ((*value & ~valid_emu_mask) | - (cfg_entry->data & valid_emu_mask)); + *value = PT_MERGE_VALUE(*value, cfg_entry->data, ~valid_emu_mask); return 0; } @@ -2850,13 +2780,11 @@ static int pt_byte_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); return 0; } @@ -2872,13 +2800,11 @@ static int pt_word_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); return 0; } @@ -2894,13 +2820,11 @@ static int pt_long_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); return 0; } @@ -2917,12 +2841,11 @@ static int pt_cmd_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* mapping BAR */ pt_bar_mapping(ptdev, wr_value & PCI_COMMAND_IO, @@ -2988,8 +2911,7 @@ static int pt_bar_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* check whether we need to update the virtual region address or not */ switch (ptdev->bases[index].bar_flag) @@ -3007,7 +2929,8 @@ static int pt_bar_reg_write(struct pt_dev *ptdev, if ((last_addr >= 0x10000) && (cfg_entry->data != (PT_BAR_ALLF & ~bar_ro_mask))) { - PT_LOG("Guest attempt to set Base Address over the 64KB. " + PT_LOG("Warning: Guest attempt to set Base Address " + "over the 64KB. " "[%02x:%02x.%x][Offset:%02xh][Address:%08xh][Size:%08xh]\n", pci_bus_num(d->bus), ((d->devfn >> 3) & 0x1F), (d->devfn & 0x7), @@ -3023,7 +2946,7 @@ static int pt_bar_reg_write(struct pt_dev *ptdev, { if (cfg_entry->data != (PT_BAR_ALLF & ~bar_ro_mask)) { - PT_LOG("Guest attempt to set high MMIO Base Address. " + PT_LOG("Warning: Guest attempt to set high MMIO Base Address. " "Ignore mapping. " "[%02x:%02x.%x][Offset:%02xh][High Address:%08xh]\n", pci_bus_num(d->bus), @@ -3066,8 +2989,7 @@ static int pt_bar_reg_write(struct pt_dev *ptdev, exit: /* create value for writing to I/O device register */ throughable_mask = ~bar_emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); return 0; } @@ -3099,16 +3021,14 @@ static int pt_exp_rom_bar_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = bar_emu_mask & ~bar_ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* update the corresponding virtual region address */ r->addr = cfg_entry->data; /* create value for writing to I/O device register */ throughable_mask = ~bar_emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); return 0; } @@ -3122,22 +3042,16 @@ static int pt_pmcsr_reg_write(struct pt_dev *ptdev, PCIDevice *d = &ptdev->dev; uint16_t writable_mask = 0; uint16_t throughable_mask = 0; - uint16_t pmcsr_mask = (PCI_PM_CTRL_PME_ENABLE | - PCI_PM_CTRL_DATA_SEL_MASK | - PCI_PM_CTRL_PME_STATUS); struct pt_pm_info *pm_state = ptdev->pm_state; uint16_t read_val = 0; /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~pmcsr_mask; - - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* set I/O device power state */ pm_state->cur_state = (dev_value & PCI_PM_CTRL_STATE_MASK); @@ -3236,101 +3150,6 @@ static int pt_pmcsr_reg_write(struct pt_dev *ptdev, return 0; } -/* write Device Control register */ -static int pt_devctrl_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask) -{ - struct pt_reg_info_tbl *reg = cfg_entry->reg; - uint16_t writable_mask = 0; - uint16_t throughable_mask = 0; - uint16_t devctrl_mask = (PCI_EXP_DEVCTL_AUX_PME | 0x8000); - - /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~devctrl_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); - - /* create value for writing to I/O device register */ - throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); - - return 0; -} - -/* write Link Control register */ -static int pt_linkctrl_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask) -{ - struct pt_reg_info_tbl *reg = cfg_entry->reg; - uint16_t writable_mask = 0; - uint16_t throughable_mask = 0; - uint16_t linkctrl_mask = (0x04 | PCI_EXP_LNKCTL_DISABLE | - PCI_EXP_LNKCTL_RETRAIN | - 0x0400 | 0x0800 | 0xF000); - - /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~linkctrl_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); - - /* create value for writing to I/O device register */ - throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); - - return 0; -} - -/* write Device Control2 register */ -static int pt_devctrl2_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask) -{ - struct pt_reg_info_tbl *reg = cfg_entry->reg; - uint16_t writable_mask = 0; - uint16_t throughable_mask = 0; - uint16_t devctrl2_mask = 0xFFE0; - - /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & ~devctrl2_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); - - /* create value for writing to I/O device register */ - throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); - - return 0; -} - -/* write Link Control2 register */ -static int pt_linkctrl2_reg_write(struct pt_dev *ptdev, - struct pt_reg_tbl *cfg_entry, - uint16_t *value, uint16_t dev_value, uint16_t valid_mask) -{ - struct pt_reg_info_tbl *reg = cfg_entry->reg; - uint16_t writable_mask = 0; - uint16_t throughable_mask = 0; - uint16_t linkctrl2_mask = (0x0040 | 0xE000); - - /* modify emulate register */ - writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask & - ~linkctrl2_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); - - /* create value for writing to I/O device register */ - throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | - (dev_value & ~throughable_mask)); - - return 0; -} - /* write Message Control register */ static int pt_msgctrl_reg_write(struct pt_dev *ptdev, struct pt_reg_tbl *cfg_entry, @@ -3346,22 +3165,19 @@ static int pt_msgctrl_reg_write(struct pt_dev *ptdev, /* Currently no support for multi-vector */ if ((*value & PCI_MSI_FLAGS_QSIZE) != 0x0) - PT_LOG("try to set more than 1 vector ctrl %x\n", *value); + PT_LOG("Warning: try to set more than 1 vector ctrl %x\n", *value); /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* update the msi_info too */ ptdev->msi->flags |= cfg_entry->data & ~(MSI_FLAG_UNINIT | PT_MSI_MAPPED | PCI_MSI_FLAGS_ENABLE); - PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl, cfg_entry->data); - /* create value for writing to I/O device register */ val = *value; throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* update MSI */ if (val & PCI_MSI_FLAGS_ENABLE) @@ -3420,16 +3236,13 @@ static int pt_msgaddr32_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* update the msi_info too */ ptdev->msi->addr_lo = cfg_entry->data; - PT_LOG("old_addr_lo:%08xh new_addr_lo:%08xh\n", old_addr, cfg_entry->data); - /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* update MSI */ if (cfg_entry->data != old_addr) @@ -3455,22 +3268,19 @@ static int pt_msgaddr64_reg_write(struct pt_dev *ptdev, if (!(ptdev->msi->flags & PCI_MSI_FLAGS_64BIT)) { /* exit I/O emulator */ - PT_LOG("why comes to Upper Address without 64 bit support??\n"); + PT_LOG("Error: why comes to Upper Address without 64 bit support??\n"); return -1; } /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* update the msi_info too */ ptdev->msi->addr_hi = cfg_entry->data; - PT_LOG("old_addr_hi:%08xh new_addr_hi:%08xh\n", old_addr, cfg_entry->data); - /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* update MSI */ if (cfg_entry->data != old_addr) @@ -3506,16 +3316,13 @@ static int pt_msgdata_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); /* update the msi_info too */ ptdev->msi->data = cfg_entry->data; - PT_LOG("old_data:%04xh new_data:%04xh\n", old_data, cfg_entry->data); - /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* update MSI */ if (cfg_entry->data != old_data) @@ -3539,14 +3346,11 @@ static int pt_msixctrl_reg_write(struct pt_dev *ptdev, /* modify emulate register */ writable_mask = reg->emu_mask & ~reg->ro_mask & valid_mask; - cfg_entry->data = ((*value & writable_mask) | - (cfg_entry->data & ~writable_mask)); + cfg_entry->data = PT_MERGE_VALUE(*value, cfg_entry->data, writable_mask); - PT_LOG("old_ctrl:%04xh new_ctrl:%04xh\n", old_ctrl, cfg_entry->data); - /* create value for writing to I/O device register */ throughable_mask = ~reg->emu_mask & valid_mask; - *value = ((*value & throughable_mask) | (dev_value & ~throughable_mask)); + *value = PT_MERGE_VALUE(*value, dev_value, throughable_mask); /* update MSI-X */ if ((*value & PCI_MSIX_ENABLE) && !(*value & PCI_MSIX_MASK)) @@ -3979,7 +3783,7 @@ int pt_init(PCIBus *e_bus, const char *direct_pci) pci_access = pci_alloc(); if ( pci_access == NULL ) { - PT_LOG("pci_access is NULL\n"); + PT_LOG("Error: pci_access is NULL\n"); return -1; } pci_init(pci_access); diff --git a/hw/pass-through.h b/hw/pass-through.h index b44b9d7..2b2dbd2 100644 --- a/hw/pass-through.h +++ b/hw/pass-through.h @@ -86,6 +86,26 @@ #define PCI_EXP_TYPE_ROOT_EC 0xa #endif +#ifndef PCI_ERR_UNCOR_MASK +/* Uncorrectable Error Mask */ +#define PCI_ERR_UNCOR_MASK 8 +#endif + +#ifndef PCI_ERR_UNCOR_SEVER +/* Uncorrectable Error Severity */ +#define PCI_ERR_UNCOR_SEVER 12 +#endif + +#ifndef PCI_ERR_COR_MASK +/* Correctable Error Mask */ +#define PCI_ERR_COR_MASK 20 +#endif + +#ifndef PCI_ERR_CAP +/* Advanced Error Capabilities */ +#define PCI_ERR_CAP 24 +#endif + #ifndef PCI_EXT_CAP_ID /* Extended Capabilities (PCI-X 2.0 and PCI Express) */ #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff) diff --git a/hw/pt-msi.c b/hw/pt-msi.c index bdd1b38..6b0aaa1 100644 --- a/hw/pt-msi.c +++ b/hw/pt-msi.c @@ -68,7 +68,7 @@ int pt_msi_setup(struct pt_dev *dev) if ( !(dev->msi->flags & MSI_FLAG_UNINIT) ) { - PT_LOG("setup physical after initialized?? \n"); + PT_LOG("Error: setup physical after initialized?? \n"); return -1; } @@ -76,13 +76,13 @@ int pt_msi_setup(struct pt_dev *dev) dev->pci_dev->dev << 3 | dev->pci_dev->func, dev->pci_dev->bus, 0, 0) ) { - PT_LOG("error map msi\n"); + PT_LOG("Error: Mapping of MSI failed.\n"); return -1; } if ( pirq < 0 ) { - PT_LOG("invalid pirq number\n"); + PT_LOG("Error: Invalid pirq number\n"); return -1; } @@ -125,7 +125,7 @@ int pt_msi_update(struct pt_dev *d) addr = (uint64_t)d->msi->addr_hi << 32 | d->msi->addr_lo; gflags = __get_msi_gflags(d->msi->data, addr); - PT_LOG("now update msi with pirq %x gvec %x\n", d->msi->pirq, gvec); + PT_LOG("Update msi with pirq %x gvec %x\n", d->msi->pirq, gvec); return xc_domain_update_msi_irq(xc_handle, domid, gvec, d->msi->pirq, gflags); } @@ -295,19 +295,19 @@ static int pt_msix_update_one(struct pt_dev *dev, int entry_nr) dev->msix->table_base); if ( ret ) { - PT_LOG("error map msix entry %x\n", entry_nr); + PT_LOG("Error: Mapping msix entry %x\n", entry_nr); return ret; } entry->pirq = pirq; } - PT_LOG("now update msix entry %x with pirq %x gvec %x\n", + PT_LOG("Update msix entry %x with pirq %x gvec %x\n", entry_nr, pirq, gvec); ret = xc_domain_update_msi_irq(xc_handle, domid, gvec, pirq, gflags); if ( ret ) { - PT_LOG("error update msix irq info for entry %d\n", entry_nr); + PT_LOG("Error: Updating msix irq info for entry %d\n", entry_nr); return ret; } @@ -378,7 +378,7 @@ void pt_msix_disable(struct pt_dev *dev) static void pci_msix_invalid_write(void *opaque, target_phys_addr_t addr, uint32_t val) { - PT_LOG("invalid write to MSI-X table, \ + PT_LOG("Error: Invalid write to MSI-X table, \ only dword access is allowed.\n"); } @@ -391,8 +391,8 @@ static void pci_msix_writel(void *opaque, target_phys_addr_t addr, uint32_t val) if ( addr % 4 ) { - PT_LOG("unaligned dword access to MSI-X table, addr %016"PRIx64"\n", - addr); + PT_LOG("Error: Unaligned dword access to MSI-X table, \ + addr %016"PRIx64"\n", addr); return; } @@ -402,8 +402,8 @@ static void pci_msix_writel(void *opaque, target_phys_addr_t addr, uint32_t val) if ( offset != 3 && msix->enabled && !(entry->io_mem[3] & 0x1) ) { - PT_LOG("can not update msix entry %d since MSI-X is already \ - function now.\n", entry_nr); + PT_LOG("Error: Can''t update msix entry %d since MSI-X is already \ + function.\n", entry_nr); return; } @@ -427,7 +427,7 @@ static CPUWriteMemoryFunc *pci_msix_write[] = { static uint32_t pci_msix_invalid_read(void *opaque, target_phys_addr_t addr) { - PT_LOG("invalid read to MSI-X table, \ + PT_LOG("Error: Invalid read to MSI-X table, \ only dword access is allowed.\n"); return 0; } @@ -440,8 +440,8 @@ static uint32_t pci_msix_readl(void *opaque, target_phys_addr_t addr) if ( addr % 4 ) { - PT_LOG("unaligned dword access to MSI-X table, addr %016"PRIx64"\n", - addr); + PT_LOG("Error: Unaligned dword access to MSI-X table, \ + addr %016"PRIx64"\n", addr); return 0; } @@ -504,7 +504,7 @@ int pt_msix_init(struct pt_dev *dev, int pos) if ( id != PCI_CAP_ID_MSIX ) { - PT_LOG("error id %x pos %x\n", id, pos); + PT_LOG("Error: Invalid id %x pos %x\n", id, pos); return -1; } @@ -516,7 +516,7 @@ int pt_msix_init(struct pt_dev *dev, int pos) + total_entries*sizeof(struct msix_entry_info)); if ( !dev->msix ) { - PT_LOG("error allocation pt_msix_info\n"); + PT_LOG("Error: Allocating pt_msix_info failed.\n"); return -1; } memset(dev->msix, 0, sizeof(struct pt_msix_info) @@ -538,7 +538,7 @@ int pt_msix_init(struct pt_dev *dev, int pos) fd = open("/dev/mem", O_RDWR); if ( fd == -1 ) { - PT_LOG("Can''t open /dev/mem: %s\n", strerror(errno)); + PT_LOG("Error: Can''t open /dev/mem: %s\n", strerror(errno)); goto error_out; } dev->msix->phys_iomem_base = mmap(0, total_entries * 16, @@ -546,7 +546,7 @@ int pt_msix_init(struct pt_dev *dev, int pos) fd, dev->msix->table_base + table_off); if ( dev->msix->phys_iomem_base == MAP_FAILED ) { - PT_LOG("Can''t map physical MSI-X table: %s\n", strerror(errno)); + PT_LOG("Error: Can''t map physical MSI-X table: %s\n", strerror(errno)); close(fd); goto error_out; } _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Simon Horman
2009-Feb-23 05:56 UTC
Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.
On Mon, Feb 23, 2009 at 10:40:22AM +0900, Yuji Shimada wrote:> > The patch cleanups the code of PCI passthrough. > > - Use LIST_FOREACH(). Don''t use lh_first, le_next directly. > - Use pci_{read, write}_block instead of "switch(len) case [124] > pci_{read, write}_{byte, word, long}();". > - Eliminate duplicate codes using PT_MEARGE_VALUE macro. > - Define PCI_ERR_* macro in pass-through.h if libpci is old. > - Remove the unreasonable loop from pt_aer_reg_{save,restore}. > - Enable pt_aer_reg_{save,restore}, even if libpci is old. > - Fix ro_mask and remove unnecessary pt_xxx_reg_write functions. > - Add "Error:" or "Warning:" to messages. > - Remove verbose messages. > > Thanks, > -- > Yuji Shimada. > > > Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp>Tested-by: Simon Horman <horms@verge.net.au> -- Simon Horman VA Linux Systems Japan K.K., Sydney, Australia Satellite Office H: www.vergenet.net/~horms/ W: www.valinux.co.jp/en _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Ian Jackson
2009-Feb-23 11:36 UTC
Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.
Simon Horman writes ("Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code
of PCI passthrough."):> On Mon, Feb 23, 2009 at 10:40:22AM +0900, Yuji Shimada wrote:
> > Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp>
>
> Tested-by: Simon Horman <horms@verge.net.au>
Thanks, I have applied this.
The problem causing it to be rejected was that hw/passthrough.[ch] and
hw/pt-msi.[ch] were full of trailing whitespace, which Yuji Shimada''s
mailer evidently removes. I think the mailer was right and the code
was wrong.
So I have removed all of that trailing whitespace with a trivial perl
one-liner and then committed the cleanup patch on top. I haven''t
tested the pass-through but the tree does build.
Ian.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
Boris Derzhavets
2009-Feb-23 14:23 UTC
Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.
I was under impression, that mentioned patch is supposed to support
loading HVM DomU (?). If answer is "yes" , then my question:-
When http://xenbits.xensource.com/xen-unstable.hg will get this update?
Looks like "make tools" is using
http://xenbits.xensource.com/git-http/qemu-xen-unstable.git when building
xen-unstable.hg/tools/ioemu-remote.
If answer is "no", i am sorry for misunderstanding.
Fresh Xen-Unstable Dom0 install (along with the most recent build
2.6.29-rc5) still shows during attempt to start HVM DomU:-
# xm dmesg
. . . . . .
(XEN) HVM1: HVM Loader
(XEN) HVM1: Detected Xen v3.4-unstable
(XEN) HVM1: CPU speed is 3006 MHz
(XEN) irq.c:235: Dom1 PCI link 0 changed 0 -> 5
(XEN) HVM1: PCI-ISA link 0 routed to IRQ5
(XEN) irq.c:235: Dom1 PCI link 1 changed 0 -> 10
(XEN) HVM1: PCI-ISA link 1 routed to IRQ10
(XEN) irq.c:235: Dom1 PCI link 2 changed 0 -> 11
(XEN) HVM1: PCI-ISA link 2 routed to IRQ11
(XEN) irq.c:235: Dom1 PCI link 3 changed 0 -> 5
(XEN) HVM1: PCI-ISA link 3 routed to IRQ5
(XEN) HVM1: pci dev 01:2 INTD->IRQ5
(XEN) HVM1: pci dev 01:3 INTA->IRQ10
(XEN) HVM1: pci dev 03:0 INTA->IRQ5
(XEN) HVM1: pci dev 04:0 INTA->IRQ5
(XEN) HVM1: pci dev 02:0 bar 10 size 02000000: f0000008
(XEN) HVM1: pci dev 03:0 bar 14 size 01000000: f2000008
(XEN) HVM1: pci dev 02:0 bar 14 size 00001000: f3000000
(XEN) HVM1: pci dev 03:0 bar 10 size 00000100: 0000c001
(XEN) HVM1: pci dev 04:0 bar 10 size 00000100: 0000c101
(XEN) HVM1: pci dev 04:0 bar 14 size 00000100: f3001000
(XEN) HVM1: pci dev 01:2 bar 20 size 00000020: 0000c201
(XEN) HVM1: pci dev 01:1 bar 20 size 00000010: 0000c221
(XEN) HVM1: Multiprocessor initialisation:
(XEN) HVM1: - CPU0 ... 36-bit phys ... fixed MTRRs ... var MTRRs [2/8] ...
done.
(XEN) HVM1: Testing HVM environment:
(XEN) HVM1: - REP INSB across page boundaries ... passed
(XEN) HVM1: Passed 1/1 tests
(XEN) HVM1: Writing SMBIOS tables ...
(XEN) HVM1: Loading ROMBIOS ...
(XEN) HVM1: 9788 bytes of ROMBIOS high-memory extensions:
(XEN) HVM1: Relocating to 0xfc000000-0xfc00263c ... done
(XEN) HVM1: Creating MP tables ...
(XEN) HVM1: Loading Cirrus VGABIOS ...
(XEN) HVM1: Loading PCI Option ROM ...
(XEN) HVM1: - Manufacturer: http://etherboot.org
(XEN) HVM1: - Product name: gPXE
(XEN) HVM1: Loading ACPI ...
********************************
Logfile under /var/log/xen :-
********************************
domid: 1
qemu: the number of cpus is 1
config qemu network with xen bridge for tap1.0 eth0
Watching /local/domain/0/device-model/1/logdirty/next-active
Watching /local/domain/0/device-model/1/command
xs_read(): vncpasswd get error.
/vm/1388b5b0-3888-5c75-b701-3e82249a379e/vncpasswd.
qemu_map_cache_init nr_buckets = 10000 size 3145728
shared page at pfn feffd
buffered io page at pfn feffb
Guest uuid = 1388b5b0-3888-5c75-b701-3e82249a379e
Time offset set 0
populating video RAM at ff000000
mapping video RAM from ff000000
Register xen platform.
Done register platform.
xs_read(/local/domain/0/device-model/1/xen_extended_power_mgmt): read error
medium change watch on `hdc'' (index: 0): /dev/loop0
I/O request not ready: 0, ptr: 0, port: 0, data: 0, count: 0, size: 0
cirrus vga map change while on lfb mode
--- On Mon, 2/23/09, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote:
From: Ian Jackson <Ian.Jackson@eu.citrix.com>
Subject: Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.
To: "Simon Horman" <horms@verge.net.au>
Cc: "Yuji Shimada" <shimada-yxb@necst.nec.co.jp>,
"xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>
Date: Monday, February 23, 2009, 6:36 AM
Simon Horman writes ("Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code
of PCI passthrough."):> On Mon, Feb 23, 2009 at 10:40:22AM +0900, Yuji Shimada wrote:
> > Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp>
>
> Tested-by: Simon Horman <horms@verge.net.au>
Thanks, I have applied this.
The problem causing it to be rejected was that hw/passthrough.[ch] and
hw/pt-msi.[ch] were full of trailing whitespace, which Yuji Shimada''s
mailer evidently removes. I think the mailer was right and the code
was wrong.
So I have removed all of that trailing whitespace with a trivial perl
one-liner and then committed the cleanup patch on top. I haven''t
tested the pass-through but the tree does build.
Ian.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
Ian Jackson
2009-Feb-23 14:53 UTC
Re: [Xen-devel] HVM guest question (was Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.)
Boris Derzhavets writes ("Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the
code of PCI passthrough."):> I was under impression, that mentioned patch is supposed to support
> loading HVM DomU (?).
No, it''s just code cleanup for PCI passthrough, which is for passing
PCI devices through to guests. If you are not doing PCI passthrough -
ie, most ordinary HVM guests - then these changes will not affect you.
> If answer is "yes" , then my question:-
> When http://xenbits.xensource.com/xen-unstable.hg will get this update?
In this case, just now. All changes that we make to xen-unstable,
including the qemu-xen-unstable subsidiary tree, go through an
automated build-and-test. Only versions which pass the (fairly
rudimentary) tests make it through to the main trees.
The pre-testing trees (called `staging'') are also available and
published but not the `usual'' case.
> Looks like "make tools" is using
> http://xenbits.xensource.com/git-http/qemu-xen-unstable.git when
> building xen-unstable.hg/tools/ioemu-remote.
Yes. You can change this by setting the CONFIG_QEMU make variable, eg
in a file `.config'' in the xen-unstable.hg top level.
> If answer is "no", i am sorry for misunderstanding.
>
> Fresh Xen-Unstable Dom0 install (along with the most recent build
> 2.6.29-rc5) still shows during attempt to start HVM DomU:-
These messages are not very surprising. Is it working ?
Ian.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
Andrew Lyon
2009-Feb-23 15:04 UTC
Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.
On Mon, Feb 23, 2009 at 2:23 PM, Boris Derzhavets <bderzhavets@yahoo.com> wrote:> I was under impression, that mentioned patch is supposed to support > loading HVM DomU (?). If answer is "yes" , then my question:- > When http://xenbits.xensource.com/xen-unstable.hg will get this update? > Looks like "make tools" is using > http://xenbits.xensource.com/git-http/qemu-xen-unstable.git when building > xen-unstable.hg/tools/ioemu-remote. > If answer is "no", i am sorry for misunderstanding. > > Fresh Xen-Unstable Dom0 install (along with the most recent build > 2.6.29-rc5) still shows during attempt to start HVM DomU:- > > # xm dmesg > . . . . . . > (XEN) HVM1: HVM Loader > (XEN) HVM1: Detected Xen v3.4-unstable > (XEN) HVM1: CPU speed is 3006 MHz > (XEN) irq.c:235: Dom1 PCI link 0 changed 0 -> 5 > (XEN) HVM1: PCI-ISA link 0 routed to IRQ5 > (XEN) irq.c:235: Dom1 PCI link 1 changed 0 -> 10 > (XEN) HVM1: PCI-ISA link 1 routed to IRQ10 > (XEN) irq.c:235: Dom1 PCI link 2 changed 0 -> 11 > (XEN) HVM1: PCI-ISA link 2 routed to IRQ11 > (XEN) irq.c:235: Dom1 PCI link 3 changed 0 -> 5 > (XEN) HVM1: PCI-ISA link 3 routed to IRQ5 > (XEN) HVM1: pci dev 01:2 INTD->IRQ5 > (XEN) HVM1: pci dev 01:3 INTA->IRQ10 > (XEN) HVM1: pci dev 03:0 INTA->IRQ5 > (XEN) HVM1: pci dev 04:0 INTA->IRQ5 > (XEN) HVM1: pci dev 02:0 bar 10 size 02000000: f0000008 > (XEN) HVM1: pci dev 03:0 bar 14 size 01000000: f2000008 > (XEN) HVM1: pci dev 02:0 bar 14 size 00001000: f3000000 > (XEN) HVM1: pci dev 03:0 bar 10 size 00000100: 0000c001 > (XEN) HVM1: pci dev 04:0 bar 10 size 00000100: 0000c101 > (XEN) HVM1: pci dev 04:0 bar 14 size 00000100: f3001000 > (XEN) HVM1: pci dev 01:2 bar 20 size 00000020: 0000c201 > (XEN) HVM1: pci dev 01:1 bar 20 size 00000010: 0000c221 > (XEN) HVM1: Multiprocessor initialisation: > (XEN) HVM1: - CPU0 ... 36-bit phys ... fixed MTRRs ... var MTRRs [2/8] ... > done. > (XEN) HVM1: Testing HVM environment: > (XEN) HVM1: - REP INSB across page boundaries ... passed > (XEN) HVM1: Passed 1/1 tests > (XEN) HVM1: Writing SMBIOS tables ... > (XEN) HVM1: Loading ROMBIOS ... > (XEN) HVM1: 9788 bytes of ROMBIOS high-memory extensions: > (XEN) HVM1: Relocating to 0xfc000000-0xfc00263c ... done > (XEN) HVM1: Creating MP tables ... > (XEN) HVM1: Loading Cirrus VGABIOS ... > (XEN) HVM1: Loading PCI Option ROM ... > (XEN) HVM1: - Manufacturer: http://etherboot.org > (XEN) HVM1: - Product name: gPXE > (XEN) HVM1: Loading ACPI ... > > > ******************************** > Logfile under /var/log/xen :- > ******************************** > > domid: 1 > qemu: the number of cpus is 1 > config qemu network with xen bridge for tap1.0 eth0 > Watching /local/domain/0/device-model/1/logdirty/next-active > Watching /local/domain/0/device-model/1/command > xs_read(): vncpasswd get error. > /vm/1388b5b0-3888-5c75-b701-3e82249a379e/vncpasswd. > qemu_map_cache_init nr_buckets = 10000 size 3145728 > shared page at pfn feffd > buffered io page at pfn feffb > Guest uuid = 1388b5b0-3888-5c75-b701-3e82249a379e > Time offset set 0 > populating video RAM at ff000000 > mapping video RAM from ff000000 > Register xen platform. > Done register platform. > xs_read(/local/domain/0/device-model/1/xen_extended_power_mgmt): read error > medium change watch on `hdc'' (index: 0): /dev/loop0 > I/O request not ready: 0, ptr: 0, port: 0, data: 0, count: 0, size: 0 > cirrus vga map change while on lfb mode > > > > > --- On Mon, 2/23/09, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote: > > From: Ian Jackson <Ian.Jackson@eu.citrix.com> > Subject: Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI > passthrough. > To: "Simon Horman" <horms@verge.net.au> > Cc: "Yuji Shimada" <shimada-yxb@necst.nec.co.jp>, > "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com> > Date: Monday, February 23, 2009, 6:36 AM > > Simon Horman writes ("Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code > of PCI passthrough."): >> On Mon, Feb 23, 2009 at 10:40:22AM +0900, Yuji Shimada wrote: >> > Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp> >> >> Tested-by: Simon Horman <horms@verge.net.au> > > Thanks, I have applied this. > > The problem causing it to be rejected was that hw/passthrough.[ch] and > hw/pt-msi.[ch] were full of trailing whitespace, which Yuji Shimada''s > mailer evidently removes. I think > the mailer was right and the code > was wrong. > > So I have removed all of that trailing whitespace with a trivial perl > one-liner and then committed the cleanup patch on top. I haven''t > tested the pass-through but the tree does build. > > Ian. > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel > > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel > >Boris, There is another problem as well as the "pci power management" issue that the patch fixes, with Xen unstable and the patch applied I can start hvm''s if I use a normal Xen kernel, but if I use the pv_ops kernel I get the sentinel message in xen log: [2009-02-22 14:01:53 3467] WARNING (image:470) domain xptest: device model failure: pid 3735: malfunctioning (closed sentinel), killed; see /var/log/xen/qemu-dm-xptest.log I''ve posted the qemu-dm log before, I dont think this line "I/O request not ready: 0, ptr: 0, port: 0, data: 0, count: 0, size: 0" is about the problem because it is also logged when I use a non pv_ops kernel and hvm works ok. Andy _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Andrew Lyon
2009-Feb-23 15:09 UTC
Re: [Xen-devel] HVM guest question (was Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.)
On Mon, Feb 23, 2009 at 2:53 PM, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote:> Boris Derzhavets writes ("Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough."): >> I was under impression, that mentioned patch is supposed to support >> loading HVM DomU (?). > > No, it''s just code cleanup for PCI passthrough, which is for passing > PCI devices through to guests. If you are not doing PCI passthrough - > ie, most ordinary HVM guests - then these changes will not affect you. > >> If answer is "yes" , then my question:- >> When http://xenbits.xensource.com/xen-unstable.hg will get this update? > > In this case, just now. All changes that we make to xen-unstable, > including the qemu-xen-unstable subsidiary tree, go through an > automated build-and-test. Only versions which pass the (fairly > rudimentary) tests make it through to the main trees. > > The pre-testing trees (called `staging'') are also available and > published but not the `usual'' case. > >> Looks like "make tools" is using >> http://xenbits.xensource.com/git-http/qemu-xen-unstable.git when >> building xen-unstable.hg/tools/ioemu-remote. > > Yes. You can change this by setting the CONFIG_QEMU make variable, eg > in a file `.config'' in the xen-unstable.hg top level. > >> If answer is "no", i am sorry for misunderstanding. >> >> Fresh Xen-Unstable Dom0 install (along with the most recent build >> 2.6.29-rc5) still shows during attempt to start HVM DomU:- > > These messages are not very surprising. Is it working ?No, when try to start HVM on Xen unstable with pv_ops kernel I get this error: [2009-02-22 14:01:53 3467] WARNING (image:470) domain xptest: device model failure: pid 3735: malfunctioning (closed sentinel), killed; see /var/log/xen/qemu-dm-xptest.log cat /var/log/xen/qemu-dm-xptest.log domid: 4 qemu: the number of cpus is 1 Using xvda for guest''s hda Strip off blktap sub-type prefix to /root/xp (drv ''aio'') Watching /local/domain/0/device-model/4/logdirty/next-active Watching /local/domain/0/device-model/4/command qemu_map_cache_init nr_buckets = 10000 size 3145728 shared page at pfn 1fffe buffered io page at pfn 1fffc Time offset set 0 Register xen platform. Done register platform. I/O request not ready: 0, ptr: 0, port: 0, data: 0, count: 0, size: 0 If I change the kernel to normal Xen kernel (not pv_ops) it works ok. What can I do to debug? Andy> > Ian. > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel >_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Boris Derzhavets
2009-Feb-23 15:36 UTC
Re: [Xen-devel] HVM guest question (was Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.)
>In this case, just now. All changes that we make to xen-unstable, >including the qemu-xen-unstable subsidiary tree, go through an >automated build-and-test.I''ve cloned xen-unstable about 1.5 hr ago , by some reasons changes had not been applied to /usr/src/xen-unstable.hg/tools/ioemu-remote/hw/pass-through.c .> Is it working ?PV DomUs for F10,SNV_106,Interpid Server (via debootstrap), OpenSuse 11.1 may be installed ( via remote VNC connection, even utilizing vfb ) and work pretty stable at Xen Unstable Dom0 ( kernel 2.6.29-rc5 ). HVM DomUs failed at startup . Nothing listen at localhost:5900. --- On Mon, 2/23/09, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote: From: Ian Jackson <Ian.Jackson@eu.citrix.com> Subject: Re: [Xen-devel] HVM guest question (was Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.) To: "bderzhavets@yahoo.com" <bderzhavets@yahoo.com> Cc: "Simon Horman" <horms@verge.net.au>, "Yuji Shimada" <shimada-yxb@necst.nec.co.jp>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com> Date: Monday, February 23, 2009, 9:53 AM Boris Derzhavets writes ("Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough."):> I was under impression, that mentioned patch is supposed to support > loading HVM DomU (?).No, it''s just code cleanup for PCI passthrough, which is for passing PCI devices through to guests. If you are not doing PCI passthrough - ie, most ordinary HVM guests - then these changes will not affect you.> If answer is "yes" , then my question:- > When http://xenbits.xensource.com/xen-unstable.hg will get this update?In this case, just now. All changes that we make to xen-unstable, including the qemu-xen-unstable subsidiary tree, go through an automated build-and-test. Only versions which pass the (fairly rudimentary) tests make it through to the main trees. The pre-testing trees (called `staging'') are also available and published but not the `usual'' case.> Looks like "make tools" is using > http://xenbits.xensource.com/git-http/qemu-xen-unstable.git when > building xen-unstable.hg/tools/ioemu-remote.Yes. You can change this by setting the CONFIG_QEMU make variable, eg in a file `.config'' in the xen-unstable.hg top level.> If answer is "no", i am sorry for misunderstanding. > > Fresh Xen-Unstable Dom0 install (along with the most recent build > 2.6.29-rc5) still shows during attempt to start HVM DomU:-These messages are not very surprising. Is it working ? Ian. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Andrew Lyon writes ("Re: [Xen-devel] HVM guest question (was Re: [PATCH]
ioemu: Cleanup the code of PCI passthrough.)"):> On Mon, Feb 23, 2009 at 2:53 PM, Ian Jackson
<Ian.Jackson@eu.citrix.com> wrote:
> > These messages are not very surprising. Is it working ?
>
> No, when try to start HVM on Xen unstable with pv_ops kernel I get this
error:
Ah. This is rather odd. Normally I would hope that xend would report
an exit status. (I haven''t tried pvops with qemu.)
I would suggest running qemu-dm under strace. This can be done easily
enough with a simple wrapper script, something like:
#!/bin/sh
set -e
exec strace -vvs500 -f -o /root/qemu-dm.strace \
/usr/lib/xen/bin/qemu-dm "$@"
and then give the name of the script as device_model in your config file.
Ian.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
Ian Jackson
2009-Feb-23 16:22 UTC
Re: [Xen-devel] HVM guest question (was Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.)
Boris Derzhavets writes ("Re: [Xen-devel] HVM guest question (was Re:
[PATCH] ioemu: Cleanup the code of PCI
passthrough.)"):> [Ian Jackson:]
> > Is it working ?
...> HVM DomUs failed at startup . Nothing listen at localhost:5900.
Is this with dom0 pvops ? Or something else ? Could you post your
config file ?
Unless you''re actually using pci passthrough the changes to
hw/pass-through.[ch] are irrelevant to you.
Thanks,
Ian.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
Andrew Lyon
2009-Feb-23 17:08 UTC
Re: [Xen-devel] HVM guest question (was Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.)
On Mon, Feb 23, 2009 at 4:22 PM, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote:> Boris Derzhavets writes ("Re: [Xen-devel] HVM guest question (was Re: > [PATCH] ioemu: Cleanup the code of PCI passthrough.)"): >> [Ian Jackson:] >> > Is it working ? > ... >> HVM DomUs failed at startup . Nothing listen at localhost:5900. > > Is this with dom0 pvops ? Or something else ? Could you post your > config file ?I have the same problem as Boris, its very easy to replicate, just try to start a hvm while running a recent pv_ops kernel in dom0 with Xen 3.2.1 + backported pv_ops patches or Xen 3.4 unstable. Last few lines of "xm log" [2009-02-23 17:02:22 3524] DEBUG (DevController:144) Waiting for 0. [2009-02-23 17:02:22 3524] DEBUG (DevController:139) Waiting for devices pci. [2009-02-23 17:02:22 3524] DEBUG (DevController:139) Waiting for devices ioports. [2009-02-23 17:02:22 3524] DEBUG (DevController:139) Waiting for devices tap. [2009-02-23 17:02:22 3524] DEBUG (DevController:139) Waiting for devices vtpm. [2009-02-23 17:02:22 3524] INFO (XendDomain:1180) Domain xptest (2) unpaused. [2009-02-23 17:02:22 3524] WARNING (image:482) domain xptest: device model failure: pid 4028: malfunctioning (closed sentinel), killed; see /var/log/xen/qemu-dm-xptest.log u start the hvm qemu-dm fails: localhost xen # cat /var/log/xen/qemu-dm-xptest.log domid: 2 qemu: the number of cpus is 2 config qemu network with xen bridge for tap2.0 xenbr0 Watching /local/domain/0/device-model/2/logdirty/next-active Watching /local/domain/0/device-model/2/command char device redirected to /dev/pts/1 qemu_map_cache_init nr_buckets = 10000 size 3145728 shared page at pfn feffd buffered io page at pfn feffb Guest uuid = 46f22c82-8a3d-47e3-b9c5-3b5f6eaf7a12 Time offset set 0 populating video RAM at ff000000 mapping video RAM from ff000000 Register xen platform. Done register platform. xs_read(/local/domain/0/device-model/2/xen_extended_power_mgmt): read error medium change watch on `hdc'' (index: 1): /mnt/jos-tb1_store/CD Images/Other/EN Win_XP_Pro_w_SP2/en_winxp_pro_with_sp2.iso I/O request not ready: 0, ptr: 0, port: 0, data: 0, count: 0, size: 0 I/O request not ready: 0, ptr: 0, port: 0, data: 0, count: 0, size: 0 cirrus vga map change while on lfb mode localhost xen # xm info: host : localhost release : 2.6.29-rc5-tip version : #2 SMP Sun Feb 22 13:27:49 GMT 2009 machine : x86_64 nr_cpus : 2 nr_nodes : 1 cores_per_socket : 2 threads_per_core : 1 cpu_mhz : 2394 hw_caps : bfebfbff:20100800:00000000:00000140:0000e3bd:00000000:0 0000001:00000000 virt_caps : hvm hvm_directio total_memory : 3965 free_memory : 131 node_to_cpu : node0:0-1 node_to_memory : node0:131 xen_major : 3 xen_minor : 4 xen_extra : -unstable xen_caps : xen-3.0-x86_64 xen-3.0-x86_32p hvm-3.0-x86_32 hvm-3.0-x 86_32p hvm-3.0-x86_64 xen_scheduler : credit xen_pagesize : 4096 platform_params : virt_start=0xffff800000000000 xen_changeset : unavailable cc_compiler : gcc version 4.1.2 (Gentoo 4.1.2 p1.0.2) cc_compile_by : root cc_compile_domain : cc_compile_date : Mon Feb 23 10:37:49 GMT 2009 xend_config_format : 4 kernel config: # # Automatically generated make config: don''t edit # Linux kernel version: 2.6.29-rc5 # Fri Feb 20 10:40:57 2009 # CONFIG_64BIT=y # CONFIG_X86_32 is not set CONFIG_X86_64=y CONFIG_X86=y CONFIG_ARCH_DEFCONFIG="arch/x86/configs/x86_64_defconfig" CONFIG_GENERIC_TIME=y CONFIG_GENERIC_CMOS_UPDATE=y CONFIG_CLOCKSOURCE_WATCHDOG=y CONFIG_GENERIC_CLOCKEVENTS=y CONFIG_GENERIC_CLOCKEVENTS_BROADCAST=y CONFIG_LOCKDEP_SUPPORT=y CONFIG_STACKTRACE_SUPPORT=y CONFIG_HAVE_LATENCYTOP_SUPPORT=y CONFIG_FAST_CMPXCHG_LOCAL=y CONFIG_MMU=y CONFIG_ZONE_DMA=y CONFIG_GENERIC_ISA_DMA=y CONFIG_GENERIC_IOMAP=y CONFIG_GENERIC_BUG=y CONFIG_GENERIC_BUG_RELATIVE_POINTERS=y CONFIG_GENERIC_HWEIGHT=y CONFIG_ARCH_MAY_HAVE_PC_FDC=y CONFIG_RWSEM_GENERIC_SPINLOCK=y # CONFIG_RWSEM_XCHGADD_ALGORITHM is not set CONFIG_ARCH_HAS_CPU_IDLE_WAIT=y CONFIG_GENERIC_CALIBRATE_DELAY=y CONFIG_GENERIC_TIME_VSYSCALL=y CONFIG_ARCH_HAS_CPU_RELAX=y CONFIG_ARCH_HAS_DEFAULT_IDLE=y CONFIG_ARCH_HAS_CACHE_LINE_SIZE=y CONFIG_HAVE_SETUP_PER_CPU_AREA=y CONFIG_HAVE_CPUMASK_OF_CPU_MAP=y CONFIG_ARCH_HIBERNATION_POSSIBLE=y CONFIG_ARCH_SUSPEND_POSSIBLE=y CONFIG_ZONE_DMA32=y CONFIG_ARCH_POPULATES_NODE_MAP=y CONFIG_AUDIT_ARCH=y CONFIG_ARCH_SUPPORTS_OPTIMIZED_INLINING=y CONFIG_GENERIC_HARDIRQS=y CONFIG_GENERIC_IRQ_PROBE=y CONFIG_GENERIC_PENDING_IRQ=y CONFIG_USE_GENERIC_SMP_HELPERS=y CONFIG_X86_64_SMP=y CONFIG_X86_HT=y CONFIG_X86_TRAMPOLINE=y # CONFIG_KTIME_SCALAR is not set CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config" # # General setup # CONFIG_EXPERIMENTAL=y CONFIG_LOCK_KERNEL=y CONFIG_INIT_ENV_ARG_LIMIT=32 CONFIG_LOCALVERSION="" # CONFIG_LOCALVERSION_AUTO is not set CONFIG_SWAP=y CONFIG_SYSVIPC=y CONFIG_SYSVIPC_SYSCTL=y CONFIG_POSIX_MQUEUE=y CONFIG_BSD_PROCESS_ACCT=y # CONFIG_BSD_PROCESS_ACCT_V3 is not set CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y CONFIG_AUDIT=y CONFIG_AUDITSYSCALL=y CONFIG_AUDIT_TREE=y # # RCU Subsystem # CONFIG_CLASSIC_RCU=y # CONFIG_TREE_RCU is not set # CONFIG_PREEMPT_RCU is not set # CONFIG_TREE_RCU_TRACE is not set # CONFIG_PREEMPT_RCU_TRACE is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=17 CONFIG_HAVE_UNSTABLE_SCHED_CLOCK=y # CONFIG_GROUP_SCHED is not set # CONFIG_CGROUPS is not set # CONFIG_SYSFS_DEPRECATED_V2 is not set CONFIG_RELAY=y CONFIG_NAMESPACES=y CONFIG_UTS_NS=y CONFIG_IPC_NS=y CONFIG_USER_NS=y CONFIG_PID_NS=y # CONFIG_NET_NS is not set CONFIG_BLK_DEV_INITRD=y CONFIG_INITRAMFS_SOURCE="" CONFIG_CC_OPTIMIZE_FOR_SIZE=y CONFIG_SYSCTL=y # CONFIG_EMBEDDED is not set CONFIG_UID16=y CONFIG_SYSCTL_SYSCALL=y CONFIG_KALLSYMS=y CONFIG_KALLSYMS_ALL=y CONFIG_KALLSYMS_EXTRA_PASS=y CONFIG_HOTPLUG=y CONFIG_PRINTK=y CONFIG_BUG=y CONFIG_ELF_CORE=y CONFIG_PCSPKR_PLATFORM=y # CONFIG_COMPAT_BRK is not set CONFIG_BASE_FULL=y CONFIG_FUTEX=y CONFIG_ANON_INODES=y CONFIG_EPOLL=y CONFIG_SIGNALFD=y CONFIG_TIMERFD=y CONFIG_EVENTFD=y CONFIG_SHMEM=y CONFIG_AIO=y CONFIG_HAVE_PERF_COUNTERS=y # # Performance Counters # CONFIG_PERF_COUNTERS=y CONFIG_VM_EVENT_COUNTERS=y CONFIG_PCI_QUIRKS=y CONFIG_SLUB_DEBUG=y # CONFIG_SLAB is not set CONFIG_SLUB=y # CONFIG_SLOB is not set # CONFIG_PROFILING is not set CONFIG_TRACEPOINTS=y CONFIG_MARKERS=y CONFIG_HAVE_OPROFILE=y CONFIG_KPROBES=y CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS=y CONFIG_KRETPROBES=y CONFIG_HAVE_IOREMAP_PROT=y CONFIG_HAVE_KPROBES=y CONFIG_HAVE_KRETPROBES=y CONFIG_HAVE_ARCH_TRACEHOOK=y # CONFIG_HAVE_GENERIC_DMA_COHERENT is not set CONFIG_SLABINFO=y CONFIG_RT_MUTEXES=y CONFIG_BASE_SMALL=0 CONFIG_MODULES=y # CONFIG_MODULE_FORCE_LOAD is not set CONFIG_MODULE_UNLOAD=y CONFIG_MODULE_FORCE_UNLOAD=y # CONFIG_MODVERSIONS is not set # CONFIG_MODULE_SRCVERSION_ALL is not set CONFIG_STOP_MACHINE=y CONFIG_BLOCK=y CONFIG_BLK_DEV_BSG=y # CONFIG_BLK_DEV_INTEGRITY is not set CONFIG_BLOCK_COMPAT=y # # IO Schedulers # CONFIG_IOSCHED_NOOP=y CONFIG_IOSCHED_AS=y CONFIG_IOSCHED_DEADLINE=y CONFIG_IOSCHED_CFQ=y # CONFIG_DEFAULT_AS is not set # CONFIG_DEFAULT_DEADLINE is not set CONFIG_DEFAULT_CFQ=y # CONFIG_DEFAULT_NOOP is not set CONFIG_DEFAULT_IOSCHED="cfq" CONFIG_FREEZER=y # # Processor type and features # # CONFIG_NO_HZ is not set # CONFIG_HIGH_RES_TIMERS is not set CONFIG_GENERIC_CLOCKEVENTS_BUILD=y CONFIG_SMP=y # CONFIG_X86_X2APIC is not set # CONFIG_SPARSE_IRQ is not set CONFIG_X86_MPPARSE=y CONFIG_X86_EXTENDED_PLATFORM=y # CONFIG_X86_VSMP is not set # CONFIG_X86_UV is not set CONFIG_SCHED_OMIT_FRAME_POINTER=y CONFIG_PARAVIRT_GUEST=y CONFIG_XEN=y CONFIG_XEN_MAX_DOMAIN_MEMORY=32 CONFIG_XEN_SAVE_RESTORE=y # CONFIG_XEN_DEBUG_FS is not set CONFIG_XEN_DOM0=y CONFIG_XEN_PRIVILEGED_GUEST=y CONFIG_XEN_DOM0_PCI=y # CONFIG_KVM_CLOCK is not set # CONFIG_KVM_GUEST is not set CONFIG_PARAVIRT=y CONFIG_PARAVIRT_CLOCK=y # CONFIG_PARAVIRT_DEBUG is not set # CONFIG_MEMTEST is not set # CONFIG_M386 is not set # CONFIG_M486 is not set # CONFIG_M586 is not set # CONFIG_M586TSC is not set # CONFIG_M586MMX is not set # CONFIG_M686 is not set # CONFIG_MPENTIUMII is not set # CONFIG_MPENTIUMIII is not set # CONFIG_MPENTIUMM is not set # CONFIG_MPENTIUM4 is not set # CONFIG_MK6 is not set # CONFIG_MK7 is not set # CONFIG_MK8 is not set # CONFIG_MCRUSOE is not set # CONFIG_MEFFICEON is not set # CONFIG_MWINCHIPC6 is not set # CONFIG_MWINCHIP3D is not set # CONFIG_MGEODEGX1 is not set # CONFIG_MGEODE_LX is not set # CONFIG_MCYRIXIII is not set # CONFIG_MVIAC3_2 is not set # CONFIG_MVIAC7 is not set # CONFIG_MPSC is not set CONFIG_MCORE2=y # CONFIG_GENERIC_CPU is not set CONFIG_X86_CPU=y CONFIG_X86_L1_CACHE_BYTES=64 CONFIG_X86_INTERNODE_CACHE_BYTES=64 CONFIG_X86_CMPXCHG=y CONFIG_X86_L1_CACHE_SHIFT=6 CONFIG_X86_WP_WORKS_OK=y CONFIG_X86_INTEL_USERCOPY=y CONFIG_X86_USE_PPRO_CHECKSUM=y CONFIG_X86_P6_NOP=y CONFIG_X86_TSC=y CONFIG_X86_CMPXCHG64=y CONFIG_X86_CMOV=y CONFIG_X86_MINIMUM_CPU_FAMILY=64 CONFIG_X86_DEBUGCTLMSR=y CONFIG_CPU_SUP_INTEL=y CONFIG_CPU_SUP_AMD=y CONFIG_CPU_SUP_CENTAUR_64=y CONFIG_X86_DS=y CONFIG_X86_PTRACE_BTS=y CONFIG_HPET_TIMER=y CONFIG_DMI=y CONFIG_GART_IOMMU=y # CONFIG_CALGARY_IOMMU is not set # CONFIG_AMD_IOMMU is not set CONFIG_SWIOTLB=y CONFIG_IOMMU_HELPER=y # CONFIG_IOMMU_API is not set # CONFIG_MAXSMP is not set CONFIG_NR_CPUS=4 # CONFIG_SCHED_SMT is not set CONFIG_SCHED_MC=y # CONFIG_PREEMPT_NONE is not set CONFIG_PREEMPT_VOLUNTARY=y # CONFIG_PREEMPT is not set CONFIG_X86_LOCAL_APIC=y CONFIG_X86_IO_APIC=y # CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS is not set # CONFIG_X86_MCE is not set # CONFIG_I8K is not set # CONFIG_MICROCODE is not set CONFIG_X86_MSR=y CONFIG_X86_CPUID=y CONFIG_ARCH_PHYS_ADDR_T_64BIT=y CONFIG_DIRECT_GBPAGES=y # CONFIG_NUMA is not set CONFIG_ARCH_SPARSEMEM_DEFAULT=y CONFIG_ARCH_SPARSEMEM_ENABLE=y CONFIG_ARCH_SELECT_MEMORY_MODEL=y CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000 CONFIG_SELECT_MEMORY_MODEL=y # CONFIG_FLATMEM_MANUAL is not set # CONFIG_DISCONTIGMEM_MANUAL is not set CONFIG_SPARSEMEM_MANUAL=y CONFIG_SPARSEMEM=y CONFIG_HAVE_MEMORY_PRESENT=y CONFIG_SPARSEMEM_EXTREME=y CONFIG_SPARSEMEM_VMEMMAP_ENABLE=y CONFIG_SPARSEMEM_VMEMMAP=y # CONFIG_MEMORY_HOTPLUG is not set CONFIG_PAGEFLAGS_EXTENDED=y CONFIG_SPLIT_PTLOCK_CPUS=4 CONFIG_PHYS_ADDR_T_64BIT=y CONFIG_ZONE_DMA_FLAG=1 CONFIG_BOUNCE=y CONFIG_VIRT_TO_BUS=y CONFIG_UNEVICTABLE_LRU=y # CONFIG_X86_CHECK_BIOS_CORRUPTION is not set CONFIG_X86_RESERVE_LOW_64K=y CONFIG_MTRR=y CONFIG_MTRR_SANITIZER=y CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=0 CONFIG_MTRR_SANITIZER_SPARE_REG_NR_DEFAULT=1 # CONFIG_X86_PAT is not set # CONFIG_EFI is not set CONFIG_SECCOMP=y # CONFIG_CC_STACKPROTECTOR is not set # CONFIG_HZ_100 is not set # CONFIG_HZ_250 is not set # CONFIG_HZ_300 is not set CONFIG_HZ_1000=y CONFIG_HZ=1000 # CONFIG_SCHED_HRTICK is not set CONFIG_KEXEC=y # CONFIG_CRASH_DUMP is not set CONFIG_PHYSICAL_START=0x200000 # CONFIG_RELOCATABLE is not set CONFIG_PHYSICAL_ALIGN=0x200000 CONFIG_HOTPLUG_CPU=y # CONFIG_COMPAT_VDSO is not set # CONFIG_CMDLINE_BOOL is not set CONFIG_ARCH_ENABLE_MEMORY_HOTPLUG=y # # Power management and ACPI options # CONFIG_PM=y CONFIG_PM_DEBUG=y # CONFIG_PM_VERBOSE is not set CONFIG_CAN_PM_TRACE=y CONFIG_PM_TRACE=y CONFIG_PM_TRACE_RTC=y CONFIG_PM_SLEEP_SMP=y CONFIG_PM_SLEEP=y CONFIG_SUSPEND=y CONFIG_SUSPEND_FREEZER=y # CONFIG_HIBERNATION is not set CONFIG_ACPI=y CONFIG_ACPI_SLEEP=y CONFIG_ACPI_PROCFS=y CONFIG_ACPI_PROCFS_POWER=y CONFIG_ACPI_SYSFS_POWER=y CONFIG_ACPI_PROC_EVENT=y CONFIG_ACPI_AC=y CONFIG_ACPI_BATTERY=y CONFIG_ACPI_BUTTON=y CONFIG_ACPI_FAN=y CONFIG_ACPI_DOCK=y CONFIG_ACPI_PROCESSOR=y CONFIG_ACPI_HOTPLUG_CPU=y CONFIG_ACPI_THERMAL=y # CONFIG_ACPI_CUSTOM_DSDT is not set CONFIG_ACPI_BLACKLIST_YEAR=0 # CONFIG_ACPI_DEBUG is not set # CONFIG_ACPI_PCI_SLOT is not set CONFIG_ACPI_SYSTEM=y CONFIG_X86_PM_TIMER=y CONFIG_ACPI_CONTAINER=y # CONFIG_ACPI_SBS is not set # # CPU Frequency scaling # # CONFIG_CPU_FREQ is not set CONFIG_CPU_IDLE=y CONFIG_CPU_IDLE_GOV_LADDER=y # # Memory power savings # # CONFIG_I7300_IDLE is not set # # Bus options (PCI etc.) # CONFIG_PCI=y CONFIG_PCI_DIRECT=y CONFIG_PCI_MMCONFIG=y CONFIG_PCI_XEN=y CONFIG_PCI_DOMAINS=y # CONFIG_DMAR is not set # CONFIG_INTR_REMAP is not set CONFIG_PCIEPORTBUS=y # CONFIG_HOTPLUG_PCI_PCIE is not set CONFIG_PCIEAER=y # CONFIG_PCIEASPM is not set CONFIG_ARCH_SUPPORTS_MSI=y CONFIG_PCI_MSI=y # CONFIG_PCI_LEGACY is not set # CONFIG_PCI_DEBUG is not set # CONFIG_PCI_STUB is not set CONFIG_HT_IRQ=y CONFIG_ISA_DMA_API=y CONFIG_K8_NB=y # CONFIG_PCCARD is not set CONFIG_HOTPLUG_PCI=y # CONFIG_HOTPLUG_PCI_FAKE is not set # CONFIG_HOTPLUG_PCI_ACPI is not set # CONFIG_HOTPLUG_PCI_CPCI is not set # CONFIG_HOTPLUG_PCI_SHPC is not set # # Executable file formats / Emulations # CONFIG_BINFMT_ELF=y CONFIG_COMPAT_BINFMT_ELF=y # CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set # CONFIG_HAVE_AOUT is not set CONFIG_BINFMT_MISC=y CONFIG_IA32_EMULATION=y # CONFIG_IA32_AOUT is not set CONFIG_COMPAT=y CONFIG_COMPAT_FOR_U64_ALIGNMENT=y CONFIG_SYSVIPC_COMPAT=y CONFIG_NET=y # # Networking options # CONFIG_COMPAT_NET_DEV_OPS=y CONFIG_PACKET=y CONFIG_PACKET_MMAP=y CONFIG_UNIX=y # CONFIG_NET_KEY is not set CONFIG_INET=y CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_ASK_IP_FIB_HASH=y # CONFIG_IP_FIB_TRIE is not set CONFIG_IP_FIB_HASH=y CONFIG_IP_MULTIPLE_TABLES=y # CONFIG_IP_ROUTE_MULTIPATH is not set CONFIG_IP_ROUTE_VERBOSE=y CONFIG_IP_PNP=y CONFIG_IP_PNP_DHCP=y CONFIG_IP_PNP_BOOTP=y CONFIG_IP_PNP_RARP=y # CONFIG_NET_IPIP is not set # CONFIG_NET_IPGRE is not set CONFIG_IP_MROUTE=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y # CONFIG_ARPD is not set CONFIG_SYN_COOKIES=y # CONFIG_INET_AH is not set # CONFIG_INET_ESP is not set # CONFIG_INET_IPCOMP is not set # CONFIG_INET_XFRM_TUNNEL is not set # CONFIG_INET_TUNNEL is not set # CONFIG_INET_XFRM_MODE_TRANSPORT is not set # CONFIG_INET_XFRM_MODE_TUNNEL is not set # CONFIG_INET_XFRM_MODE_BEET is not set CONFIG_INET_LRO=y # CONFIG_INET_DIAG is not set CONFIG_TCP_CONG_ADVANCED=y # CONFIG_TCP_CONG_BIC is not set CONFIG_TCP_CONG_CUBIC=y # CONFIG_TCP_CONG_WESTWOOD is not set # CONFIG_TCP_CONG_HTCP is not set # CONFIG_TCP_CONG_HSTCP is not set # CONFIG_TCP_CONG_HYBLA is not set # CONFIG_TCP_CONG_VEGAS is not set # CONFIG_TCP_CONG_SCALABLE is not set # CONFIG_TCP_CONG_LP is not set # CONFIG_TCP_CONG_VENO is not set # CONFIG_TCP_CONG_YEAH is not set # CONFIG_TCP_CONG_ILLINOIS is not set # CONFIG_DEFAULT_BIC is not set CONFIG_DEFAULT_CUBIC=y # CONFIG_DEFAULT_HTCP is not set # CONFIG_DEFAULT_VEGAS is not set # CONFIG_DEFAULT_WESTWOOD is not set # CONFIG_DEFAULT_RENO is not set CONFIG_DEFAULT_TCP_CONG="cubic" # CONFIG_TCP_MD5SIG is not set # CONFIG_IPV6 is not set # CONFIG_NETWORK_SECMARK is not set # CONFIG_NETFILTER is not set # CONFIG_IP_DCCP is not set # CONFIG_IP_SCTP is not set # CONFIG_TIPC is not set # CONFIG_ATM is not set CONFIG_STP=y CONFIG_BRIDGE=y # CONFIG_NET_DSA is not set # CONFIG_VLAN_8021Q is not set # CONFIG_DECNET is not set CONFIG_LLC=y # CONFIG_LLC2 is not set # CONFIG_IPX is not set # CONFIG_ATALK is not set # CONFIG_X25 is not set # CONFIG_LAPB is not set # CONFIG_ECONET is not set # CONFIG_WAN_ROUTER is not set # CONFIG_NET_SCHED is not set # CONFIG_DCB is not set # # Network testing # # CONFIG_NET_PKTGEN is not set # CONFIG_NET_TCPPROBE is not set # CONFIG_HAMRADIO is not set # CONFIG_CAN is not set # CONFIG_IRDA is not set # CONFIG_BT is not set # CONFIG_AF_RXRPC is not set # CONFIG_PHONET is not set CONFIG_FIB_RULES=y CONFIG_WIRELESS=y CONFIG_CFG80211=y # CONFIG_CFG80211_REG_DEBUG is not set CONFIG_NL80211=y CONFIG_WIRELESS_OLD_REGULATORY=y CONFIG_WIRELESS_EXT=y CONFIG_WIRELESS_EXT_SYSFS=y # CONFIG_LIB80211 is not set CONFIG_MAC80211=y # # Rate control algorithm selection # CONFIG_MAC80211_RC_MINSTREL=y # CONFIG_MAC80211_RC_DEFAULT_PID is not set CONFIG_MAC80211_RC_DEFAULT_MINSTREL=y CONFIG_MAC80211_RC_DEFAULT="minstrel" # CONFIG_MAC80211_MESH is not set CONFIG_MAC80211_LEDS=y # CONFIG_MAC80211_DEBUGFS is not set # CONFIG_MAC80211_DEBUG_MENU is not set # CONFIG_WIMAX is not set # CONFIG_RFKILL is not set # # Device Drivers # # # Generic Driver Options # CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_STANDALONE=y CONFIG_PREVENT_FIRMWARE_BUILD=y CONFIG_FW_LOADER=y CONFIG_FIRMWARE_IN_KERNEL=y CONFIG_EXTRA_FIRMWARE="" # CONFIG_DEBUG_DRIVER is not set CONFIG_DEBUG_DEVRES=y # CONFIG_SYS_HYPERVISOR is not set CONFIG_CONNECTOR=y CONFIG_PROC_EVENTS=y # CONFIG_MTD is not set # CONFIG_PARPORT is not set CONFIG_PNP=y CONFIG_PNP_DEBUG_MESSAGES=y # # Protocols # CONFIG_PNPACPI=y CONFIG_BLK_DEV=y # CONFIG_BLK_DEV_FD is not set # CONFIG_BLK_CPQ_DA is not set # CONFIG_BLK_CPQ_CISS_DA is not set # CONFIG_BLK_DEV_DAC960 is not set # CONFIG_BLK_DEV_UMEM is not set # CONFIG_BLK_DEV_COW_COMMON is not set CONFIG_BLK_DEV_LOOP=y # CONFIG_BLK_DEV_CRYPTOLOOP is not set # CONFIG_BLK_DEV_NBD is not set # CONFIG_BLK_DEV_SX8 is not set # CONFIG_BLK_DEV_UB is not set CONFIG_BLK_DEV_RAM=y CONFIG_BLK_DEV_RAM_COUNT=16 CONFIG_BLK_DEV_RAM_SIZE=16384 # CONFIG_BLK_DEV_XIP is not set # CONFIG_CDROM_PKTCDVD is not set # CONFIG_ATA_OVER_ETH is not set CONFIG_XEN_BLKDEV_FRONTEND=y # CONFIG_BLK_DEV_HD is not set CONFIG_MISC_DEVICES=y # CONFIG_IBM_ASM is not set # CONFIG_PHANTOM is not set # CONFIG_SGI_IOC4 is not set # CONFIG_TIFM_CORE is not set # CONFIG_ICS932S401 is not set # CONFIG_ENCLOSURE_SERVICES is not set # CONFIG_HP_ILO is not set # CONFIG_C2PORT is not set # # EEPROM support # # CONFIG_EEPROM_AT24 is not set # CONFIG_EEPROM_LEGACY is not set # CONFIG_EEPROM_93CX6 is not set CONFIG_HAVE_IDE=y # CONFIG_IDE is not set # # SCSI device support # # CONFIG_RAID_ATTRS is not set CONFIG_SCSI=y CONFIG_SCSI_DMA=y # CONFIG_SCSI_TGT is not set # CONFIG_SCSI_NETLINK is not set CONFIG_SCSI_PROC_FS=y # # SCSI support type (disk, tape, CD-ROM) # CONFIG_BLK_DEV_SD=y # CONFIG_CHR_DEV_ST is not set # CONFIG_CHR_DEV_OSST is not set CONFIG_BLK_DEV_SR=y CONFIG_BLK_DEV_SR_VENDOR=y CONFIG_CHR_DEV_SG=y # CONFIG_CHR_DEV_SCH is not set # # Some SCSI devices (e.g. CD jukebox) support multiple LUNs # # CONFIG_SCSI_MULTI_LUN is not set CONFIG_SCSI_CONSTANTS=y # CONFIG_SCSI_LOGGING is not set # CONFIG_SCSI_SCAN_ASYNC is not set CONFIG_SCSI_WAIT_SCAN=m # # SCSI Transports # CONFIG_SCSI_SPI_ATTRS=y # CONFIG_SCSI_FC_ATTRS is not set CONFIG_SCSI_ISCSI_ATTRS=y # CONFIG_SCSI_SAS_ATTRS is not set # CONFIG_SCSI_SAS_LIBSAS is not set # CONFIG_SCSI_SRP_ATTRS is not set # CONFIG_SCSI_LOWLEVEL is not set # CONFIG_SCSI_DH is not set CONFIG_ATA=y # CONFIG_ATA_NONSTANDARD is not set CONFIG_ATA_ACPI=y CONFIG_SATA_PMP=y CONFIG_SATA_AHCI=y # CONFIG_SATA_SIL24 is not set CONFIG_ATA_SFF=y # CONFIG_SATA_SVW is not set CONFIG_ATA_PIIX=y # CONFIG_SATA_MV is not set # CONFIG_SATA_NV is not set # CONFIG_PDC_ADMA is not set # CONFIG_SATA_QSTOR is not set # CONFIG_SATA_PROMISE is not set # CONFIG_SATA_SX4 is not set # CONFIG_SATA_SIL is not set # CONFIG_SATA_SIS is not set # CONFIG_SATA_ULI is not set # CONFIG_SATA_VIA is not set # CONFIG_SATA_VITESSE is not set # CONFIG_SATA_INIC162X is not set # CONFIG_PATA_ACPI is not set # CONFIG_PATA_ALI is not set CONFIG_PATA_AMD=y # CONFIG_PATA_ARTOP is not set # CONFIG_PATA_ATIIXP is not set # CONFIG_PATA_CMD640_PCI is not set # CONFIG_PATA_CMD64X is not set # CONFIG_PATA_CS5520 is not set # CONFIG_PATA_CS5530 is not set # CONFIG_PATA_CYPRESS is not set # CONFIG_PATA_EFAR is not set # CONFIG_ATA_GENERIC is not set # CONFIG_PATA_HPT366 is not set # CONFIG_PATA_HPT37X is not set # CONFIG_PATA_HPT3X2N is not set # CONFIG_PATA_HPT3X3 is not set # CONFIG_PATA_IT821X is not set # CONFIG_PATA_IT8213 is not set # CONFIG_PATA_JMICRON is not set # CONFIG_PATA_TRIFLEX is not set # CONFIG_PATA_MARVELL is not set # CONFIG_PATA_MPIIX is not set CONFIG_PATA_OLDPIIX=y # CONFIG_PATA_NETCELL is not set # CONFIG_PATA_NINJA32 is not set # CONFIG_PATA_NS87410 is not set # CONFIG_PATA_NS87415 is not set # CONFIG_PATA_OPTI is not set # CONFIG_PATA_OPTIDMA is not set # CONFIG_PATA_PDC_OLD is not set # CONFIG_PATA_RADISYS is not set # CONFIG_PATA_RZ1000 is not set # CONFIG_PATA_SC1200 is not set # CONFIG_PATA_SERVERWORKS is not set # CONFIG_PATA_PDC2027X is not set # CONFIG_PATA_SIL680 is not set # CONFIG_PATA_SIS is not set # CONFIG_PATA_VIA is not set # CONFIG_PATA_WINBOND is not set CONFIG_PATA_SCH=y CONFIG_MD=y CONFIG_BLK_DEV_MD=y CONFIG_MD_AUTODETECT=y # CONFIG_MD_LINEAR is not set # CONFIG_MD_RAID0 is not set # CONFIG_MD_RAID1 is not set # CONFIG_MD_RAID10 is not set # CONFIG_MD_RAID456 is not set # CONFIG_MD_MULTIPATH is not set # CONFIG_MD_FAULTY is not set CONFIG_BLK_DEV_DM=y # CONFIG_DM_DEBUG is not set # CONFIG_DM_CRYPT is not set CONFIG_DM_SNAPSHOT=m CONFIG_DM_MIRROR=y CONFIG_DM_ZERO=y # CONFIG_DM_MULTIPATH is not set # CONFIG_DM_DELAY is not set # CONFIG_DM_UEVENT is not set # CONFIG_FUSION is not set # # IEEE 1394 (FireWire) support # # # Enable only one of the two stacks, unless you know what you are doing # # CONFIG_FIREWIRE is not set # CONFIG_IEEE1394 is not set # CONFIG_I2O is not set # CONFIG_MACINTOSH_DRIVERS is not set CONFIG_NETDEVICES=y # CONFIG_DUMMY is not set # CONFIG_BONDING is not set # CONFIG_MACVLAN is not set # CONFIG_EQUALIZER is not set CONFIG_TUN=y # CONFIG_VETH is not set # CONFIG_NET_SB1000 is not set # CONFIG_ARCNET is not set # CONFIG_NET_ETHERNET is not set CONFIG_NETDEV_1000=y # CONFIG_ACENIC is not set # CONFIG_DL2K is not set # CONFIG_E1000 is not set CONFIG_E1000E=m # CONFIG_IP1000 is not set # CONFIG_IGB is not set # CONFIG_NS83820 is not set # CONFIG_HAMACHI is not set # CONFIG_YELLOWFIN is not set # CONFIG_R8169 is not set # CONFIG_SIS190 is not set # CONFIG_SKGE is not set # CONFIG_SKY2 is not set # CONFIG_VIA_VELOCITY is not set # CONFIG_TIGON3 is not set # CONFIG_BNX2 is not set # CONFIG_QLA3XXX is not set # CONFIG_ATL1 is not set # CONFIG_ATL1E is not set # CONFIG_JME is not set # CONFIG_NETDEV_10000 is not set # CONFIG_TR is not set # # Wireless LAN # # CONFIG_WLAN_PRE80211 is not set # CONFIG_WLAN_80211 is not set # CONFIG_IWLWIFI_LEDS is not set # # Enable WiMAX (Networking options) to see the WiMAX drivers # # # USB Network Adapters # # CONFIG_USB_CATC is not set # CONFIG_USB_KAWETH is not set # CONFIG_USB_PEGASUS is not set # CONFIG_USB_RTL8150 is not set # CONFIG_USB_USBNET is not set # CONFIG_WAN is not set CONFIG_XEN_NETDEV_FRONTEND=y # CONFIG_FDDI is not set # CONFIG_HIPPI is not set # CONFIG_PPP is not set # CONFIG_SLIP is not set # CONFIG_NET_FC is not set CONFIG_NETCONSOLE=y # CONFIG_NETCONSOLE_DYNAMIC is not set CONFIG_NETPOLL=y # CONFIG_NETPOLL_TRAP is not set CONFIG_NET_POLL_CONTROLLER=y # CONFIG_ISDN is not set # CONFIG_PHONE is not set # # Input device support # CONFIG_INPUT=y CONFIG_INPUT_FF_MEMLESS=y CONFIG_INPUT_POLLDEV=y # # Userland interfaces # CONFIG_INPUT_MOUSEDEV=y # CONFIG_INPUT_MOUSEDEV_PSAUX is not set CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768 # CONFIG_INPUT_JOYDEV is not set CONFIG_INPUT_EVDEV=y # CONFIG_INPUT_EVBUG is not set CONFIG_XEN_KBDDEV_FRONTEND=y # # Input Device Drivers # CONFIG_INPUT_KEYBOARD=y CONFIG_KEYBOARD_ATKBD=y # CONFIG_KEYBOARD_SUNKBD is not set # CONFIG_KEYBOARD_LKKBD is not set # CONFIG_KEYBOARD_XTKBD is not set # CONFIG_KEYBOARD_NEWTON is not set # CONFIG_KEYBOARD_STOWAWAY is not set CONFIG_INPUT_MOUSE=y CONFIG_MOUSE_PS2=y CONFIG_MOUSE_PS2_ALPS=y CONFIG_MOUSE_PS2_LOGIPS2PP=y CONFIG_MOUSE_PS2_SYNAPTICS=y CONFIG_MOUSE_PS2_LIFEBOOK=y CONFIG_MOUSE_PS2_TRACKPOINT=y # CONFIG_MOUSE_PS2_ELANTECH is not set # CONFIG_MOUSE_PS2_TOUCHKIT is not set # CONFIG_MOUSE_SERIAL is not set # CONFIG_MOUSE_APPLETOUCH is not set # CONFIG_MOUSE_BCM5974 is not set # CONFIG_MOUSE_VSXXXAA is not set CONFIG_INPUT_JOYSTICK=y # CONFIG_JOYSTICK_ANALOG is not set # CONFIG_JOYSTICK_A3D is not set # CONFIG_JOYSTICK_ADI is not set # CONFIG_JOYSTICK_COBRA is not set # CONFIG_JOYSTICK_GF2K is not set # CONFIG_JOYSTICK_GRIP is not set # CONFIG_JOYSTICK_GRIP_MP is not set # CONFIG_JOYSTICK_GUILLEMOT is not set # CONFIG_JOYSTICK_INTERACT is not set # CONFIG_JOYSTICK_SIDEWINDER is not set # CONFIG_JOYSTICK_TMDC is not set # CONFIG_JOYSTICK_IFORCE is not set # CONFIG_JOYSTICK_WARRIOR is not set # CONFIG_JOYSTICK_MAGELLAN is not set # CONFIG_JOYSTICK_SPACEORB is not set # CONFIG_JOYSTICK_SPACEBALL is not set # CONFIG_JOYSTICK_STINGER is not set # CONFIG_JOYSTICK_TWIDJOY is not set # CONFIG_JOYSTICK_ZHENHUA is not set # CONFIG_JOYSTICK_JOYDUMP is not set # CONFIG_JOYSTICK_XPAD is not set CONFIG_INPUT_TABLET=y # CONFIG_TABLET_USB_ACECAD is not set # CONFIG_TABLET_USB_AIPTEK is not set # CONFIG_TABLET_USB_GTCO is not set # CONFIG_TABLET_USB_KBTAB is not set # CONFIG_TABLET_USB_WACOM is not set CONFIG_INPUT_TOUCHSCREEN=y # CONFIG_TOUCHSCREEN_FUJITSU is not set # CONFIG_TOUCHSCREEN_GUNZE is not set # CONFIG_TOUCHSCREEN_ELO is not set # CONFIG_TOUCHSCREEN_WACOM_W8001 is not set # CONFIG_TOUCHSCREEN_MTOUCH is not set # CONFIG_TOUCHSCREEN_INEXIO is not set # CONFIG_TOUCHSCREEN_MK712 is not set # CONFIG_TOUCHSCREEN_PENMOUNT is not set # CONFIG_TOUCHSCREEN_TOUCHRIGHT is not set # CONFIG_TOUCHSCREEN_TOUCHWIN is not set # CONFIG_TOUCHSCREEN_USB_COMPOSITE is not set # CONFIG_TOUCHSCREEN_TOUCHIT213 is not set # CONFIG_TOUCHSCREEN_TSC2007 is not set CONFIG_INPUT_MISC=y # CONFIG_INPUT_PCSPKR is not set # CONFIG_INPUT_APANEL is not set # CONFIG_INPUT_ATLAS_BTNS is not set # CONFIG_INPUT_ATI_REMOTE is not set # CONFIG_INPUT_ATI_REMOTE2 is not set # CONFIG_INPUT_KEYSPAN_REMOTE is not set # CONFIG_INPUT_POWERMATE is not set # CONFIG_INPUT_YEALINK is not set # CONFIG_INPUT_CM109 is not set # CONFIG_INPUT_UINPUT is not set # # Hardware I/O ports # CONFIG_SERIO=y CONFIG_SERIO_I8042=y CONFIG_SERIO_SERPORT=y # CONFIG_SERIO_CT82C710 is not set # CONFIG_SERIO_PCIPS2 is not set CONFIG_SERIO_LIBPS2=y # CONFIG_SERIO_RAW is not set # CONFIG_GAMEPORT is not set # # Character devices # CONFIG_VT=y CONFIG_CONSOLE_TRANSLATIONS=y CONFIG_VT_CONSOLE=y CONFIG_HW_CONSOLE=y CONFIG_VT_HW_CONSOLE_BINDING=y CONFIG_DEVKMEM=y CONFIG_SERIAL_NONSTANDARD=y # CONFIG_COMPUTONE is not set # CONFIG_ROCKETPORT is not set # CONFIG_CYCLADES is not set # CONFIG_DIGIEPCA is not set # CONFIG_MOXA_INTELLIO is not set # CONFIG_MOXA_SMARTIO is not set # CONFIG_ISI is not set # CONFIG_SYNCLINK is not set # CONFIG_SYNCLINKMP is not set # CONFIG_SYNCLINK_GT is not set # CONFIG_N_HDLC is not set # CONFIG_RISCOM8 is not set # CONFIG_SPECIALIX is not set # CONFIG_SX is not set # CONFIG_RIO is not set # CONFIG_STALDRV is not set # CONFIG_NOZOMI is not set # # Serial drivers # # CONFIG_SERIAL_8250 is not set CONFIG_FIX_EARLYCON_MEM=y # # Non-8250 serial port support # # CONFIG_SERIAL_JSM is not set CONFIG_UNIX98_PTYS=y # CONFIG_DEVPTS_MULTIPLE_INSTANCES is not set # CONFIG_LEGACY_PTYS is not set CONFIG_HVC_DRIVER=y CONFIG_HVC_IRQ=y CONFIG_HVC_XEN=y # CONFIG_IPMI_HANDLER is not set CONFIG_HW_RANDOM=y # CONFIG_HW_RANDOM_INTEL is not set # CONFIG_HW_RANDOM_AMD is not set CONFIG_NVRAM=y # CONFIG_RTC is not set # CONFIG_GEN_RTC is not set # CONFIG_R3964 is not set # CONFIG_APPLICOM is not set # CONFIG_MWAVE is not set # CONFIG_PC8736x_GPIO is not set # CONFIG_RAW_DRIVER is not set # CONFIG_HPET is not set # CONFIG_HANGCHECK_TIMER is not set # CONFIG_TCG_TPM is not set # CONFIG_TELCLOCK is not set CONFIG_DEVPORT=y CONFIG_I2C=y CONFIG_I2C_BOARDINFO=y # CONFIG_I2C_CHARDEV is not set CONFIG_I2C_HELPER_AUTO=y CONFIG_I2C_ALGOBIT=y # # I2C Hardware Bus support # # # PC SMBus host controller drivers # # CONFIG_I2C_ALI1535 is not set # CONFIG_I2C_ALI1563 is not set # CONFIG_I2C_ALI15X3 is not set # CONFIG_I2C_AMD756 is not set # CONFIG_I2C_AMD8111 is not set # CONFIG_I2C_I801 is not set # CONFIG_I2C_ISCH is not set # CONFIG_I2C_PIIX4 is not set # CONFIG_I2C_NFORCE2 is not set # CONFIG_I2C_SIS5595 is not set # CONFIG_I2C_SIS630 is not set # CONFIG_I2C_SIS96X is not set # CONFIG_I2C_VIA is not set # CONFIG_I2C_VIAPRO is not set # # I2C system bus drivers (mostly embedded / system-on-chip) # # CONFIG_I2C_OCORES is not set # CONFIG_I2C_SIMTEC is not set # # External I2C/SMBus adapter drivers # # CONFIG_I2C_PARPORT_LIGHT is not set # CONFIG_I2C_TAOS_EVM is not set # CONFIG_I2C_TINY_USB is not set # # Graphics adapter I2C/DDC channel drivers # # CONFIG_I2C_VOODOO3 is not set # # Other I2C/SMBus bus drivers # # CONFIG_I2C_PCA_PLATFORM is not set # CONFIG_I2C_STUB is not set # # Miscellaneous I2C Chip support # # CONFIG_DS1682 is not set # CONFIG_SENSORS_PCF8574 is not set # CONFIG_PCF8575 is not set # CONFIG_SENSORS_PCA9539 is not set # CONFIG_SENSORS_PCF8591 is not set # CONFIG_SENSORS_MAX6875 is not set # CONFIG_SENSORS_TSL2550 is not set # CONFIG_I2C_DEBUG_CORE is not set # CONFIG_I2C_DEBUG_ALGO is not set # CONFIG_I2C_DEBUG_BUS is not set # CONFIG_I2C_DEBUG_CHIP is not set # CONFIG_SPI is not set CONFIG_ARCH_WANT_OPTIONAL_GPIOLIB=y # CONFIG_GPIOLIB is not set # CONFIG_W1 is not set CONFIG_POWER_SUPPLY=y # CONFIG_POWER_SUPPLY_DEBUG is not set # CONFIG_PDA_POWER is not set # CONFIG_BATTERY_DS2760 is not set # CONFIG_BATTERY_BQ27x00 is not set CONFIG_HWMON=m # CONFIG_HWMON_VID is not set # CONFIG_SENSORS_ABITUGURU is not set # CONFIG_SENSORS_ABITUGURU3 is not set # CONFIG_SENSORS_AD7414 is not set # CONFIG_SENSORS_AD7418 is not set # CONFIG_SENSORS_ADM1021 is not set # CONFIG_SENSORS_ADM1025 is not set # CONFIG_SENSORS_ADM1026 is not set # CONFIG_SENSORS_ADM1029 is not set # CONFIG_SENSORS_ADM1031 is not set # CONFIG_SENSORS_ADM9240 is not set # CONFIG_SENSORS_ADT7462 is not set # CONFIG_SENSORS_ADT7470 is not set # CONFIG_SENSORS_ADT7473 is not set # CONFIG_SENSORS_ADT7475 is not set # CONFIG_SENSORS_K8TEMP is not set # CONFIG_SENSORS_ASB100 is not set # CONFIG_SENSORS_ATXP1 is not set # CONFIG_SENSORS_DS1621 is not set # CONFIG_SENSORS_I5K_AMB is not set # CONFIG_SENSORS_F71805F is not set # CONFIG_SENSORS_F71882FG is not set # CONFIG_SENSORS_F75375S is not set # CONFIG_SENSORS_FSCHER is not set # CONFIG_SENSORS_FSCPOS is not set # CONFIG_SENSORS_FSCHMD is not set # CONFIG_SENSORS_GL518SM is not set # CONFIG_SENSORS_GL520SM is not set CONFIG_SENSORS_CORETEMP=m # CONFIG_SENSORS_IT87 is not set # CONFIG_SENSORS_LM63 is not set # CONFIG_SENSORS_LM75 is not set # CONFIG_SENSORS_LM77 is not set # CONFIG_SENSORS_LM78 is not set # CONFIG_SENSORS_LM80 is not set # CONFIG_SENSORS_LM83 is not set # CONFIG_SENSORS_LM85 is not set # CONFIG_SENSORS_LM87 is not set # CONFIG_SENSORS_LM90 is not set # CONFIG_SENSORS_LM92 is not set # CONFIG_SENSORS_LM93 is not set # CONFIG_SENSORS_LTC4245 is not set # CONFIG_SENSORS_MAX1619 is not set # CONFIG_SENSORS_MAX6650 is not set # CONFIG_SENSORS_PC87360 is not set # CONFIG_SENSORS_PC87427 is not set # CONFIG_SENSORS_SIS5595 is not set # CONFIG_SENSORS_DME1737 is not set # CONFIG_SENSORS_SMSC47M1 is not set # CONFIG_SENSORS_SMSC47M192 is not set # CONFIG_SENSORS_SMSC47B397 is not set # CONFIG_SENSORS_ADS7828 is not set # CONFIG_SENSORS_THMC50 is not set # CONFIG_SENSORS_VIA686A is not set # CONFIG_SENSORS_VT1211 is not set # CONFIG_SENSORS_VT8231 is not set # CONFIG_SENSORS_W83781D is not set # CONFIG_SENSORS_W83791D is not set # CONFIG_SENSORS_W83792D is not set # CONFIG_SENSORS_W83793 is not set # CONFIG_SENSORS_W83L785TS is not set # CONFIG_SENSORS_W83L786NG is not set # CONFIG_SENSORS_W83627HF is not set # CONFIG_SENSORS_W83627EHF is not set # CONFIG_SENSORS_HDAPS is not set # CONFIG_SENSORS_LIS3LV02D is not set # CONFIG_SENSORS_APPLESMC is not set # CONFIG_HWMON_DEBUG_CHIP is not set CONFIG_THERMAL=y # CONFIG_WATCHDOG is not set CONFIG_SSB_POSSIBLE=y # # Sonics Silicon Backplane # # CONFIG_SSB is not set # # Multifunction device drivers # # CONFIG_MFD_CORE is not set # CONFIG_MFD_SM501 is not set # CONFIG_HTC_PASIC3 is not set # CONFIG_TWL4030_CORE is not set # CONFIG_MFD_TMIO is not set # CONFIG_PMIC_DA903X is not set # CONFIG_MFD_WM8400 is not set # CONFIG_MFD_PCF50633 is not set # CONFIG_REGULATOR is not set # # Multimedia devices # # # Multimedia core support # # CONFIG_VIDEO_DEV is not set # CONFIG_DVB_CORE is not set # CONFIG_VIDEO_MEDIA is not set # # Multimedia drivers # # CONFIG_DAB is not set # # Graphics support # CONFIG_AGP=y CONFIG_AGP_AMD64=y CONFIG_AGP_INTEL=y # CONFIG_AGP_SIS is not set # CONFIG_AGP_VIA is not set CONFIG_DRM=y # CONFIG_DRM_TDFX is not set # CONFIG_DRM_R128 is not set # CONFIG_DRM_RADEON is not set # CONFIG_DRM_I810 is not set # CONFIG_DRM_I830 is not set CONFIG_DRM_I915=y # CONFIG_DRM_I915_KMS is not set # CONFIG_DRM_MGA is not set # CONFIG_DRM_SIS is not set # CONFIG_DRM_VIA is not set # CONFIG_DRM_SAVAGE is not set # CONFIG_VGASTATE is not set # CONFIG_VIDEO_OUTPUT_CONTROL is not set CONFIG_FB=y # CONFIG_FIRMWARE_EDID is not set # CONFIG_FB_DDC is not set # CONFIG_FB_BOOT_VESA_SUPPORT is not set CONFIG_FB_CFB_FILLRECT=y CONFIG_FB_CFB_COPYAREA=y CONFIG_FB_CFB_IMAGEBLIT=y # CONFIG_FB_CFB_REV_PIXELS_IN_BYTE is not set CONFIG_FB_SYS_FILLRECT=y CONFIG_FB_SYS_COPYAREA=y CONFIG_FB_SYS_IMAGEBLIT=y # CONFIG_FB_FOREIGN_ENDIAN is not set CONFIG_FB_SYS_FOPS=y CONFIG_FB_DEFERRED_IO=y # CONFIG_FB_SVGALIB is not set # CONFIG_FB_MACMODES is not set # CONFIG_FB_BACKLIGHT is not set CONFIG_FB_MODE_HELPERS=y CONFIG_FB_TILEBLITTING=y # # Frame buffer hardware drivers # # CONFIG_FB_CIRRUS is not set # CONFIG_FB_PM2 is not set # CONFIG_FB_CYBER2000 is not set # CONFIG_FB_ARC is not set # CONFIG_FB_ASILIANT is not set # CONFIG_FB_IMSTT is not set # CONFIG_FB_VGA16 is not set # CONFIG_FB_UVESA is not set # CONFIG_FB_VESA is not set # CONFIG_FB_N411 is not set # CONFIG_FB_HGA is not set # CONFIG_FB_S1D13XXX is not set # CONFIG_FB_NVIDIA is not set # CONFIG_FB_RIVA is not set # CONFIG_FB_LE80578 is not set # CONFIG_FB_INTEL is not set # CONFIG_FB_MATROX is not set # CONFIG_FB_RADEON is not set # CONFIG_FB_ATY128 is not set # CONFIG_FB_ATY is not set # CONFIG_FB_S3 is not set # CONFIG_FB_SAVAGE is not set # CONFIG_FB_SIS is not set # CONFIG_FB_VIA is not set # CONFIG_FB_NEOMAGIC is not set # CONFIG_FB_KYRO is not set # CONFIG_FB_3DFX is not set # CONFIG_FB_VOODOO1 is not set # CONFIG_FB_VT8623 is not set # CONFIG_FB_TRIDENT is not set # CONFIG_FB_ARK is not set # CONFIG_FB_PM3 is not set # CONFIG_FB_CARMINE is not set # CONFIG_FB_GEODE is not set # CONFIG_FB_VIRTUAL is not set CONFIG_XEN_FBDEV_FRONTEND=y # CONFIG_FB_METRONOME is not set # CONFIG_FB_MB862XX is not set CONFIG_BACKLIGHT_LCD_SUPPORT=y # CONFIG_LCD_CLASS_DEVICE is not set CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_GENERIC=y # CONFIG_BACKLIGHT_PROGEAR is not set # CONFIG_BACKLIGHT_MBP_NVIDIA is not set # CONFIG_BACKLIGHT_SAHARA is not set # # Display device support # # CONFIG_DISPLAY_SUPPORT is not set # # Console display driver support # CONFIG_VGA_CONSOLE=y CONFIG_VGACON_SOFT_SCROLLBACK=y CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64 CONFIG_DUMMY_CONSOLE=y # CONFIG_FRAMEBUFFER_CONSOLE is not set CONFIG_LOGO=y # CONFIG_LOGO_LINUX_MONO is not set # CONFIG_LOGO_LINUX_VGA16 is not set CONFIG_LOGO_LINUX_CLUT224=y # CONFIG_SOUND is not set # CONFIG_HID_SUPPORT is not set CONFIG_USB_SUPPORT=y CONFIG_USB_ARCH_HAS_HCD=y CONFIG_USB_ARCH_HAS_OHCI=y CONFIG_USB_ARCH_HAS_EHCI=y CONFIG_USB=y CONFIG_USB_DEBUG=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y # # Miscellaneous USB options # CONFIG_USB_DEVICEFS=y # CONFIG_USB_DEVICE_CLASS is not set # CONFIG_USB_DYNAMIC_MINORS is not set CONFIG_USB_SUSPEND=y # CONFIG_USB_OTG is not set CONFIG_USB_MON=y # CONFIG_USB_WUSB is not set # CONFIG_USB_WUSB_CBAF is not set # # USB Host Controller Drivers # # CONFIG_USB_C67X00_HCD is not set CONFIG_USB_EHCI_HCD=y # CONFIG_USB_EHCI_ROOT_HUB_TT is not set # CONFIG_USB_EHCI_TT_NEWSCHED is not set # CONFIG_USB_OXU210HP_HCD is not set # CONFIG_USB_ISP116X_HCD is not set # CONFIG_USB_ISP1760_HCD is not set CONFIG_USB_OHCI_HCD=y # CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set # CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set CONFIG_USB_OHCI_LITTLE_ENDIAN=y CONFIG_USB_UHCI_HCD=y # CONFIG_USB_SL811_HCD is not set # CONFIG_USB_R8A66597_HCD is not set # CONFIG_USB_HWA_HCD is not set # # USB Device Class drivers # # CONFIG_USB_ACM is not set CONFIG_USB_PRINTER=y # CONFIG_USB_WDM is not set # CONFIG_USB_TMC is not set # # NOTE: USB_STORAGE depends on SCSI but BLK_DEV_SD may also be needed; # # # see USB_STORAGE Help for more information # CONFIG_USB_STORAGE=y # CONFIG_USB_STORAGE_DEBUG is not set # CONFIG_USB_STORAGE_DATAFAB is not set # CONFIG_USB_STORAGE_FREECOM is not set # CONFIG_USB_STORAGE_ISD200 is not set # CONFIG_USB_STORAGE_USBAT is not set # CONFIG_USB_STORAGE_SDDR09 is not set # CONFIG_USB_STORAGE_SDDR55 is not set # CONFIG_USB_STORAGE_JUMPSHOT is not set # CONFIG_USB_STORAGE_ALAUDA is not set # CONFIG_USB_STORAGE_ONETOUCH is not set # CONFIG_USB_STORAGE_KARMA is not set # CONFIG_USB_STORAGE_CYPRESS_ATACB is not set CONFIG_USB_LIBUSUAL=y # # USB Imaging devices # # CONFIG_USB_MDC800 is not set # CONFIG_USB_MICROTEK is not set # # USB port drivers # # CONFIG_USB_SERIAL is not set # # USB Miscellaneous drivers # # CONFIG_USB_EMI62 is not set # CONFIG_USB_EMI26 is not set # CONFIG_USB_ADUTUX is not set # CONFIG_USB_SEVSEG is not set # CONFIG_USB_RIO500 is not set # CONFIG_USB_LEGOTOWER is not set # CONFIG_USB_LCD is not set # CONFIG_USB_BERRY_CHARGE is not set # CONFIG_USB_LED is not set # CONFIG_USB_CYPRESS_CY7C63 is not set # CONFIG_USB_CYTHERM is not set # CONFIG_USB_PHIDGET is not set # CONFIG_USB_IDMOUSE is not set # CONFIG_USB_FTDI_ELAN is not set # CONFIG_USB_APPLEDISPLAY is not set # CONFIG_USB_SISUSBVGA is not set # CONFIG_USB_LD is not set # CONFIG_USB_TRANCEVIBRATOR is not set # CONFIG_USB_IOWARRIOR is not set # CONFIG_USB_TEST is not set # CONFIG_USB_ISIGHTFW is not set # CONFIG_USB_VST is not set # # OTG and related infrastructure # # CONFIG_UWB is not set # CONFIG_MMC is not set # CONFIG_MEMSTICK is not set CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y # # LED drivers # # CONFIG_LEDS_ALIX2 is not set # CONFIG_LEDS_PCA9532 is not set # CONFIG_LEDS_CLEVO_MAIL is not set # CONFIG_LEDS_PCA955X is not set # # LED Triggers # CONFIG_LEDS_TRIGGERS=y # CONFIG_LEDS_TRIGGER_TIMER is not set # CONFIG_LEDS_TRIGGER_HEARTBEAT is not set # CONFIG_LEDS_TRIGGER_BACKLIGHT is not set # CONFIG_LEDS_TRIGGER_DEFAULT_ON is not set # CONFIG_ACCESSIBILITY is not set # CONFIG_EDAC is not set # CONFIG_RTC_CLASS is not set # CONFIG_DMADEVICES is not set # CONFIG_UIO is not set CONFIG_XEN_BALLOON=y CONFIG_XEN_SCRUB_PAGES=y CONFIG_XEN_DEV_EVTCHN=y CONFIG_XEN_BACKEND=y CONFIG_XEN_BLKDEV_BACKEND=y CONFIG_XEN_NETDEV_BACKEND=y CONFIG_XENFS=y CONFIG_XEN_COMPAT_XENFS=y CONFIG_XEN_XENBUS_FRONTEND=y # CONFIG_STAGING is not set CONFIG_X86_PLATFORM_DEVICES=y # CONFIG_ASUS_LAPTOP is not set # CONFIG_FUJITSU_LAPTOP is not set # CONFIG_MSI_LAPTOP is not set # CONFIG_PANASONIC_LAPTOP is not set # CONFIG_COMPAL_LAPTOP is not set # CONFIG_SONY_LAPTOP is not set # CONFIG_THINKPAD_ACPI is not set # CONFIG_INTEL_MENLOW is not set # CONFIG_ACPI_WMI is not set # CONFIG_ACPI_ASUS is not set # CONFIG_ACPI_TOSHIBA is not set # # Firmware Drivers # # CONFIG_EDD is not set CONFIG_FIRMWARE_MEMMAP=y # CONFIG_DELL_RBU is not set CONFIG_DCDBAS=y CONFIG_DMIID=y # CONFIG_ISCSI_IBFT_FIND is not set # # File systems # CONFIG_EXT2_FS=m # CONFIG_EXT2_FS_XATTR is not set # CONFIG_EXT2_FS_XIP is not set CONFIG_EXT3_FS=y CONFIG_EXT3_FS_XATTR=y CONFIG_EXT3_FS_POSIX_ACL=y CONFIG_EXT3_FS_SECURITY=y # CONFIG_EXT4_FS is not set CONFIG_JBD=y # CONFIG_JBD_DEBUG is not set CONFIG_FS_MBCACHE=y # CONFIG_REISERFS_FS is not set # CONFIG_JFS_FS is not set CONFIG_FS_POSIX_ACL=y CONFIG_FILE_LOCKING=y # CONFIG_XFS_FS is not set # CONFIG_GFS2_FS is not set # CONFIG_OCFS2_FS is not set # CONFIG_BTRFS_FS is not set CONFIG_DNOTIFY=y CONFIG_INOTIFY=y CONFIG_INOTIFY_USER=y CONFIG_QUOTA=y CONFIG_QUOTA_NETLINK_INTERFACE=y # CONFIG_PRINT_QUOTA_WARNING is not set CONFIG_QUOTA_TREE=y # CONFIG_QFMT_V1 is not set CONFIG_QFMT_V2=y CONFIG_QUOTACTL=y # CONFIG_AUTOFS_FS is not set CONFIG_AUTOFS4_FS=y # CONFIG_FUSE_FS is not set CONFIG_GENERIC_ACL=y # # CD-ROM/DVD Filesystems # CONFIG_ISO9660_FS=y CONFIG_JOLIET=y CONFIG_ZISOFS=y # CONFIG_UDF_FS is not set # # DOS/FAT/NT Filesystems # CONFIG_FAT_FS=y CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y CONFIG_FAT_DEFAULT_CODEPAGE=437 CONFIG_FAT_DEFAULT_IOCHARSET="iso8859-1" # CONFIG_NTFS_FS is not set # # Pseudo filesystems # CONFIG_PROC_FS=y CONFIG_PROC_KCORE=y CONFIG_PROC_SYSCTL=y CONFIG_PROC_PAGE_MONITOR=y CONFIG_SYSFS=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y # CONFIG_HUGETLBFS is not set # CONFIG_HUGETLB_PAGE is not set # CONFIG_CONFIGFS_FS is not set CONFIG_MISC_FILESYSTEMS=y # CONFIG_ADFS_FS is not set # CONFIG_AFFS_FS is not set # CONFIG_ECRYPT_FS is not set # CONFIG_HFS_FS is not set # CONFIG_HFSPLUS_FS is not set # CONFIG_BEFS_FS is not set # CONFIG_BFS_FS is not set # CONFIG_EFS_FS is not set # CONFIG_CRAMFS is not set # CONFIG_SQUASHFS is not set # CONFIG_VXFS_FS is not set # CONFIG_MINIX_FS is not set # CONFIG_OMFS_FS is not set # CONFIG_HPFS_FS is not set # CONFIG_QNX4FS_FS is not set # CONFIG_ROMFS_FS is not set # CONFIG_SYSV_FS is not set # CONFIG_UFS_FS is not set CONFIG_NETWORK_FILESYSTEMS=y CONFIG_NFS_FS=y CONFIG_NFS_V3=y CONFIG_NFS_V3_ACL=y CONFIG_NFS_V4=y CONFIG_ROOT_NFS=y # CONFIG_NFSD is not set CONFIG_LOCKD=y CONFIG_LOCKD_V4=y CONFIG_NFS_ACL_SUPPORT=y CONFIG_NFS_COMMON=y CONFIG_SUNRPC=y CONFIG_SUNRPC_GSS=y # CONFIG_SUNRPC_REGISTER_V4 is not set CONFIG_RPCSEC_GSS_KRB5=y # CONFIG_RPCSEC_GSS_SPKM3 is not set # CONFIG_SMB_FS is not set # CONFIG_CIFS is not set # CONFIG_NCP_FS is not set # CONFIG_CODA_FS is not set # CONFIG_AFS_FS is not set # # Partition Types # CONFIG_PARTITION_ADVANCED=y # CONFIG_ACORN_PARTITION is not set CONFIG_OSF_PARTITION=y CONFIG_AMIGA_PARTITION=y # CONFIG_ATARI_PARTITION is not set CONFIG_MAC_PARTITION=y CONFIG_MSDOS_PARTITION=y CONFIG_BSD_DISKLABEL=y CONFIG_MINIX_SUBPARTITION=y CONFIG_SOLARIS_X86_PARTITION=y CONFIG_UNIXWARE_DISKLABEL=y # CONFIG_LDM_PARTITION is not set CONFIG_SGI_PARTITION=y # CONFIG_ULTRIX_PARTITION is not set CONFIG_SUN_PARTITION=y CONFIG_KARMA_PARTITION=y CONFIG_EFI_PARTITION=y # CONFIG_SYSV68_PARTITION is not set CONFIG_NLS=y CONFIG_NLS_DEFAULT="utf8" CONFIG_NLS_CODEPAGE_437=y # CONFIG_NLS_CODEPAGE_737 is not set # CONFIG_NLS_CODEPAGE_775 is not set # CONFIG_NLS_CODEPAGE_850 is not set # CONFIG_NLS_CODEPAGE_852 is not set # CONFIG_NLS_CODEPAGE_855 is not set # CONFIG_NLS_CODEPAGE_857 is not set # CONFIG_NLS_CODEPAGE_860 is not set # CONFIG_NLS_CODEPAGE_861 is not set # CONFIG_NLS_CODEPAGE_862 is not set # CONFIG_NLS_CODEPAGE_863 is not set # CONFIG_NLS_CODEPAGE_864 is not set # CONFIG_NLS_CODEPAGE_865 is not set # CONFIG_NLS_CODEPAGE_866 is not set # CONFIG_NLS_CODEPAGE_869 is not set # CONFIG_NLS_CODEPAGE_936 is not set # CONFIG_NLS_CODEPAGE_950 is not set # CONFIG_NLS_CODEPAGE_932 is not set # CONFIG_NLS_CODEPAGE_949 is not set # CONFIG_NLS_CODEPAGE_874 is not set # CONFIG_NLS_ISO8859_8 is not set # CONFIG_NLS_CODEPAGE_1250 is not set # CONFIG_NLS_CODEPAGE_1251 is not set CONFIG_NLS_ASCII=y CONFIG_NLS_ISO8859_1=y # CONFIG_NLS_ISO8859_2 is not set # CONFIG_NLS_ISO8859_3 is not set # CONFIG_NLS_ISO8859_4 is not set # CONFIG_NLS_ISO8859_5 is not set # CONFIG_NLS_ISO8859_6 is not set # CONFIG_NLS_ISO8859_7 is not set # CONFIG_NLS_ISO8859_9 is not set # CONFIG_NLS_ISO8859_13 is not set # CONFIG_NLS_ISO8859_14 is not set # CONFIG_NLS_ISO8859_15 is not set # CONFIG_NLS_KOI8_R is not set # CONFIG_NLS_KOI8_U is not set CONFIG_NLS_UTF8=y # CONFIG_DLM is not set # # Kernel hacking # CONFIG_TRACE_IRQFLAGS_SUPPORT=y # CONFIG_PRINTK_TIME is not set CONFIG_ALLOW_WARNINGS=y CONFIG_ENABLE_WARN_DEPRECATED=y CONFIG_ENABLE_MUST_CHECK=y CONFIG_FRAME_WARN=2048 CONFIG_MAGIC_SYSRQ=y # CONFIG_UNUSED_SYMBOLS is not set CONFIG_DEBUG_FS=y # CONFIG_HEADERS_CHECK is not set CONFIG_DEBUG_KERNEL=y # CONFIG_DEBUG_SHIRQ is not set # CONFIG_DETECT_SOFTLOCKUP is not set CONFIG_DETECT_HUNG_TASK=y # CONFIG_BOOTPARAM_HUNG_TASK_PANIC is not set CONFIG_BOOTPARAM_HUNG_TASK_PANIC_VALUE=0 # CONFIG_SCHED_DEBUG is not set CONFIG_SCHEDSTATS=y CONFIG_TIMER_STATS=y # CONFIG_DEBUG_OBJECTS is not set # CONFIG_SLUB_DEBUG_ON is not set # CONFIG_SLUB_STATS is not set # CONFIG_DEBUG_RT_MUTEXES is not set # CONFIG_RT_MUTEX_TESTER is not set # CONFIG_DEBUG_SPINLOCK is not set # CONFIG_DEBUG_MUTEXES is not set # CONFIG_DEBUG_LOCK_ALLOC is not set # CONFIG_PROVE_LOCKING is not set # CONFIG_LOCK_STAT is not set # CONFIG_DEBUG_SPINLOCK_SLEEP is not set # CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set CONFIG_STACKTRACE=y # CONFIG_DEBUG_KOBJECT is not set CONFIG_DEBUG_BUGVERBOSE=y # CONFIG_DEBUG_INFO is not set # CONFIG_DEBUG_VM is not set # CONFIG_DEBUG_VIRTUAL is not set # CONFIG_DEBUG_WRITECOUNT is not set CONFIG_DEBUG_MEMORY_INIT=y # CONFIG_DEBUG_LIST is not set # CONFIG_DEBUG_SG is not set # CONFIG_DEBUG_NOTIFIERS is not set CONFIG_ARCH_WANT_FRAME_POINTERS=y CONFIG_FRAME_POINTER=y # CONFIG_BOOT_PRINTK_DELAY is not set # CONFIG_RCU_TORTURE_TEST is not set # CONFIG_RCU_CPU_STALL_DETECTOR is not set # CONFIG_KPROBES_SANITY_TEST is not set # CONFIG_BACKTRACE_SELF_TEST is not set # CONFIG_DEBUG_BLOCK_EXT_DEVT is not set # CONFIG_LKDTM is not set # CONFIG_FAULT_INJECTION is not set # CONFIG_LATENCYTOP is not set CONFIG_SYSCTL_SYSCALL_CHECK=y CONFIG_USER_STACKTRACE_SUPPORT=y CONFIG_NOP_TRACER=y CONFIG_HAVE_FUNCTION_TRACER=y CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y CONFIG_HAVE_FUNCTION_TRACE_MCOUNT_TEST=y CONFIG_HAVE_DYNAMIC_FTRACE=y CONFIG_HAVE_FTRACE_MCOUNT_RECORD=y CONFIG_HAVE_HW_BRANCH_TRACER=y CONFIG_RING_BUFFER=y CONFIG_TRACING=y # # Tracers # # CONFIG_FUNCTION_TRACER is not set # CONFIG_IRQSOFF_TRACER is not set # CONFIG_SYSPROF_TRACER is not set # CONFIG_SCHED_TRACER is not set # CONFIG_CONTEXT_SWITCH_TRACER is not set # CONFIG_BOOT_TRACER is not set # CONFIG_TRACE_BRANCH_PROFILING is not set # CONFIG_POWER_TRACER is not set # CONFIG_STACK_TRACER is not set # CONFIG_HW_BRANCH_TRACER is not set # CONFIG_KMEMTRACE is not set # CONFIG_WORKQUEUE_TRACER is not set CONFIG_BLK_DEV_IO_TRACE=y # CONFIG_FTRACE_STARTUP_TEST is not set # CONFIG_MMIOTRACE is not set # CONFIG_PROVIDE_OHCI1394_DMA_INIT is not set # CONFIG_DYNAMIC_PRINTK_DEBUG is not set # CONFIG_SAMPLES is not set CONFIG_HAVE_ARCH_KGDB=y # CONFIG_KGDB is not set # CONFIG_STRICT_DEVMEM is not set CONFIG_X86_VERBOSE_BOOTUP=y CONFIG_EARLY_PRINTK=y # CONFIG_EARLY_PRINTK_DBGP is not set CONFIG_DEBUG_STACKOVERFLOW=y CONFIG_DEBUG_STACK_USAGE=y # CONFIG_DEBUG_PAGEALLOC is not set # CONFIG_DEBUG_PER_CPU_MAPS is not set # CONFIG_X86_PTDUMP is not set CONFIG_DEBUG_RODATA=y # CONFIG_DEBUG_RODATA_TEST is not set CONFIG_DEBUG_NX_TEST=m # CONFIG_IOMMU_DEBUG is not set CONFIG_HAVE_MMIOTRACE_SUPPORT=y CONFIG_IO_DELAY_TYPE_0X80=0 CONFIG_IO_DELAY_TYPE_0XED=1 CONFIG_IO_DELAY_TYPE_UDELAY=2 CONFIG_IO_DELAY_TYPE_NONE=3 CONFIG_IO_DELAY_0X80=y # CONFIG_IO_DELAY_0XED is not set # CONFIG_IO_DELAY_UDELAY is not set # CONFIG_IO_DELAY_NONE is not set CONFIG_DEFAULT_IO_DELAY_TYPE=0 # CONFIG_DEBUG_BOOT_PARAMS is not set # CONFIG_CPA_DEBUG is not set # CONFIG_OPTIMIZE_INLINING is not set # # Security options # CONFIG_KEYS=y CONFIG_KEYS_DEBUG_PROC_KEYS=y # CONFIG_SECURITY is not set # CONFIG_SECURITYFS is not set CONFIG_SECURITY_FILE_CAPABILITIES=y CONFIG_CRYPTO=y # # Crypto core or helper # # CONFIG_CRYPTO_FIPS is not set CONFIG_CRYPTO_ALGAPI=y CONFIG_CRYPTO_ALGAPI2=y CONFIG_CRYPTO_AEAD=y CONFIG_CRYPTO_AEAD2=y CONFIG_CRYPTO_BLKCIPHER=y CONFIG_CRYPTO_BLKCIPHER2=y CONFIG_CRYPTO_HASH=y CONFIG_CRYPTO_HASH2=y CONFIG_CRYPTO_RNG2=y CONFIG_CRYPTO_MANAGER=y CONFIG_CRYPTO_MANAGER2=y # CONFIG_CRYPTO_GF128MUL is not set # CONFIG_CRYPTO_NULL is not set # CONFIG_CRYPTO_CRYPTD is not set CONFIG_CRYPTO_AUTHENC=y # CONFIG_CRYPTO_TEST is not set # # Authenticated Encryption with Associated Data # # CONFIG_CRYPTO_CCM is not set # CONFIG_CRYPTO_GCM is not set # CONFIG_CRYPTO_SEQIV is not set # # Block modes # CONFIG_CRYPTO_CBC=y # CONFIG_CRYPTO_CTR is not set # CONFIG_CRYPTO_CTS is not set CONFIG_CRYPTO_ECB=y # CONFIG_CRYPTO_LRW is not set # CONFIG_CRYPTO_PCBC is not set # CONFIG_CRYPTO_XTS is not set # # Hash modes # CONFIG_CRYPTO_HMAC=y # CONFIG_CRYPTO_XCBC is not set # # Digest # # CONFIG_CRYPTO_CRC32C is not set # CONFIG_CRYPTO_CRC32C_INTEL is not set # CONFIG_CRYPTO_MD4 is not set CONFIG_CRYPTO_MD5=y # CONFIG_CRYPTO_MICHAEL_MIC is not set # CONFIG_CRYPTO_RMD128 is not set # CONFIG_CRYPTO_RMD160 is not set # CONFIG_CRYPTO_RMD256 is not set # CONFIG_CRYPTO_RMD320 is not set CONFIG_CRYPTO_SHA1=y # CONFIG_CRYPTO_SHA256 is not set # CONFIG_CRYPTO_SHA512 is not set # CONFIG_CRYPTO_TGR192 is not set # CONFIG_CRYPTO_WP512 is not set # # Ciphers # CONFIG_CRYPTO_AES=y # CONFIG_CRYPTO_AES_X86_64 is not set # CONFIG_CRYPTO_ANUBIS is not set CONFIG_CRYPTO_ARC4=y # CONFIG_CRYPTO_BLOWFISH is not set # CONFIG_CRYPTO_CAMELLIA is not set # CONFIG_CRYPTO_CAST5 is not set # CONFIG_CRYPTO_CAST6 is not set CONFIG_CRYPTO_DES=y # CONFIG_CRYPTO_FCRYPT is not set # CONFIG_CRYPTO_KHAZAD is not set # CONFIG_CRYPTO_SALSA20 is not set # CONFIG_CRYPTO_SALSA20_X86_64 is not set # CONFIG_CRYPTO_SEED is not set # CONFIG_CRYPTO_SERPENT is not set # CONFIG_CRYPTO_TEA is not set # CONFIG_CRYPTO_TWOFISH is not set # CONFIG_CRYPTO_TWOFISH_X86_64 is not set # # Compression # # CONFIG_CRYPTO_DEFLATE is not set # CONFIG_CRYPTO_LZO is not set # # Random Number Generation # # CONFIG_CRYPTO_ANSI_CPRNG is not set CONFIG_CRYPTO_HW=y # CONFIG_CRYPTO_DEV_HIFN_795X is not set CONFIG_HAVE_KVM=y CONFIG_VIRTUALIZATION=y # CONFIG_KVM is not set # CONFIG_VIRTIO_PCI is not set # CONFIG_VIRTIO_BALLOON is not set # # Library routines # CONFIG_BITREVERSE=y CONFIG_GENERIC_FIND_FIRST_BIT=y CONFIG_GENERIC_FIND_NEXT_BIT=y CONFIG_GENERIC_FIND_LAST_BIT=y # CONFIG_CRC_CCITT is not set # CONFIG_CRC16 is not set CONFIG_CRC_T10DIF=y # CONFIG_CRC_ITU_T is not set CONFIG_CRC32=y # CONFIG_CRC7 is not set # CONFIG_LIBCRC32C is not set CONFIG_ZLIB_INFLATE=y CONFIG_HAS_IOMEM=y CONFIG_HAS_IOPORT=y CONFIG_HAS_DMA=y Andy> > Unless you''re actually using pci passthrough the changes to > hw/pass-through.[ch] are irrelevant to you. > > Thanks, > Ian. > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel >_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Boris Derzhavets
2009-Feb-23 17:38 UTC
Re: [Xen-devel] HVM guest question (was Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.)
>Is this with dom0 pvops ? Or something else ? Could you post your >config file ?Yes , with dom0 pvops # lofiadm -f ~boris/isos/ubuntuSRV.iso # cd ../vm # cat intrepid.hvm name = "Ubuntu810HVM" builder = "hvm" memory = "2048" disk = [''phy:/dev/loop0,hdc:cdrom,r'',''phy:/dev/sdb7,hda,w''] vif = [ ''type=ioemu,bridge=eth0'' ] device_model = "/usr/lib64/xen/bin/qemu-dm" kernel = "/usr/lib/xen/boot/hvmloader" vnc=1 boot="d" usb=1 usbdevice="tablet" vcpus=1 on_reboot = "restart" on_crash = "restart" # xm create intrepid.hvm --- On Mon, 2/23/09, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote: From: Ian Jackson <Ian.Jackson@eu.citrix.com> Subject: Re: [Xen-devel] HVM guest question (was Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.) To: "bderzhavets@yahoo.com" <bderzhavets@yahoo.com> Cc: "Simon Horman" <horms@verge.net.au>, "Yuji Shimada" <shimada-yxb@necst.nec.co.jp>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com> Date: Monday, February 23, 2009, 11:22 AM Boris Derzhavets writes ("Re: [Xen-devel] HVM guest question (was Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.)"):> [Ian Jackson:] > > Is it working ?...> HVM DomUs failed at startup . Nothing listen at localhost:5900.Is this with dom0 pvops ? Or something else ? Could you post your config file ? Unless you''re actually using pci passthrough the changes to hw/pass-through.[ch] are irrelevant to you. Thanks, Ian. _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
I''ve tried that :-
name = "Ubuntu810HVM"
builder = "hvm"
memory = "2048"
disk =
[''phy:/dev/loop0,hdc:cdrom,r'',''phy:/dev/sdb7,hda,w'']
vif = [ ''type=ioemu,bridge=eth0'' ]
# device_model = "/usr/lib64/xen/bin/qemu-dm"
device_model = "device_model_wrap.sh"
kernel = "/usr/lib/xen/boot/hvmloader"
vnc=1
boot="d"
usb=1
usbdevice="tablet"
vcpus=1
on_reboot = "restart"
on_crash = "restart"
cat device_model_wrap.sh
#!/bin/sh
set -e
exec strace -vvs500 -f -o ~boris/vm/qemu-dm.strace \
/usr/lib64/xen/bin/qemu-dm "$@"
Same behavior. File qemu-dm.strace has not been created at all.
Content of log file under /var/log/xen is just the same.
xm dmesg is much less informative. Just 2-3 HVM lines
--- On Mon, 2/23/09, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote:
From: Ian Jackson <Ian.Jackson@eu.citrix.com>
Subject: Re: [Xen-devel] HVM pvops failures
To: "Andrew Lyon" <andrew.lyon@gmail.com>
Cc: "xen-devel@lists.xensource.com"
<xen-devel@lists.xensource.com>
Date: Monday, February 23, 2009, 11:21 AM
Andrew Lyon writes ("Re: [Xen-devel] HVM guest question (was Re: [PATCH]
ioemu: Cleanup the code of PCI passthrough.)"):> On Mon, Feb 23, 2009 at 2:53 PM, Ian Jackson
<Ian.Jackson@eu.citrix.com> wrote:> > These messages are not very surprising. Is it working ?
>
> No, when try to start HVM on Xen unstable with pv_ops kernel I get this
error:
Ah. This is rather odd. Normally I would hope that xend would report
an exit status. (I haven''t tried pvops with qemu.)
I would suggest running qemu-dm under strace. This can be done easily
enough with a simple wrapper script, something like:
#!/bin/sh
set -e
exec strace -vvs500 -f -o /root/qemu-dm.strace \
/usr/lib/xen/bin/qemu-dm "$@"
and then give the name of the script as device_model in your config file.
Ian.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
[This email is either empty or too large to be displayed at this time]
root@ServerXen331:~# which strace /usr/bin/strace --- On Mon, 2/23/09, Andrew Lyon <andrew.lyon@gmail.com> wrote: From: Andrew Lyon <andrew.lyon@gmail.com> Subject: Re: [Xen-devel] HVM pvops failures To: bderzhavets@yahoo.com Cc: "Ian Jackson" <Ian.Jackson@eu.citrix.com>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com> Date: Monday, February 23, 2009, 2:45 PM On Mon, Feb 23, 2009 at 6:47 PM, Boris Derzhavets <bderzhavets@yahoo.com> wrote:> I''ve tried that :- > > name = "Ubuntu810HVM" > builder = "hvm" > memory = "2048" > disk [''phy:/dev/loop0,hdc:cdrom,r'',''phy:/dev/sdb7,hda,w''] > vif = [ ''type=ioemu,bridge=eth0'' ] > # device_model = "/usr/lib64/xen/bin/qemu-dm" > device_model = "device_model_wrap.sh" > kernel = "/usr/lib/xen/boot/hvmloader" > vnc=1 > boot="d" > usb=1 > usbdevice="tablet" > vcpus=1 > on_reboot = "restart" > on_crash = "restart" > > cat device_model_wrap.sh > #!/bin/sh > set -e > exec strace -vvs500 -f -o ~boris/vm/qemu-dm.strace \ > /usr/lib64/xen/bin/qemu-dm "$@" > > > Same behavior. File qemu-dm.strace has not been created at all. > Content of log file under /var/log/xen is just the same. > xm dmesg is much less informative. Just 2-3 HVM linesWorked for me, I''ve attached the 1mb strace logfile. Perhaps you don''t have strace installed? Andy> > > --- On Mon, 2/23/09, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote: > > From: Ian Jackson <Ian.Jackson@eu.citrix.com> > Subject: Re: [Xen-devel] HVM pvops failures > To: "Andrew Lyon" <andrew.lyon@gmail.com> > Cc: "xen-devel@lists.xensource.com"<xen-devel@lists.xensource.com>> Date: Monday, February 23, 2009, 11:21 AM > > Andrew Lyon writes ("Re: [Xen-devel] HVM guest question (was Re:[PATCH]> ioemu: Cleanup the code of PCI passthrough.)"): >> On Mon, Feb 23, 2009 at 2:53 PM, Ian Jackson > <Ian.Jackson@eu.citrix.com> wrote: >> > These messages are not very surprising. Is it working ? >> >> No, when try to start HVM on Xen unstable with pv_ops kernel I getthis> error: > > Ah. This is rather odd. Normally I would hope that xend would report > an exit status. (I haven''t tried pvops with > qemu.) > > I would suggest running qemu-dm under strace. This can be done easily > enough with a simple wrapper script, something like: > #!/bin/sh > set -e > exec strace -vvs500 -f -o /root/qemu-dm.strace \ > /usr/lib/xen/bin/qemu-dm "$@" > and then give the name of the script as device_model in your config file. > > Ian. > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel > >_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Simon Horman
2009-Feb-23 22:30 UTC
Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.
On Mon, Feb 23, 2009 at 11:36:01AM +0000, Ian Jackson wrote:> Simon Horman writes ("Re: [Xen-devel] Re: [PATCH] ioemu: Cleanup the code of PCI passthrough."): > > On Mon, Feb 23, 2009 at 10:40:22AM +0900, Yuji Shimada wrote: > > > Signed-off-by: Yuji Shimada <shimada-yxb@necst.nec.co.jp> > > > > Tested-by: Simon Horman <horms@verge.net.au> > > Thanks, I have applied this. > > The problem causing it to be rejected was that hw/passthrough.[ch] and > hw/pt-msi.[ch] were full of trailing whitespace, which Yuji Shimada''s > mailer evidently removes. I think the mailer was right and the code > was wrong. > > So I have removed all of that trailing whitespace with a trivial perl > one-liner and then committed the cleanup patch on top. I haven''t > tested the pass-through but the tree does build.It seems to work in my environment (2.6.27.5 dom0, not pv_ops). -- Simon Horman VA Linux Systems Japan K.K., Sydney, Australia Satellite Office H: www.vergenet.net/~horms/ W: www.valinux.co.jp/en _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Ian Jackson wrote:> Andrew Lyon writes ("Re: [Xen-devel] HVM guest question (was Re: [PATCH] ioemu: Cleanup the code of PCI passthrough.)"): > >> On Mon, Feb 23, 2009 at 2:53 PM, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote: >> >>> These messages are not very surprising. Is it working ? >>> >> No, when try to start HVM on Xen unstable with pv_ops kernel I get this error: >> > > Ah. This is rather odd. Normally I would hope that xend would report > an exit status. (I haven''t tried pvops with qemu.) > >Hm, I''m getting: [2009-02-23 15:26:18 4380] WARNING (image:482) domain win7: device model failure: pid 5409: died due to signal 7; see /var/log/xen/qemu-dm-win7.log Hm, signal 7 - SIGBUS. I wonder if Using stub domains doesn''t work either.> I would suggest running qemu-dm under strace. This can be done easily > enough with a simple wrapper script, something like: > #!/bin/sh > set -e > exec strace -vvs500 -f -o /root/qemu-dm.strace \ > /usr/lib/xen/bin/qemu-dm "$@" > and then give the name of the script as device_model in your config file. >I see: ... 5079 ioctl(10, EVIOCGKEYCODE, 0x7fffdfd52b70) = 0 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 539747423}) = 0 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 539837298}) = 0 5079 select(14, [3 6 10 11 13], [], [], {0, 10000}) = 1 (in [10], left {0, 9995}) 5079 read(10, "\36\0\0\0"..., 4) = 4 5079 write(10, "\36\0\0\0"..., 4) = 4 5079 ioctl(10, EVIOCGKEYCODE, 0x7fffdfd52b70) = 0 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 540495964}) = 0 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 540591278}) = 0 5079 select(14, [3 6 10 11 13], [], [], {0, 10000}) = 1 (in [10], left {0, 9995}) 5079 read(10, "\36\0\0\0"..., 4) = 4 5079 write(10, "\36\0\0\0"..., 4) = 4 5079 mmap(NULL, 1048576, PROT_READ|PROT_WRITE, MAP_SHARED, 4, 0) = 0x7f1ad5f2b000 5079 ioctl(4, SNDCTL_DSP_STEREO, 0x7fffdfd52230) = 0 5079 --- SIGBUS (Bus error) @ 0 (0) --- 5157 +++ killed by SIGBUS +++ This mmap and ioctl is from /proc/xen/privcmd. J _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Boris Derzhavets
2009-Feb-24 11:21 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
[This email is either empty or too large to be displayed at this time]
Boris Derzhavets
2009-Feb-24 11:38 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
[This email is either empty or too large to be displayed at this time]
Andrew Lyon
2009-Feb-25 14:28 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
On Tue, Feb 24, 2009 at 11:38 AM, Boris Derzhavets <bderzhavets@yahoo.com> wrote:> I fixed error in hvm profile and got a similar qemu-dm.strace ( > /usr/lib64/.../qemu-dm). > > --- On Mon, 2/23/09, Jeremy Fitzhardinge <jeremy@goop.org> wrote: > > From: Jeremy Fitzhardinge <jeremy@goop.org> > Subject: Re: [Xen-devel] HVM pvops failures > To: "Ian Jackson" <Ian.Jackson@eu.citrix.com> > Cc: "Andrew Lyon" <andrew.lyon@gmail.com>, "xen-devel@lists.xensource.com" > <xen-devel@lists.xensource.com>, "Ian Campbell" <Ian.Campbell@citrix.com> > Date: Monday, February 23, 2009, 7:12 PM > > Ian Jackson wrote: >> Andrew Lyon writes ("Re: [Xen-devel] HVM guest question (was Re: > [PATCH] ioemu: Cleanup the code of PCI passthrough.)"): >> >>> On Mon, Feb 23, 2009 at 2:53 PM, Ian > Jackson > <Ian.Jackson@eu.citrix.com> wrote: >>> >>>> These messages are not very surprising. Is it working ? >>>> >>> No, when try to start HVM on Xen unstable with pv_ops kernel I get > this error: >>> >> >> Ah. This is rather odd. Normally I would hope that xend would report >> an exit status. (I haven''t tried pvops with qemu.) >> >> > Hm, I''m getting: > [2009-02-23 15:26:18 4380] WARNING (image:482) domain win7: device model > failure: pid 5409: died due to signal 7; see /var/log/xen/qemu-dm-win7.log > > Hm, signal 7 - SIGBUS. I wonder if > > Using stub domains doesn''t work either. > >> I would suggest running qemu-dm under strace. This can be done easily >> enough with a simple wrapper script, something like: >> #!/bin/sh >> set -e >> exec strace -vvs500 -f -o /root/qemu-dm.strace \ >> > /usr/lib/xen/bin/qemu-dm "$@" >> and then give the name of the script as device_model in your config file.Is there anything more I can do to help debug this problem? I am eager to do more testing with pv_ops and I have time to do it at the moment, but hvm support is currently broken so there is little I can do with my test box. Thx Andy>> > I see: > > ... > 5079 ioctl(10, EVIOCGKEYCODE, 0x7fffdfd52b70) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 539747423}) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 539837298}) = 0 > 5079 select(14, [3 6 10 11 13], [], [], {0, 10000}) = 1 (in [10], left {0, > 9995}) > 5079 read(10, "\36\0\0\0"..., 4) = 4 > 5079 write(10, "\36\0\0\0"..., 4) = 4 > 5079 ioctl(10, EVIOCGKEYCODE, 0x7fffdfd52b70) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 540495964}) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 540591278}) = 0 > 5079 select(14, [3 6 10 11 13], [], [], {0, 10000}) = 1 (in [10], left {0, > 9995}) > 5079 read(10, "\36\0\0\0"..., 4) = 4 > 5079 write(10, "\36\0\0\0"..., 4) = 4 > 5079 mmap(NULL, 1048576, PROT_READ|PROT_WRITE, MAP_SHARED, 4, 0) > 0x7f1ad5f2b000 > 5079 > ioctl(4, SNDCTL_DSP_STEREO, 0x7fffdfd52230) = 0 > 5079 --- SIGBUS (Bus error) @ 0 (0) --- > 5157 +++ killed by SIGBUS +++ > > > This mmap and ioctl is from /proc/xen/privcmd. > > J > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel > >_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Boris Derzhavets
2009-Feb-25 15:10 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
Hi Andy, Stubdoms fail as well ( as Jeremy suspected). QEMU is obviously important issue for pv-ops in Dom0. Boris. --- On Wed, 2/25/09, Andrew Lyon <andrew.lyon@gmail.com> wrote: From: Andrew Lyon <andrew.lyon@gmail.com> Subject: Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained) To: "Boris Derzhavets" <bderzhavets@yahoo.com> Cc: "Jeremy Fitzhardinge" <jeremy@goop.org>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>, "Ian Jackson" <Ian.Jackson@eu.citrix.com>, "Ian Campbell" <Ian.Campbell@citrix.com> Date: Wednesday, February 25, 2009, 9:28 AM On Tue, Feb 24, 2009 at 11:38 AM, Boris Derzhavets <bderzhavets@yahoo.com> wrote:> I fixed error in hvm profile and got a similar qemu-dm.strace ( > /usr/lib64/.../qemu-dm). > > --- On Mon, 2/23/09, Jeremy Fitzhardinge <jeremy@goop.org> wrote: > > From: Jeremy Fitzhardinge <jeremy@goop.org> > Subject: Re: [Xen-devel] HVM pvops failures > To: "Ian Jackson" <Ian.Jackson@eu.citrix.com> > Cc: "Andrew Lyon" <andrew.lyon@gmail.com>,"xen-devel@lists.xensource.com"> <xen-devel@lists.xensource.com>, "Ian Campbell"<Ian.Campbell@citrix.com>> Date: Monday, February 23, 2009, 7:12 PM > > Ian Jackson wrote: >> Andrew Lyon writes ("Re: [Xen-devel] HVM guest question (was Re: > [PATCH] ioemu: Cleanup the code of PCI passthrough.)"): >> >>> On Mon, Feb 23, 2009 at 2:53 PM, Ian > Jackson > <Ian.Jackson@eu.citrix.com> wrote: >>> >>>> These messages are not very surprising. Is it working ? >>>> >>> No, when try to start HVM on Xen unstable with pv_ops kernel I get > this error: >>> >> >> Ah. This is rather odd. Normally I would hope that xend would report >> an exit status. (I haven''t tried pvops with qemu.) >> >> > Hm, I''m getting: > [2009-02-23 15:26:18 4380] WARNING (image:482) domain win7: device model > failure: pid 5409: died due to signal 7; see /var/log/xen/qemu-dm-win7.log > > Hm, signal 7 - SIGBUS. I wonder if > > Using stub domains doesn''t work either. > >> I would suggest running qemu-dm under strace. This can be done easily >> enough with a simple wrapper script, something like: >> #!/bin/sh >> set -e >> exec strace -vvs500 -f -o /root/qemu-dm.strace \ >> > /usr/lib/xen/bin/qemu-dm "$@" >> and then give the name of the script as device_model in your configfile. Is there anything more I can do to help debug this problem? I am eager to do more testing with pv_ops and I have time to do it at the moment, but hvm support is currently broken so there is little I can do with my test box. Thx Andy>> > I see: > > ... > 5079 ioctl(10, EVIOCGKEYCODE, 0x7fffdfd52b70) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 539747423}) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 539837298}) = 0 > 5079 select(14, [3 6 10 11 13], [], [], {0, 10000}) = 1 (in [10], left{0,> 9995}) > 5079 read(10, "\36\0\0\0"..., 4) = 4 > 5079 write(10, "\36\0\0\0"..., 4) = 4 > 5079 ioctl(10, EVIOCGKEYCODE, 0x7fffdfd52b70) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 540495964}) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 540591278}) = 0 > 5079 select(14, [3 6 10 11 13], [], [], {0, 10000}) = 1 (in [10], left{0,> 9995}) > 5079 read(10, "\36\0\0\0"..., 4) = 4 > 5079 write(10, "\36\0\0\0"..., 4) = 4 > 5079 mmap(NULL, 1048576, PROT_READ|PROT_WRITE, MAP_SHARED, 4, 0) > 0x7f1ad5f2b000 > 5079 > ioctl(4, SNDCTL_DSP_STEREO, 0x7fffdfd52230) = 0 > 5079 --- SIGBUS (Bus error) @ 0 (0) --- > 5157 +++ killed by SIGBUS +++ > > > This mmap and ioctl is from /proc/xen/privcmd. > > J > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel > >_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Boris Derzhavets
2009-Feb-25 15:41 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
1.You can install a lot of PV DomUs i guess via two pygrub profiles, first one to install DomU, second one to load DomU, for guests having distros on DVDs with xen-inified or pv_ops (DomU) enabled kernel. It works fine, through my experience. Details here:- http://lxer.com/module/newswire/view/112300/index.html F10 has been tested. 2. For Ubuntu( or Debian) DomUs "debootstrap port" to your Xen Unstable Dom0 will allow straight forward installations. I prefer trick with HVM image prebuilt for corresponding PV DomU pygrub''s profile at Xen 3.3.X Dom0s. However, now i learned debootstrap (debian tool) and liked it very much ;). Details here:- http://lxer.com/module/newswire/view/114465/index.html Ubuntu Intrepid Server (64 bit) has been tested 3. You can try to install OpenSolaris 2008/11 or Solaris Nevada PV DomU on ZFS. That''s really tuff. Pygrub won''t help you to read Sun''s the most recent ZFS images. Details here:- http://www.neuhalfen.name/drupal/node/3 --- On Wed, 2/25/09, Andrew Lyon <andrew.lyon@gmail.com> wrote: From: Andrew Lyon <andrew.lyon@gmail.com> Subject: Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained) To: "Boris Derzhavets" <bderzhavets@yahoo.com> Cc: "Jeremy Fitzhardinge" <jeremy@goop.org>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>, "Ian Jackson" <Ian.Jackson@eu.citrix.com>, "Ian Campbell" <Ian.Campbell@citrix.com> Date: Wednesday, February 25, 2009, 9:28 AM On Tue, Feb 24, 2009 at 11:38 AM, Boris Derzhavets <bderzhavets@yahoo.com> wrote:> I fixed error in hvm profile and got a similar qemu-dm.strace ( > /usr/lib64/.../qemu-dm). > > --- On Mon, 2/23/09, Jeremy Fitzhardinge <jeremy@goop.org> wrote: > > From: Jeremy Fitzhardinge <jeremy@goop.org> > Subject: Re: [Xen-devel] HVM pvops failures > To: "Ian Jackson" <Ian.Jackson@eu.citrix.com> > Cc: "Andrew Lyon" <andrew.lyon@gmail.com>,"xen-devel@lists.xensource.com"> <xen-devel@lists.xensource.com>, "Ian Campbell"<Ian.Campbell@citrix.com>> Date: Monday, February 23, 2009, 7:12 PM > > Ian Jackson wrote: >> Andrew Lyon writes ("Re: [Xen-devel] HVM guest question (was Re: > [PATCH] ioemu: Cleanup the code of PCI passthrough.)"): >> >>> On Mon, Feb 23, 2009 at 2:53 PM, Ian > Jackson > <Ian.Jackson@eu.citrix.com> wrote: >>> >>>> These messages are not very surprising. Is it working ? >>>> >>> No, when try to start HVM on Xen unstable with pv_ops kernel I get > this error: >>> >> >> Ah. This is rather odd. Normally I would hope that xend would report >> an exit status. (I haven''t tried pvops with qemu.) >> >> > Hm, I''m getting: > [2009-02-23 15:26:18 4380] WARNING (image:482) domain win7: device model > failure: pid 5409: died due to signal 7; see /var/log/xen/qemu-dm-win7.log > > Hm, signal 7 - SIGBUS. I wonder if > > Using stub domains doesn''t work either. > >> I would suggest running qemu-dm under strace. This can be done easily >> enough with a simple wrapper script, something like: >> #!/bin/sh >> set -e >> exec strace -vvs500 -f -o /root/qemu-dm.strace \ >> > /usr/lib/xen/bin/qemu-dm "$@" >> and then give the name of the script as device_model in your configfile. Is there anything more I can do to help debug this problem? I am eager to do more testing with pv_ops and I have time to do it at the moment, but hvm support is currently broken so there is little I can do with my test box. Thx Andy>> > I see: > > ... > 5079 ioctl(10, EVIOCGKEYCODE, 0x7fffdfd52b70) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 539747423}) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 539837298}) = 0 > 5079 select(14, [3 6 10 11 13], [], [], {0, 10000}) = 1 (in [10], left{0,> 9995}) > 5079 read(10, "\36\0\0\0"..., 4) = 4 > 5079 write(10, "\36\0\0\0"..., 4) = 4 > 5079 ioctl(10, EVIOCGKEYCODE, 0x7fffdfd52b70) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 540495964}) = 0 > 5079 clock_gettime(CLOCK_MONOTONIC, {1324, 540591278}) = 0 > 5079 select(14, [3 6 10 11 13], [], [], {0, 10000}) = 1 (in [10], left{0,> 9995}) > 5079 read(10, "\36\0\0\0"..., 4) = 4 > 5079 write(10, "\36\0\0\0"..., 4) = 4 > 5079 mmap(NULL, 1048576, PROT_READ|PROT_WRITE, MAP_SHARED, 4, 0) > 0x7f1ad5f2b000 > 5079 > ioctl(4, SNDCTL_DSP_STEREO, 0x7fffdfd52230) = 0 > 5079 --- SIGBUS (Bus error) @ 0 (0) --- > 5157 +++ killed by SIGBUS +++ > > > This mmap and ioctl is from /proc/xen/privcmd. > > J > > _______________________________________________ > Xen-devel mailing list > Xen-devel@lists.xensource.com > http://lists.xensource.com/xen-devel > >_______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Jeremy Fitzhardinge
2009-Feb-25 21:02 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
Andrew Lyon wrote:> On Tue, Feb 24, 2009 at 11:38 AM, Boris Derzhavets > <bderzhavets@yahoo.com> wrote: > >> I fixed error in hvm profile and got a similar qemu-dm.strace ( >> /usr/lib64/.../qemu-dm). >> >> --- On Mon, 2/23/09, Jeremy Fitzhardinge <jeremy@goop.org> wrote: >> >> From: Jeremy Fitzhardinge <jeremy@goop.org> >> Subject: Re: [Xen-devel] HVM pvops failures >> To: "Ian Jackson" <Ian.Jackson@eu.citrix.com> >> Cc: "Andrew Lyon" <andrew.lyon@gmail.com>, "xen-devel@lists.xensource.com" >> <xen-devel@lists.xensource.com>, "Ian Campbell" <Ian.Campbell@citrix.com> >> Date: Monday, February 23, 2009, 7:12 PM >> >> Ian Jackson wrote: >> >>> Andrew Lyon writes ("Re: [Xen-devel] HVM guest question (was Re: >>> >> [PATCH] ioemu: Cleanup the code of PCI passthrough.)"): >> >>>> On Mon, Feb 23, 2009 at 2:53 PM, Ian >>>> >> Jackson >> <Ian.Jackson@eu.citrix.com> wrote: >> >>>>> These messages are not very surprising. Is it working ? >>>>> >>>>> >>>> No, when try to start HVM on Xen unstable with pv_ops kernel I get >>>> >> this error: >> >>> Ah. This is rather odd. Normally I would hope that xend would report >>> an exit status. (I haven''t tried pvops with qemu.) >>> >>> >>> >> Hm, I''m getting: >> [2009-02-23 15:26:18 4380] WARNING (image:482) domain win7: device model >> failure: pid 5409: died due to signal 7; see /var/log/xen/qemu-dm-win7.log >> >> Hm, signal 7 - SIGBUS. I wonder if >> >> Using stub domains doesn''t work either. >> >> >>> I would suggest running qemu-dm under strace. This can be done easily >>> enough with a simple wrapper script, something like: >>> #!/bin/sh >>> set -e >>> exec strace -vvs500 -f -o /root/qemu-dm.strace \ >>> >>> >> /usr/lib/xen/bin/qemu-dm "$@" >> >>> and then give the name of the script as device_model in your config file. >>> > > > Is there anything more I can do to help debug this problem? I am eager > to do more testing with pv_ops and I have time to do it at the moment, > but hvm support is currently broken so there is little I can do with > my test box. >I was hoping Ian J would pop up and say "Its broken like this! Fix it like this!". There does appear to be some incompatibility between the pvops dom0 and qemu which is causing this SIGBUS; it would be really useful to know what page qemu is trying to access. It might be a problem in the pvops /proc/xen/privcmd implementation, or it could be a bug in qemu which happens to work with 2.6.18. The alternative is to try stubdom, which should avoid the issue. I haven''t had much success in making it work, but it looks like I was not starting fs-backend. I''ll try again shortly. J _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Jeremy Fitzhardinge
2009-Feb-25 23:57 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
Boris Derzhavets wrote:> Hi Andy, > > Stubdoms fail as well ( as Jeremy suspected). >I made more progress when I ran "fs-backend" first, and set up proper disk and vif entries. Now I''m getting to the state where the domain and its stub domains are running, but the main domain is doing nothing in its zilch state (no state flags in xm list, no cpu consumption). There''s a window, but it has no output (not even bios, so it isn''t starting at all). J _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Boris Derzhavets
2009-Feb-26 06:47 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
>There''s a window, but it has no output (not even bios, so >it isn''t starting at all).Same results --- On Wed, 2/25/09, Jeremy Fitzhardinge <jeremy@goop.org> wrote: From: Jeremy Fitzhardinge <jeremy@goop.org> Subject: Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained) To: bderzhavets@yahoo.com Cc: "Andrew Lyon" <andrew.lyon@gmail.com>, "Ian Jackson" <Ian.Jackson@eu.citrix.com>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>, "Ian Campbell" <Ian.Campbell@citrix.com> Date: Wednesday, February 25, 2009, 6:57 PM Boris Derzhavets wrote:> Hi Andy, > > Stubdoms fail as well ( as Jeremy suspected). >I made more progress when I ran "fs-backend" first, and set up proper disk and vif entries. Now I''m getting to the state where the domain and its stub domains are running, but the main domain is doing nothing in its zilch state (no state flags in xm list, no cpu consumption). There''s a window, but it has no output (not even bios, so it isn''t starting at all). J _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Ian Jackson
2009-Feb-26 11:35 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
Jeremy Fitzhardinge writes ("Re: [Xen-devel] HVM pvops failures (one more
qemu-dm.strace obtained)"):> I was hoping Ian J would pop up and say "Its broken like this! Fix it
> like this!".
Yes, when I have a moment I''ll try it myself but I''ve been
buried in
the bowels of a nightmare USB emulation. Soon I''ll know whether the
latter works and thus whether I have any time to dig into pvops.
Ian.
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xensource.com
http://lists.xensource.com/xen-devel
Andrew Lyon
2009-Mar-03 10:55 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
On Thu, Feb 26, 2009 at 11:35 AM, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote:> Jeremy Fitzhardinge writes ("Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)"): >> I was hoping Ian J would pop up and say "Its broken like this! Fix it >> like this!". > > Yes, when I have a moment I''ll try it myself but I''ve been buried in > the bowels of a nightmare USB emulation. Soon I''ll know whether the > latter works and thus whether I have any time to dig into pvops. > > Ian. >Has anybody made any progress on the qemu-dm / hvm issue with pv_ops? I spent most of yesterday going through the strace logs but I cannot see why it fails as it does. pv domU seems to work ok, but I dont have any need to run pv. andy _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Boris Derzhavets
2009-Mar-03 11:27 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
Quoting Stefano Stabellini:- Hi all, this patch series imports from qemu mainstream the recent DisplayState interface changes. The new interface allows to have multiple frontends running at the same time (vnc and sdl), however this series does not enable it in xend yet. Most of the patches are just backports from qemu mainstream, adapted to qemu-xen whenever was necessary. The last two patches are not in qemu mainstream yet: - patch 12 of 13 deals with changes to the xenfb frontend and backend; - patch 13 of 13 introduces a DisplaySurface allocator interface that allows display frontends (like xenfbfront and sdl) to provide the DisplaySurface buffer to graphic devices whenever necessary. Currently it is used only by xenfbfront but it is also useful for sdl. [Xen-devel] [PATCH 13 of 13] introducing a DisplayAllocator interface Mon, 3/2/09 18KB Read Stefano Stabellini [Xen-devel] [PATCH 12 of 13] fix xenfb frontend and backend Mon, 3/2/09 12KB Read Stefano Stabellini [Xen-devel] [PATCH 11 of 13] serial: open a null device if the CharDriverState argument is null Mon, 3/2/09 6KB Read Stefano Stabellini [Xen-devel] [PATCH 10 of 13] add an init function parameter to qemu_chr_open() Mon, 3/2/09 9KB Read Stefano Stabellini [Xen-devel] [PATCH 9 of 13] fix screendump Mon, 3/2/09 9KB Read Stefano Stabellini [Xen-devel] [PATCH 6 of 13] graphical_console_init change Mon, 3/2/09 97KB Read Stefano Stabellini [Xen-devel] [PATCH 4 of 13] DisplayState interface change Mon, 3/2/09 70KB Read Stefano Stabellini [Xen-devel] [PATCH 2 of 13] Introduce accessors for DisplayState Mon, 3/2/09 44KB Read Stefano Stabellini [Xen-devel] [PATCH 2 of 13] Introduce accessors for DisplayState Mon, 3/2/09 44KB Read Stefano Stabellini [Xen-devel] [PATCH 8 of 13] Coalesce virtual console screen updates. Mon, 3/2/09 9KB Read Stefano Stabellini [Xen-devel] [PATCH 7 of 13] fix console switch Mon, 3/2/09 7KB Read Stefano Stabellini [Xen-devel] [PATCH 5 of 13] exploiting the new interface in vnc.c Mon, 3/2/09 26KB Read Stefano Stabellini [Xen-devel] [PATCH 3 of 13] remove bgr Mon, 3/2/09 9KB Read Stefano Stabellini [Xen-devel] [PATCH 1 of 13] Implement "info chardev" command. (Gerd Hoffmann) Mon, 3/2/09 14KB Read Stefano Stabellini [Xen-devel] [PATCH 0 of 13] DisplayState changes Mon, 3/2/09 5KB --- On Tue, 3/3/09, Andrew Lyon <andrew.lyon@gmail.com> wrote: From: Andrew Lyon <andrew.lyon@gmail.com> Subject: Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained) To: "Ian Jackson" <Ian.Jackson@eu.citrix.com> Cc: "Ian Campbell" <Ian.Campbell@eu.citrix.com>, "Jeremy Fitzhardinge" <jeremy@goop.org>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>, "Boris Derzhavets" <bderzhavets@yahoo.com> Date: Tuesday, March 3, 2009, 5:55 AM On Thu, Feb 26, 2009 at 11:35 AM, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote:> Jeremy Fitzhardinge writes ("Re: [Xen-devel] HVM pvops failures (onemore qemu-dm.strace obtained)"):>> I was hoping Ian J would pop up and say "Its broken like this!Fix it>> like this!". > > Yes, when I have a moment I''ll try it myself but I''ve been buriedin> the bowels of a nightmare USB emulation. Soon I''ll know whether the > latter works and thus whether I have any time to dig into pvops. > > Ian. >Has anybody made any progress on the qemu-dm / hvm issue with pv_ops? I spent most of yesterday going through the strace logs but I cannot see why it fails as it does. pv domU seems to work ok, but I dont have any need to run pv. andy _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Jeremy Fitzhardinge
2009-Mar-03 17:41 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
Andrew Lyon wrote:> On Thu, Feb 26, 2009 at 11:35 AM, Ian Jackson <Ian.Jackson@eu.citrix.com> wrote: > >> Jeremy Fitzhardinge writes ("Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)"): >> >>> I was hoping Ian J would pop up and say "Its broken like this! Fix it >>> like this!". >>> >> Yes, when I have a moment I''ll try it myself but I''ve been buried in >> the bowels of a nightmare USB emulation. Soon I''ll know whether the >> latter works and thus whether I have any time to dig into pvops. >> >> Ian. >> >> > > Has anybody made any progress on the qemu-dm / hvm issue with pv_ops? > I spent most of yesterday going through the strace logs but I cannot > see why it fails as it does. >Thanks for looking into this. The crash is a SIGBUS in qemu, shortly after an mmap of /proc/xen/privcmd, which is a suspicious combination. The SIGBUS means we managed to create a mapping where the kernel thinks there are no backing pages (at least in part). It would be useful to know if any memory accesses to the privcmd mapping succeed, and what the offset of the failing one is. (Assuming the SIGBUS is related to a privcmd mapping at all.) I don''t think privcmd mappings can be completely broken, because the qemu backend for pvfb works fine, and I assume that uses that path to map the framebuffer... Also, have you tried using stub domains? They should have no dependence on the dom0 kernel at all, so in theory they should work regardless. J _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Andrew Lyon
2009-Mar-18 08:17 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
On Tue, Mar 3, 2009 at 5:41 PM, Jeremy Fitzhardinge <jeremy@goop.org> wrote:> Andrew Lyon wrote: >> >> On Thu, Feb 26, 2009 at 11:35 AM, Ian Jackson <Ian.Jackson@eu.citrix.com> >> wrote: >> >>> >>> Jeremy Fitzhardinge writes ("Re: [Xen-devel] HVM pvops failures (one more >>> qemu-dm.strace obtained)"): >>> >>>> >>>> I was hoping Ian J would pop up and say "Its broken like this! Fix it >>>> like this!". >>>> >>> >>> Yes, when I have a moment I''ll try it myself but I''ve been buried in >>> the bowels of a nightmare USB emulation. Soon I''ll know whether the >>> latter works and thus whether I have any time to dig into pvops. >>> >>> Ian. >>> >>> >> >> Has anybody made any progress on the qemu-dm / hvm issue with pv_ops? >> I spent most of yesterday going through the strace logs but I cannot >> see why it fails as it does. >> > > Thanks for looking into this. The crash is a SIGBUS in qemu, shortly after > an mmap of /proc/xen/privcmd, which is a suspicious combination. The SIGBUS > means we managed to create a mapping where the kernel thinks there are no > backing pages (at least in part). It would be useful to know if any memory > accesses to the privcmd mapping succeed, and what the offset of the failing > one is. (Assuming the SIGBUS is related to a privcmd mapping at all.) > > I don''t think privcmd mappings can be completely broken, because the qemu > backend for pvfb works fine, and I assume that uses that path to map the > framebuffer... > > Also, have you tried using stub domains? They should have no dependence on > the dom0 kernel at all, so in theory they should work regardless. > > J >I tried Stub domains yesterday but as soon as I "xm create" the system locked up, I could still ping it but no response on the serial console and ssh was responsive, very strange.. I''ve never seen a system ping but have unresponsive console. Can we try to debug the problem with hvm on pv_ops? Andy _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Boris Derzhavets
2009-Mar-18 14:42 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
Ping is based on ICMP. TCP (UDP) services might fail to reach the host. Failure of cheksum offloading on the second host may be the first example. But here it doesn''t seem to be the case. "tcpdump" on Xen host may help after issue comes up. See what happens to ssh packages when they arrive. Boris. --- On Wed, 3/18/09, Andrew Lyon <andrew.lyon@gmail.com> wrote: From: Andrew Lyon <andrew.lyon@gmail.com> Subject: Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained) To: "Jeremy Fitzhardinge" <jeremy@goop.org> Cc: "Ian Campbell" <Ian.Campbell@eu.citrix.com>, "Boris Derzhavets" <bderzhavets@yahoo.com>, "xen-devel@lists.xensource.com" <xen-devel@lists.xensource.com>, "Ian Jackson" <Ian.Jackson@eu.citrix.com> Date: Wednesday, March 18, 2009, 4:17 AM On Tue, Mar 3, 2009 at 5:41 PM, Jeremy Fitzhardinge <jeremy@goop.org> wrote:> Andrew Lyon wrote: >> >> On Thu, Feb 26, 2009 at 11:35 AM, Ian Jackson<Ian.Jackson@eu.citrix.com>>> wrote: >> >>> >>> Jeremy Fitzhardinge writes ("Re: [Xen-devel] HVM pvopsfailures (one more>>> qemu-dm.strace obtained)"): >>> >>>> >>>> I was hoping Ian J would pop up and say "Its broken likethis! Fix it>>>> like this!". >>>> >>> >>> Yes, when I have a moment I''ll try it myself but I''ve beenburied in>>> the bowels of a nightmare USB emulation. Soon I''ll knowwhether the>>> latter works and thus whether I have any time to dig into pvops. >>> >>> Ian. >>> >>> >> >> Has anybody made any progress on the qemu-dm / hvm issue with pv_ops? >> I spent most of yesterday going through the strace logs but I cannot >> see why it fails as it does. >> > > Thanks for looking into this. The crash is a SIGBUS in qemu, shortlyafter> an mmap of /proc/xen/privcmd, which is a suspicious combination. TheSIGBUS> means we managed to create a mapping where the kernel thinks there are no > backing pages (at least in part). It would be useful to know if anymemory> accesses to the privcmd mapping succeed, and what the offset of thefailing> one is. (Assuming the SIGBUS is related to a privcmd mapping at all.) > > I don''t think privcmd mappings can be completely broken, because theqemu> backend for pvfb works fine, and I assume that uses that path to map the > framebuffer... > > Also, have you tried using stub domains? They should have no dependenceon> the dom0 kernel at all, so in theory they should work regardless. > > J >I tried Stub domains yesterday but as soon as I "xm create" the system locked up, I could still ping it but no response on the serial console and ssh was responsive, very strange.. I''ve never seen a system ping but have unresponsive console. Can we try to debug the problem with hvm on pv_ops? Andy _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Andrew Lyon
2009-Mar-23 14:15 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
On Wed, Mar 18, 2009 at 2:42 PM, Boris Derzhavets <bderzhavets@yahoo.com> wrote:> Ping is based on ICMP. > > TCP (UDP) services might fail to reach the host. > Failure of cheksum offloading on the second host may be the first example. > But here it doesn''t seem to be the case. > "tcpdump" on Xen host may help after issue comes up. > See what happens to ssh packages when they arrive. > > Boris.It is not a network problem, the system completely locks up when I try to start a stubdom, even the local keyboard and vga is not responsive. Andy _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
Jeremy Fitzhardinge
2009-Mar-23 18:07 UTC
Re: [Xen-devel] HVM pvops failures (one more qemu-dm.strace obtained)
Andrew Lyon wrote:> I tried Stub domains yesterday but as soon as I "xm create" the system > locked up, I could still ping it but no response on the serial console > and ssh was responsive, very strange.. I''ve never seen a system ping > but have unresponsive console. > > Can we try to debug the problem with hvm on pv_ops? >I haven''t seen anything like that before. All I''ve seen is that domain creation fails, but dom0 is unaffected. On the other hand, I haven''t had a chance to try out hvm lately, as I''ve been working on other things. J _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel