Keir (and anyone else with an opinion on this :), Given that you have suggested that patching from the hypervisor might have synchronisation issues, my current thought on a mechanism for signalling a DomU when a TPR write occurs is this: . DomU allocates a page and makes a hypercall to the hypervisor saying "put info about TPR writes here" and use this event channel to signal me. . When a TPR write occurs, the hypervisor fills in the entry in the buffer nominated above and sets a flag. Until the flag is cleared, the hypervisor does no further signalling. . The guest sees the event (via the interrupt - same as any other event), patches the kernel as appropriate, then clears the flag . Repeat until all the places are patched. Obviously a number of iterations will be required before all the patching is done, but I don''t think that''s a problem. Patching would occur in the DomU with all processors at HIGH_LEVEL (interrupts disabled). Does that sound acceptable? Thanks James _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
On 01/01/2009 00:57, "James Harper" <james.harper@bendigoit.com.au> wrote:> Obviously a number of iterations will be required before all the > patching is done, but I don''t think that''s a problem. Patching would > occur in the DomU with all processors at HIGH_LEVEL (interrupts > disabled). > > Does that sound acceptable?I''d run with AMD''s static patch tables and see how far that gets you. There''s no reason to think Microsoft are going to release any further kernels without the lazy TPR optimisation. Otherwise something like you suggest should work. -- Keir _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel
> On 01/01/2009 00:57, "James Harper" <james.harper@bendigoit.com.au>wrote:> > > Obviously a number of iterations will be required before all the > > patching is done, but I don''t think that''s a problem. Patching would > > occur in the DomU with all processors at HIGH_LEVEL (interrupts > > disabled). > > > > Does that sound acceptable? > > I''d run with AMD''s static patch tables and see how far that gets you.I''ve exchanged a few emails with Travis and he seems to think they may be incomplete, although I guess adding the missing entries wouldn''t be a big deal - just add some periodic logging to the hypervisor and catch the writes.> There''s no reason to think Microsoft are going to release any further > kernels without the lazy TPR optimisation.Hadn''t thought of it that way... Travis has indicated that his license is compatible with GPLv2, so yes, I''ll stick with that. Thanks James _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel