Mark Langsdorf
2007-Nov-02 21:30 UTC
[Xen-devel] [cpufreq][PATCH][1/2] Xen support for architectural pstate driver
With the third generation Opteron parts, AMD switched to an
architecturally defined interface for PowerNow! that uses
different MSRs than previous versions.
Add support in msr-index.h and traps.c for the new interface.
Signed-off-by: Mark Langsdorf <mark.langsdorf@amd.com>
iff -r 650cadd1b283 xen/arch/x86/traps.c
--- a/xen/arch/x86/traps.c Fri Nov 02 16:38:11 2007 +0000
+++ b/xen/arch/x86/traps.c Fri Nov 02 16:40:14 2007 -0500
@@ -1845,6 +1845,17 @@ static int emulate_privileged_op(struct
#endif
case MSR_K7_FID_VID_STATUS:
case MSR_K7_FID_VID_CTL:
+ case MSR_K8_PSTATE_LIMIT:
+ case MSR_K8_PSTATE_CTRL:
+ case MSR_K8_PSTATE_STATUS:
+ case MSR_K8_PSTATE0:
+ case MSR_K8_PSTATE1:
+ case MSR_K8_PSTATE2:
+ case MSR_K8_PSTATE3:
+ case MSR_K8_PSTATE4:
+ case MSR_K8_PSTATE5:
+ case MSR_K8_PSTATE6:
+ case MSR_K8_PSTATE7:
if ( (cpufreq_controller != FREQCTL_dom0_kernel) ||
(boot_cpu_data.x86_vendor != X86_VENDOR_AMD) ||
wrmsr_safe(regs->ecx, eax, edx) )
@@ -1897,6 +1908,17 @@ static int emulate_privileged_op(struct
#endif
case MSR_K7_FID_VID_CTL:
case MSR_K7_FID_VID_STATUS:
+ case MSR_K8_PSTATE_LIMIT:
+ case MSR_K8_PSTATE_CTRL:
+ case MSR_K8_PSTATE_STATUS:
+ case MSR_K8_PSTATE0:
+ case MSR_K8_PSTATE1:
+ case MSR_K8_PSTATE2:
+ case MSR_K8_PSTATE3:
+ case MSR_K8_PSTATE4:
+ case MSR_K8_PSTATE5:
+ case MSR_K8_PSTATE6:
+ case MSR_K8_PSTATE7:
if ( (cpufreq_controller != FREQCTL_dom0_kernel) ||
(boot_cpu_data.x86_vendor != X86_VENDOR_AMD) ||
rdmsr_safe(regs->ecx, regs->eax, regs->edx) )
diff -r 650cadd1b283 xen/include/asm-x86/msr-index.h
--- a/xen/include/asm-x86/msr-index.h Fri Nov 02 16:38:11 2007 +0000
+++ b/xen/include/asm-x86/msr-index.h Fri Nov 02 16:40:14 2007 -0500
@@ -165,6 +165,17 @@
#define MSR_K8_HWCR 0xc0010015
#define MSR_K7_FID_VID_CTL 0xc0010041
#define MSR_K7_FID_VID_STATUS 0xc0010042
+#define MSR_K8_PSTATE_LIMIT 0xc0010061
+#define MSR_K8_PSTATE_CTRL 0xc0010062
+#define MSR_K8_PSTATE_STATUS 0xc0010063
+#define MSR_K8_PSTATE0 0xc0010064
+#define MSR_K8_PSTATE1 0xc0010065
+#define MSR_K8_PSTATE2 0xc0010066
+#define MSR_K8_PSTATE3 0xc0010067
+#define MSR_K8_PSTATE4 0xc0010068
+#define MSR_K8_PSTATE5 0xc0010069
+#define MSR_K8_PSTATE6 0xc001006A
+#define MSR_K8_PSTATE7 0xc001006B
#define MSR_K8_ENABLE_C1E 0xc0010055
#define MSR_K8_VM_CR 0xc0010114
#define MSR_K8_VM_HSAVE_PA 0xc0010117
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