Displaying 20 results from an estimated 1000 matches similar to: "help about R"
2014 Dec 08
1
Centralized Monitoring of Question
Hello Sir/Madam,
I have a question related to UPS monitoring by SNMP cards via NUT(Network UPS Tools).
We have a few SNMP Cards (MEGATEK) that connecting to a number of UPS`s. We need a centralized program to monitoring of our UPS`s.
We want to know that, NUT can help us?
Operating System: Windows or Linux
SNMP Card type: Netagent model for MEGATEK company (www.megatec.com.tw).
Yours
2014 Dec 13
2
[LLVMdev] Vectorization factor limitation in Loop Vectorizer
So IMO, if we modify the VF calculation for targets/subtargets using TTI where higher VF is supported
The vectorizer’s scope will become wider.
Did/do you foresee any issue with this?
Thanks,
Shahid
From: Nadav Rotem [mailto:nrotem at apple.com]
Sent: Saturday, December 13, 2014 2:47 AM
To: Shahid, Asghar-ahmad
Cc: llvmdev at cs.uiuc.edu
Subject: Re: [LLVMdev] Vectorization factor limitation in
2015 May 04
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
Hi Asghar-Ahmed,
I saw your last ping - sorry, I'm away on vacation and back on Wednesday.
Generally, I'm not sure that having both absd/hadd and sad are compatible
with the discussions going on in other threads, for example my thread about
min and max.
Given that those two intrinsics are fairly trivial to match , I don't see
the need to have two different canonical forms.
James
On
2014 Mar 29
1
uefi
How can I install
a dual boot centos
in my laptop
while my windows has
UEFI partition?
--
With The Best
H.Lanjanian
-----------------------------------------------------------------------
Hossein Lanjanian,
Ph.D. student
Laboratory of Systems Biology and Bioinformatics
(LBB)
Institute of Biochemistry and Biophysics (IBB), University of
Tehran
Tehran, Iran
http://LBB.ut.ac.ir
2000 Jan 19
2
Samba and /etc/shadow.
Dear mailing-list!
I have Samba 2.0.6 on a Redhat 6.1 linux box.
How can I make samba use the /etc/shadow file
for authenticating users?
Reading the archives I assumed there should be
a compile-time option I should set, but I found
no such option.
Regards
--
Shahin Merat, Dept. of gastroenterology,
Shariati Hospital, N Kargar st., Tehran, Iran
merat@ams.ac.ir / merats@sums.ac.ir
2015 May 06
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
> For the time being, if you can get away with heuristics, and that fills your
> allocated time for this task, that it's the best way forward for now.
Sorry that I could not get what exactly you mean with "heuristics".
Is it the "intrinsics approach" itself or something else?
BTW, now my plan is to just add the two intrinsics for 'absolute difference'
and
2015 May 06
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
Hi Renato,
That’s right. I agree with your *pattern vs complexity* thinking.
So I would drop llvm.sad() and go ahead with the remaining two.
Does it make sense in general?
Regards,
Shahid
> -----Original Message-----
> From: Renato Golin [mailto:renato.golin at linaro.org]
> Sent: Tuesday, May 05, 2015 8:40 PM
> To: Shahid, Asghar-ahmad
> Cc: James Molloy; llvmdev at
2015 May 05
2
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
On 4 May 2015 at 08:37, Shahid, Asghar-ahmad
<Asghar-ahmad.Shahid at amd.com> wrote:
> My worry is regarding the query for cost calculation for specific SAD
> instructions such as ‘psad’ (X86) or ‘usad’ (ARM) in Loop Vectorizer.
Hi Shahid,
The vectorizer's cost model has the ability to return different costs
for the same instruction based on the arguments (scalar/vector,
2015 May 05
1
[LLVMdev] [RFC][PATCH] Adding absd/hadd/sad intrinsics
Hi Renato,
Thanks for your response. My concern was actually this. For example, take vector type V8i16 on X86 target
With llvm.sad() intrinsic:
VC1 (Vector Cost) = Cost associated with "PSAD" instruction.
W/ llvm.absd() and llvm.hadd()
VC2 = Cost associated with "absolute diff" + "horizontal add" ( ??? )
As I will be querying with getIntrinsicCost(ID) for these
2019 Mar 06
2
[Bug 109876] New: JIYE BHUTTO
https://bugs.freedesktop.org/show_bug.cgi?id=109876
Bug ID: 109876
Summary: JIYE BHUTTO
Product: xorg
Version: unspecified
Hardware: x86 (IA32)
OS: Windows (All)
Status: NEW
Severity: critical
Priority: medium
Component: Driver/nouveau
Assignee: nouveau at
2015 May 04
2
[LLVMdev] Load value and broadcast in LLVM
Hi Shahid,
Thank you so much for your response. You suggested approach is what I am
right now using. However, it seems that the overhead is a little bit high
because we are introducing two more instructions. I was wondering if there
was a cheaper way to do it.
Best,
Zhi
On Mon, May 4, 2015 at 2:12 AM, Shahid, Asghar-ahmad <
Asghar-ahmad.Shahid at amd.com> wrote:
> Hi Zhi,
>
>
2002 Jun 20
1
Psychometric curves, two altnerative force choice, glm, and budbworms
Dear R-Listers,
to measure the psychometric curve of pitch discrimination, one sequentially
presents two tones of slightly different pitch to an observer (animal will
do), and asks "which is higher". The pschometric curve is the fraction of
correct responses plotted against the pitch difference. It passes through
50% (pure guessing) at zero and normally approaches 100% at large
2016 May 16
0
sum elements in the vector
I'm starting to think we should directly implement horizontal operations on
vector types.
My suspicion is that coming up with a nice model for this would help us a
lot with things like:
- Idiom recognition of reduction patterns that use horizontal arithmetic
- Ability to use horizontal operations in SLPVectorizer
- Significantly easier cost modeling of vectorizing loops with reductions
in
2015 Apr 18
2
[LLVMdev] how can I create an SSE instrinsics sqrt?
Thanks, Shahid. It is fixed now.
On Fri, Apr 17, 2015 at 8:50 PM, Shahid, Asghar-ahmad <
Asghar-ahmad.Shahid at amd.com> wrote:
> Hi zhi,
>
>
>
> You have to also pass the value type to getDecalaration() API such as
>
>
>
> Value* sqrtv = Intrinsic::getDeclaration(M, Intrinsic::x86_sse2_sqrt_pd,
> v->getType());
>
>
>
> Regards,
>
>
2016 May 12
3
sum elements in the vector
> why in order to add this particular instruction (sum elements in a vector) I need to add an insrinsic?
Adding intrinsic is not the only way, it is one of the way and user WILL-NOT be required to invoke
It specifically.
Currently LLVM does not have any instruction to directly represent “sum of elements in a vector” and
generate your particular instruction.However, you can do it without
2016 May 16
4
sum elements in the vector
This would be really cool. We have several instructions that perform horizontal vector operations, and have to use built-ins to select them as there is no easy way of expressing them in a TD file. Some like SUM for a ‘v4i32’ are easy enough to express with a pattern fragment, SUM ‘v8i16’ takes TableGen a long time to compute, but SUM ‘v16i8’ resulted in TableGen disappearing into itself for
2007 Sep 19
2
recommended package/docs for analyzing multiple choice tests
Hi,
What package would you recommend for analyzing the
validity/reliability of multiple choice tests. Doing things such as
classical test analysis, factor analysis, item response theory.
I've used psychometric (item.exam), MiscPsycho (alpha.Summary), and ltm
(rcor.test). MiscPsycho reported the numbers most similar to what I get
in SPSS: corrected point biserial correlations,
2016 May 27
0
sum elements in the vector
Hi Shahid.
Do you mind providing a concrete example of X86 code where an intrinsic was
added (preferrable with filenames and line numbers)? I'm having difficulty
tracking down the steps you provided.
Any help is appreciated.
On Mon, Apr 4, 2016 at 9:02 PM, Shahid, Asghar-ahmad <
Asghar-ahmad.Shahid at amd.com> wrote:
> Hi Rail,
>
>
>
> We had done this for generation
2016 May 18
3
sum elements in the vector
Hi Rail,
We used a very simple pattern expansion (actually, not a pattern fragment). For example, for AND, ADD (horizontal sum), OR and XOR of 4 elements we use something like the following TableGen structure:
class HORIZ_Op4<SDNode opc, RegisterClass regVT, ValueType rt, ValueType vt, string asmstr> :
SHAVE_Instr<(outs regVT:$dst), (ins VRF128:$src),
2015 Nov 19
5
[RFC] Introducing a vector reduction add instruction.
After some attempt to implement reduce-add in LLVM, I found out a
easier way to detect reduce-add without introducing new IR operations.
The basic idea is annotating phi node instead of add (so that it is
easier to handle other reduction operations). In PHINode class, we can
add a flag indicating if the phi node is a reduction one (the flag can
be set in loop vectorizer for vectorized phi nodes).