similar to: [PATCH][RFC] FPU LWP 5/5: enable LWP CPUID for HVM guests

Attached SVM patch fixes a virtualization of the CPUID NX bit, and cleans up other CPUID bits. Applies cleanly to xen-unstable.hg 10177. Applies to xen-3.0-testing 9696. Please apply to xen-unstable.hg. Please apply to xen-3.0-testing.hg. Tested on top of the KY patches for XCHG (HVM) and SMP SVM support. Keir, Can those 2 patches KY posted last week, also be applied to 3.0.2?

I am adding interrupt support for LWP, whose spec is available at http://support.amd.com/us/Processor_TechDocs/43724.pdf. Basically OS can specify an interrupt vector in LWP_CFG MSR; the interrupt will be triggered when event buffer overflows. For HVM guests, I want to re-inject this interrupt back into the guest VM. Here is one idea similar to virtualized PMU: It first registers a special

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# HG changeset patch # User Olaf Hering <olaf@aepfle.de> # Date 1338572607 -7200 # Node ID 3da83ff08d6b6431c104a431d6617ccb5977643b # Parent fde8ad0252ee6ddb8d71dda869db3b20b3d9ca62 xl.cfg: document the cpuid= option Signed-off-by: Olaf Hering <olaf@aepfle.de> diff -r fde8ad0252ee -r 3da83ff08d6b docs/man/xl.cfg.pod.5 --- a/docs/man/xl.cfg.pod.5 +++ b/docs/man/xl.cfg.pod.5 @@ -969,9

This patch initializes VMCB CR4 and shadow CR4 with 0 when VMCB is being constructed under nested paging mode. It complies with recent reset_to_realmode change in hvmloader. Signed-off-by: Wei Huang (wei.huang2@amd.com <mailto:wei.huang2@amd.com> ) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

flight 5665 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/5665/ Regressions :-( Tests which did not succeed and are blocking: build-amd64-oldkern 4 xen-build fail REGR. vs. 5640 build-amd64 4 xen-build fail REGR. vs. 5640 build-i386-oldkern 4 xen-build fail REGR. vs. 5640

These two patches affect the interrupt injection logic for AMD-V (only). These patches fix issues with Windows HVM guests during boot menu screen: 1) the timer countdown is no longer very slow 2) kbd response is now no longer slow or non-existent We have also seen an occasional "dma lost interrupt"/expiry errors, and these patches seem to help with these, especially with SUSE10 HVM

Hi Jan, I was wondering if we should not let the code fall through and clear all registers to zero but rather clear just the one bit we care about? My concern is that a future Intel revision may expand this function and return other information besides that XSAVEOPT, which would then be wiped out by the fall-through code. I''m thinking something like this. Let me know if I have

Patch 2/2 - Add flag to indicate that an exception event needs injecting, and to delay the ext interrupt injection. Remove unnecessary check of RFLAGS.IF for ExtInt injection. Applies cleanly to xen-unstable c/s 11831. Please apply to xen-unstable.hg. We would also want this patch to be in a 3.0.3-1 base whenever that is branched. Signed-off-by: Travis Betak <travis.betak@amd.com>

This patch supports xsave (CPUID:0x0000000D) enumeration for all sub-leaves. In specific, it fixes the following issues: 1. The sub-leaves of CPUID:0x0000000D aren''t contiguous. Hypervisor shouldn''t use register values to stop the enumeration. This patch moves checking on XSAVE sub-leaves out of if-else statement. It also bumps up sub-leaves to 63. 2. It creates a common

Hi Keir, For HVM guests, all cpuid Fn''s going through domain_cpuid() iterate over the loop and then return 0 for all four registers. Guests OS''s and cpuid tools in HVM which query for cpuid Fn 0000.0000 %eax and 8000.0000 %eax, see the value 0 and think, Xen emulates oldish 386/486 CPUs. This leads to strange boot failures, "your CPU does not support long mode" or

- use __clear_bit() rather than clear_bit() - use switch statements instead of long series of if-s - eliminate pointless casts (Applies cleanly only on top of the previously sent SVM/EFER patch.) Signed-off-by: Jan Beulich <jbeulich@novell.com> Index: 2007-08-08/xen/arch/x86/hvm/hvm.c =================================================================== ---

This patch changes hap parameter from boolean to integer. So users can disable and enable hap using "hap=0" and "hap=1". It also prints out nested paging message under SVM. Signed-off-by: Wei Huang <wei.huang2@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Remove visibility of the FFXSR CPUID bit to an HVM guest. This patch allows HVM Windows x64 to install/boot on AMD-V platforms. This patches applies cleanly to xen-unstable 13743. Please apply to xen-unstable/3.0.5. If possible, pls apply to xen-3.0.4-testing. --Tom thomas.woller@amd.com AMD Corporation 5204 E. Ben White Blvd. UBC1 Austin, Texas 78741 +1-512-602-0059

I am running 2.6.18-1.2693.fc6xen and I am receiving this message powernow-k8: Processor cpuid 681 not supported anyone know if xen works on processor : 0 vendor_id : AuthenticAMD cpu family : 6 model : 8 model name : AMD Athlon(tm) Prosussor stepping : 1 cpu MHz : 1994.985 cache size : 256 KB fdiv_bug : no hlt_bug : no

I am running 2.6.18-1.2693.fc6xen and I am receiving this message powernow-k8: Processor cpuid 681 not supported anyone know if xen works on processor : 0 vendor_id : AuthenticAMD cpu family : 6 model : 8 model name : AMD Athlon(tm) Prosussor stepping : 1 cpu MHz : 1994.985 cache size : 256 KB fdiv_bug : no hlt_bug : no

Enable Px/Cx related CPUID/MSR bits for dom0 to get correct Px/Cx info. Signed-off-by: Wei Gang <gang.wei@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Hi, this patch passes the orginal cpuid bits for X86_FEATURE_DTES64 (64-bit DS Area) and X86_FEATURE_DSCPL (CPL Qualified Debug Store) to the guest when the BTS feature is switched on. I forgot this when I did this BTS emulation. Thanks. Dietmar. Signed-off-by: Dietmar Hahn <dietmar.hahn@ts.fujitsu.com> diff -r a6b81234b189 xen/arch/x86/hvm/vmx/vpmu_core2.c ---

This is a bug fixing. So it needs go into 4.1. x86: add volatile prefix for cpuid asm clauses cpuid results are possible to be changed now. For example, changing CR4.OSXSAVE bit or setting MSR XCR_XFEATURE_ENABLED_MASK may change XSAVE related cpuid leave return values. The volatile prefix is required to avoid the second cpuid calls following some possible changing operations being optimized in

The attached patch fixes the save/restore issue seen with 32bit Windows guest VMs. The root cause is that current Xen doesn''t intercept SYSENTER-related MSRs for 32bit guest VMs. As a result, the guest_sysenter_xxx fields contain incorrect values and shouldn''t be used for save/restore. This patch checks the LMA bit of EFER register in the save/restore code path. Please apply it