similar to: [RFC PATCH 0/2] ASID: Flush by ASID

This patch implements flush by asid feature for AMD CPUs. Thanks, Wei Signed-off-by: Wei Huang <wei.huang2@amd.com> Signed-off-by: Wei Wang <wei.wang2@amd.com> -- Advanced Micro Devices GmbH Sitz: Dornach, Gemeinde Aschheim, Landkreis München Registergericht München, HRB Nr. 43632 WEEE-Reg-Nr: DE 12919551 Geschäftsführer: Alberto Bozzo, Andrew Bowd

Keir, pci-detach triggers IO page table deallocation if the last passthru device has been removed from pdev list, and this will result a BUG on amd systems for next pci-attach. This patch fixes this issue. Thanks, Wei Signed-off-by: Wei Wang <wei.wang2@amd.com> -- Advanced Micro Devices GmbH Sitz: Dornach, Gemeinde Aschheim, Landkreis München Registergericht München, HRB Nr. 43632

Hi Ian, There have been a lot of interest on gfx passthru recently. This patch enables ATI VBIOS in passthru mode. The guest VM system BIOS (including Windows boot logo) can now show in passthru screen. We have tested with various Windows and Linux guest VMs. Please help review it. We are also looking forward to comments and suggestions from Xen community users. Signed-off-by: Wei Huang

Hi, (Assume VPID is available and enabled.) I''m trying to figure the TLB stuff with VPIDs. I understand from the poorly written chapter in the intel manual that if an HVM vcpu is running then only the TLBs tagged with the vcpu.VPID will be used. If xen or a PV guest is running, then VPID 0 TLBs are what will be used. Now I understand the hvm_asid_flush_vcpu upon new guest cr3, will

Attached patch for svm will enable a tlb flush for each vmrun. Applies cleanly to 8781:dcc2beb8a1d2 Signed-off-by: Tom Woller <thomas.woller@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Signed-off-by: Wei Wang <wei.wang2@amd.com> -- Advanced Micro Devices GmbH Sitz: Dornach, Gemeinde Aschheim, Landkreis München Registergericht München, HRB Nr. 43632 WEEE-Reg-Nr: DE 12919551 Geschäftsführer: Alberto Bozzo, Andrew Bowd _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Changeset 20514 implemented deallocation for msi interrupt remapping entries. Attached patch adds the same support for amd iommu to fix a xen crash on amd iommu systems. Thanks, Wei Signed-off-by: Wei Wang <wei.wang2@amd.com> -- Legal Information: Advanced Micro Devices GmbH Karl-Hammerschmidt-Str. 34 85609 Dornach b. München Geschäftsführer: Andrew Bowd, Thomas M. McCoy, Giuliano Meroni

Hi, Attached patch implements the VMCB cleanbits SVM feature. Upcoming AMD CPUs introduce them and they are basically hints for the CPU which vmcb values can be re-used from the previous VMRUN instruction. Each bit represents a certain set of fields in the VMCB. Setting a bit tells the cpu it can re-use the cached value from the previous VMRUN. Clearing a bit tells the cpu to reload the values

Hi, I''m running a machine with: - Hypervisor: xen-unstable - Dom0: xen/next-2.6.32.17 commit c3f5aba942c7516a5c76c47345ff0a473daf2542 Hardware: -MSI 890FXA-GD70 with AMD IOMMU -Phenom X6 I''m trying to do PCI passthrough to a HVM, this fails with: Error: Failed to assign device to IOMMU (0000:04:00.0@100,msitranslate=1,power_mgmt=0) Error: pci: to avoid potential security

This patch initializes VMCB CR4 and shadow CR4 with 0 when VMCB is being constructed under nested paging mode. It complies with recent reset_to_realmode change in hvmloader. Signed-off-by: Wei Huang (wei.huang2@amd.com <mailto:wei.huang2@amd.com> ) _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Attached are the patches to support super page with EPT. We only support 2M size. And shadow may still work fine with 4K pages. The patches can be split into 3 parts. Apply order is as attached. tool.diff To allocate 2M physical contiguous memory in guest except the first 2M and the last 2M. The first 2M covers special memory, and Xen use the last few pages in guest memory to do special

I am adding interrupt support for LWP, whose spec is available at http://support.amd.com/us/Processor_TechDocs/43724.pdf. Basically OS can specify an interrupt vector in LWP_CFG MSR; the interrupt will be triggered when event buffer overflows. For HVM guests, I want to re-inject this interrupt back into the guest VM. Here is one idea similar to virtualized PMU: It first registers a special

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This patch series is based on Eugenio's fix for handling CVQs in a different ASID [0]. The first patch is the actual fix. The next 2 patches are fixing a possible issue that I found while implementing patch 1. The patches are ordered like this for clarity. [0] https://lore.kernel.org/lkml/20230112142218.725622-1-eperezma at redhat.com/ Dragos Tatulea (1): vdpa/mlx5: Fix

This patch series is based on Eugenio's fix for handling CVQs in a different ASID [0]. The first patch is the actual fix. The next 2 patches are fixing a possible issue that I found while implementing patch 1. The patches are ordered like this for clarity. [0] https://lore.kernel.org/lkml/20230112142218.725622-1-eperezma at redhat.com/ Dragos Tatulea (1): vdpa/mlx5: Fix

This patch changes hap parameter from boolean to integer. So users can disable and enable hap using "hap=0" and "hap=1". It also prints out nested paging message under SVM. Signed-off-by: Wei Huang <wei.huang2@amd.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

The attached patch fixes the save/restore issue seen with 32bit Windows guest VMs. The root cause is that current Xen doesn''t intercept SYSENTER-related MSRs for 32bit guest VMs. As a result, the guest_sysenter_xxx fields contain incorrect values and shouldn''t be used for save/restore. This patch checks the LMA bit of EFER register in the save/restore code path. Please apply it

Patch 2/2 - Add flag to indicate that an exception event needs injecting, and to delay the ext interrupt injection. Remove unnecessary check of RFLAGS.IF for ExtInt injection. Applies cleanly to xen-unstable c/s 11831. Please apply to xen-unstable.hg. We would also want this patch to be in a 3.0.3-1 base whenever that is branched. Signed-off-by: Travis Betak <travis.betak@amd.com>

Introduce a new flag to disable iommu emulation on old iommu systems. This patch is taken from my v4 patch queue, which is till pending, to make old or non-iommu system to run cleanly without interfered by iommuv2 codes. This might be helpful to isolate iommuv2 code in debugging unstable regressions. The reset part of v4 will be re-based. Thanks, Wei Signed-off-by: Wei Wang

Hi all, Please can anybody explain how communication(direct or indirect) happens between xen and guest os(windows) in full virtualization mode. Both from VMM to guest and from guest to VMM. Thanks and regards, Aditya. __________________________________________________________ Yahoo! India Answers: Share what you know. Learn something new http://in.answers.yahoo.com/