similar to: [PATCH][VT] Fix the mmio for cmp/test opcode

In sh_page_fault(), there are some code like following, why we think it is mmio only when paging_vcpu_mode_translate(v)? Thanks Yunhong Jiang /* What mfn is the guest trying to access? */ gfn = guest_l1e_get_gfn(gw.eff_l1e); gmfn = vcpu_gfn_to_mfn(v, gfn); mmio = (is_hvm_domain(d) && paging_vcpu_mode_translate(v) &&

To avoid MSR save/restore at every VM exit/entry time, we restore the x86_64 specific MSRs at domain switch time if modified. In VMX domains, we modify those upon requests from the guests to that end. Note that IA32_EFER.LME and IA32_EFER.LMA are saved/restored by H/W on every VM exit. For the usual domains (i.e. dom0 and domU), those MSRs are not modified once set at initialization time, so we

Keir Fraser wrote: > On 13 Sep 2005, at 03:40, Jiang, Yunhong wrote: > >> 1) I think the cpu_reset_interrupt() is a common API on qemu for >> hardware interrupt/exception etc,while clear the shared page is just >> for hardware interrupt. Of course, this function is currently used >> just for hardware interrupt since qemu works as a device model :) >> But

The patch enables x86_32 PAE unmodified guests on 64-bit Xen when the hvm feature is present. We tested only Linux at this point, and we''ll improve the functionality as we test other guests. The SVM needs the equivalent changes to the vmc.c to get this functionality working, but this patch does not break the build. Signed-off-by: Jun Nakajima <jun.nakajima@intel.com>

Extend the VMX intercept mechanism to include mmio as well as portio. Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com> Signed-off-by: Xiaofeng Ling <xiaofeng.ling@intel.com> Signed-off-by: Arun Sharma <arun.sharma@intel.com> diff -r febfcd0a1a0a -r 9a43d5c12b95 xen/include/asm-x86/vmx_platform.h --- a/xen/include/asm-x86/vmx_platform.h Thu Jun 30 03:20:48 2005 +++

So, Keir, can you please check in this patch? Thanks Yunhong Jiang >-----Original Message----- >From: xen-devel-bounces@lists.xensource.com >[mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of >John Clemens >Sent: Tuesday, February 28, 2006 1:35 AM >To: Jiang, Yunhong >Cc: Li, Xin B; xen-devel@lists.xensource.com >Subject: [Xen-devel] Re: [PATCH] Fix qemu-dm

Hi, Keir: the gdtr information in oldctx is an address for guest, not for vmxassist. When access descriptor on guest gdt, we need to go through guest page table if guest enable paging. This error may happen if guest enable PE/PG in one instruction. This patch fix this issue. Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com> Signed-off-by: Xin Li <xin.b.li@intel.com> Thanks

Currently the vector is not freed for MSI interrupt, the three patches fix the issue. The first patch(pirq.patch) move the get_free_pirq/map(unmap)_domain_pirq from arch/x86/physdev.c to arch/x86/irq.c, since that should be part of irq managment, no logic changes. The second patch(msi_vector_clean.patch) free the vector when the pirq is unmapped or when domain destroy. One thing need notice for

Propagate guest MSR writes to machine MSRs immediately Right now, we have an exposure between the time the MSR is written and used by an instruction such as syscall. If there is a context switch and we do vmx_do_restore_msrs(), everything goes fine. But if we don''t, then we execute the syscall with the wrong MSR. Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com>

Any advice about the patch cr8-acceleration-3.patch? Hi Keir, could you give some comments? Thanks! -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:12 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8

Intercepting this MSR is pointless - The swapgs instruction does not cause a vmexit, so the cached result of this is potentially stale after the next guest instruction. It is correctly saved and restored on vcpu context switch. Furthermore, 64bit Windows writes to this MSR on every thread context switch, so interception causes a substantial performance hit. From: Paul Durrant

Hi, Keir, These patches are rebased version of Yunhong''s original patches, which were sent out before XEN 3.2 was released. These patches enable MSI support and limited MSI-X support in XEN. Here is the original description of the patches from Yunhong''s mail. The basic idea including: 1) Keep vector global resource owned by xen, while split pirq into per-domain

This patch changes the pirq to be per-domain in xen tree. Signed-off-by: Jiang Yunhong <yunhong.jiang@intel.com> Signed-off-by: Shan Haitao <haitao.shan@intel.com> Best Regards Shan Haitao _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Patch 5 modify_pci: it provides small fix of aerdrv_core, add one new func of get_device by BDF Signed-off-by: Jiang Yunhong<yunhong.jiang@intel.com> Signed-off-by: Ke Liping<liping.ke@intel.com> Thanks& Regards, Criping _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

This patch add MSI support to passthrough HVM domain. Currently it only inercept access to MSI config space, no MSI-x support. Signed-off-by: Jiang Yunhong <yunhong.jiang@intel.com> Signed-off-by: Shan Haitao <haitao.shan@intel. <<msi_passthrough.patch>> com> Best Regards Haitao Shan _______________________________________________ Xen-devel mailing list

build p2m mapping according to m2p mapping. Signed-off-by: Xin Li <xin.b.li@intel.com> Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Sorry, please ignore this mail. (I attached the old patch...) -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:07 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8 acceleration for TPRaccessing x64

Fix regs set/get decoding in VMXAssist. Signed-off-by: Yunhong Jiang <yunhong.jiang@intel.com> Signed-off-by: Xin Li <xin.b.li@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Patch 6 pciback_err_handler.patch: Implementation for enabling PCIE_AER support in XEN This patch is the main implementation for enabling PCIE_AER handling, adding related pci error handler in pciback and pcifront. When a device sends a PCIE error message to the root port, it will triger an interrupt. The irq handler will then collect roor error status register, then schedule a work to process

Ian, Keir, This patch is to boot 32-bit VMX guest on the 64-bit host. Double-compile is used to make both 64-bit guest and 32-bit guest can work, the shadow page-table uses current 64-bit shadow code''s structure to simulate 32-bit guest''s 2-level page-table. Signed-off-by: Chengyuan Li <chengyuan.li@intel.com> Signed-off-by: Xiaohui Xin <xiaohui.xin@intel.com>