similar to: [PATCH] Limit MCG Cap

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP), INTn instruction emulation. Introduce new function vmx_inject_sw_exception() which deliver the software excetion, software interrupt and privileged software exception. Split hardware exception as a seperate function(old function vmx_inject_hw_exception()). Also Passed down intruction length

Currently number of error reporting register banks is hardcoded to 6 on AMD processors. This may break in virtualized scenarios when a hypervisor prefers to report fewer banks that the physical HW provides. Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0] that''s what we should use. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> ---

Hello, While working on a fix for the rare-but-possible problem of reentrant NMIs and MCEs, I have discovered that it is sadly possible to generate fake NMIs and MCEs which will run the relevant handlers on the relevant stacks, without invoking any of the other CPU logic for these special interrupts. A fake NMI can be generated by a processor in PIC mode as opposed to Virtual wire mode, with a

Hi, This is updated xen vMCE design foils, according to comments from community recently. This foils focus on vMCE part of Xen MCA, so as Keir said, it''s some dense. Later Will will present a document to elaborate more, including Intel MCA and surrounding features and Xen implementation. Thanks, Jinsong

This was set to zero immediately before the #GP injection code, since SYSENTER doesn''t really have a return address. Reported-by: Ian Campbell <Ian.Campbell@citrix.com> Furthermore, UREGS_cs and UREGS_rip don''t need to be written a second time, as the PUSHes above already can/do take care of putting in place the intended values. Signed-off-by: Jan Beulich

"Jan Beulich" <JBeulich at suse.com> writes: #Okay, this at least clarifies there is a (relatively big) RMRR. There is #a change to the handling of these among the ones that'll become #4.3.3 - mind giving #http://xenbits.xen.org/gitweb/?p=xen.git;a=commitdiff;h=6c63041428cc348bcb2887afabd606bc4bd5523f #a try on top of your 4.3.2 (or trying the tip of the stable-4.3 branch)? #

>>> On 20.05.14 at 18:25, <mike at estone.ca> wrote: > I've added iommu=debug to the XEN CMD Line under grub. > Attached is the xl dmesg log and system dmesg. Okay, this at least clarifies there is a (relatively big) RMRR. There is a change to the handling of these among the ones that'll become 4.3.3 - mind giving

Hi! The MCG_CAP MSR never returns a negative count of available error-reporting banks. Thus make nr_mce_banks unsigned. While here, do some other minor cleanups. Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> -- AMD Saxony, Dresden, Germany Operating System Research Center Legal Information: AMD Saxony Limited Liability Company & Co. KG Sitz (Geschäftsanschrift):

Ian Campbell <ijc at hellion.org.uk> writes: #What were the previous settings (the ones which worked for grub but not #Xen)? Do these new settings work with native Linux? # #Given the change in behaviour my gut feeling is that either the Legacy #USB Support option or the 60/64 emulation ones are the one which matters #out of that set. The default and previous settings were everything

The existing xc_domain_dumpcore is very specific to disk/file based output. Refactor the code slightly to allow more user-specified control. This is done by adding a parallel xc_domain_dumpcore2 (naming isn''t always my strong suit), which allows the specification of a callback routine and an opaque argument block. The existing dumpcore routine is modified to use the callback for all

Migrate the last TSC values for more accurate timekeeping during live migration Signed-off-by: Dave Winchell <dwinchell@virtualiron.com> Signed-off-by: Ben Guthro <bguthro@virtualiron.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

hallo everybody, i googled a lot of time, looking for PV-drivers for Windows- domUs. I found a few things about that, but nothing about download an installation. Do anybody know, where I can get it and how to install? My configuration: Dom0: CentOS 5.1 DomUs: Windows XP and 2003 Server Thanks for any help, Guenter _______________________________________________ Xen-users mailing list

Currently number of error reporting register banks is hardcoded to 6 on AMD processors. This may break in virtualized scenarios when a hypervisor prefers to report fewer banks than what the physical HW provides. Since number of supported banks is reported in MSR_IA32_MCG_CAP[7:0] that''s what we should use. Signed-off-by: Boris Ostrovsky <boris.ostrovsky@oracle.com> ---

I have recently upgraded to 2.6.18-194.3.1.el5 and within several days the machine crashed with the following error (repeating in mcelog): MCE 0 HARDWARE ERROR. This is *NOT* a software problem! Please contact your hardware vendor CPU 2 BANK 8 MISC 41 MCG status: MCi status: Error overflow Uncorrected error MCi_MISC register valid Processor context corrupt MCA: MEMORY CONTROLLER AC_CHANNEL0_ERR

Ben- I like the idea but I don''t understand how this patch can work: 1) You never put a name into `serial_devices[]'' for the summa port. The loop in `main'' that initializes the serial devices only calls `qemu_chr_open'' if there''s a string name in `serial_devices''. How did you get this to work? 2) Minor point, I don''t see the need

Hi, John Can you try the attached patch ? This issue can be reproduced on SMP platform, while the domain 0 is UP. The reason is, after finishing a dma request, the dma thread will trigger the interrupt and then clear the call back function. When guest get the interrupt , it will try to check the call back function, if it is set, then it will trigger a dma request again. So if the checking for

Jan, This patch just used to stick all 1''s to MCi_CTL, it should not involve much argue, so I sent it separately. Thanks, Jinsong ==================== Xen/MCE: stick all 1''s to MCi_CTL of vMCE This patch is a middle-work patch, prepare for future new vMCE model. It remove mci_ctl array, and keep MCi_CTL all 1''s. Signed-off-by: Liu, Jinsong

Hi, When dom0 is under heavy load any Vista or Windows 2008 HVM''s that are running and have multiple cpu''s assigned often BSOD with code 0x00000101 "A clock interrupt was not recevied ona secondary processor within the allocated time interval" It only happens if the load in dom0 is high enough to make the mouse pointer lagged, once the mouse fails to track in

Hi, When dom0 is under heavy load any Vista or Windows 2008 HVM''s that are running and have multiple cpu''s assigned often BSOD with code 0x00000101 "A clock interrupt was not recevied ona secondary processor within the allocated time interval" It only happens if the load in dom0 is high enough to make the mouse pointer lagged, once the mouse fails to track in