similar to: [PATCH] Fix write parameter masking for 32-bit guests.

Any advice about the patch cr8-acceleration-3.patch? Hi Keir, could you give some comments? Thanks! -- Dexuan -----Original Message----- From: xen-devel-bounces@lists.xensource.com [mailto:xen-devel-bounces@lists.xensource.com] On Behalf Of Cui, Dexuan Sent: 2006年10月25日 11:12 To: Keir.Fraser@cl.cam.ac.uk Cc: xen-devel@lists.xensource.com Subject: [Xen-devel] [Patch][RESEND] Add hardware CR8

The Xen platform device (introduced in changeset 11161) would cause HCT''s PCI Compliance Test to generate a failure message. The patch fixes this. Thanks Dexuan Cui Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

The PCI_EXP_TYPE_PCI_BRIDGE should be PCI_EXP_FLAGS_TYPE here. Also a tiny fix to the python comment. Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

In x64 SMP Vista HVM guest (vcpus=2 in the configuration file), the wall clock time is 50% slower than that in the real world. The attached patch fixes the issue. -- Dexuan Signed-off-by: Dexuan Cui <dexuan.cui@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

On platforms which supports x2APIC, the patches enable this enhancement for Xen. The x2APIC specification is available at http://www.intel.com/products/processor/manuals/ http://download.intel.com/design/processor/specupdt/318148.pdf apicid_u8_2_u32.patch: changes the ''apicid'' from u8 to u32; x2apic.patch: replaces the traditional MMIO-style interface to the MSR-style one; uses

The datasheet is available at http://download.intel.com/design/network/datashts/82599_datasheet.pdf See 'Table 9.7. VF PCIe Configuration Space' of the datasheet, the PCI Express Capability Structure of the VF of Intel 82599 10GbE Controller looks trivial, e.g., the PCI Express Capabilities Register is 0, so the Capability Version is 0 and pt_pcie_size_init() would fail. We should not

The patch moves the struct IO_APIC_route_entry to a common place. This allows us to share the struct with iosapic. Thanks, -- Dexuan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

HVM balloon driver or something, that''s under development, may decrease or increase the machine memory that is taken by HVM guest; in IA32/IA32e host, now Qemu maps the physical memory of HVM guest based on little blocks of memory (the block size is 64K in IA32 host or 1M in IA32E host). When HVM balloon driver decreases the reserved machine memory of HVM guest, Qemu should unmap the

Some operating systems access the local APIC TPR very frequently, and we handle that using software-based local APIC virtualization in Xen today. Such virtualization incurs a number of VM exits from the memory-access instructions against the APIC page in the guest. The attached patch enables the TPR shadow feature that provides APIC TPR virtualization in hardware. Our tests indicate it can

Currently, Xen does not support injecting an NMI to HVM guest OS. Adding this feature is necessary for those softwares which depend on NMI to function correctly, such as KDB and oprofile. The attached patch allows NMI to be injected to guest OS in NMIP capable platforms. It also enables to queue an NMI and then inject it as soon as possible. Signed-off-by: Haitao Shan

For an SMP Linux HVM guest with PV drivers inserted, when we do save/restore (or LiveMigration) for the guest, it might panic after it''s restored. The panic point is inside ap_suspend(): .... while (info->do_spin) { cpu_relax(); read_lock(&suspend_lock); HYPERVISOR_yield(); ----> guest might panic on the invocation of this function.

Thank you. I notice the system then jumps to F000:FFF0 to execute. But because VMX is turned on, switching to real-mode would incur problems? I don’t find any clue to turn on the vm86 mode as Readme in the tools/firmware directory puts. Best regards, Hu Jia Yi Ext: 20430 Tel: 65-67510430 -----Original Message----- From: Cui, Dexuan [mailto:dexuan.cui@intel.com] Sent: Thursday,

Hi Jan Beulich, > changeset 15414: 3cf5052ba5e5 x86: machine check exception handling With the c/s, when creating HVM guest, I can only see a white Qemu window. :( Can you have a look? Thanks. PS: the serial log follows: (XEN) HVM1: pci dev 02:0 bar 14 size 00001000: f2000000 (XEN) HVM1: pci dev 03:0 bar 10 size 00000100: 0000c101 (XEN) HVM1: pci dev 03:0 bar 14 size 01000000:

Hello, I''m also seeing this exact same problem. I''ve posted on xen-users, but did not get an answer. Venkat seems to be experiencing the same problem as me. I have the latest BIOS for my motherboard DQ35JO. (BIOS ver 933) I''m running a Q6600 as well. It hangs at "Brought up 4 CPUs." I''ve tried all sorts of combinations of Xen versions and kernels to

Hi, all, The attached patches try to improve the current FLR logic. The idea is: removing the FLR logic from hypervisor and adding the improved logic in Control Panel. The current FLR logic in hypervisor has some issues: 1) Dstate transition is not guaranteed to properly clear the device state; 2) the current code for PCIe FLR is actually buggy: PCI_EXP_DEVSTA_TRPND doesn''t mean the

I tried latest xen and linux-xen staging tree, but failed to run HVM domain on x86-64 environment. domU creation is OK. However the weird thing is not HVM domain itself. Instead system crashed on dom0 context. I saw once with some stack dump that xen''s page fault handler is executed on a dom0''s stack which then causes nested page fault due to unable to fetch vcpu pointer.

I think we need this feature at least for debugging purpose, right? Or, do we already have this feature? Thanks, Neo -- I would remember that if researchers were not ambitious probably today we haven''t the technology we are using! _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

> From: Thomas Gleixner [mailto:tglx at linutronix.de] > Sent: Saturday, February 11, 2017 02:02 > ... > That's important if the stuff happens cross CPU. If the update happens on > the same CPU then this is a different story and as there are VMexits > involved they might provide the required ordering already. But I can't tell > as I have no idea how that host side

> From: Thomas Gleixner [mailto:tglx at linutronix.de] > Sent: Saturday, February 11, 2017 02:02 > ... > That's important if the stuff happens cross CPU. If the update happens on > the same CPU then this is a different story and as there are VMexits > involved they might provide the required ordering already. But I can't tell > as I have no idea how that host side

Save/restore is ok against staging tree''s changeset 15020: d2ef85c6bf84, but is NOT ok against changeset 15021: 00618037d37d (Update to qemu 0.90). I use IA32pae HV; both SMP Windows 2K3 and FC5 can''t be saved properly. After "xm save dom_id 1.save" returns, Qemu window disappears, but "xm vcpu-list" still shows the domain has not been killed. If I