similar to: [PATCH 2/2] Add Px statistic interface to Xen

Add Px statistic structure to sysctl.h Add Px statistic structure to sysctl.h, including Px state value, count, residency time, transition matrix, etc. Signed-off-by: Liu Jinsong <jinsong.liu@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

Cpufreq: prevent negative px resident time, add spinlock to avoid race Due to NOW() value may drift between different cpus, we add protection to prevent negative px resident time. Due to both cpufreq logic and xenpm may race accessing cpufreq_statistic_data, we add spinlock to avoid race. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> _______________________________________________

X86: Disable PCID/INVPCID for pv This patch disable PCID/INVPCID for pv. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 0b15aa9541dc tools/libxc/xc_cpufeature.h --- a/tools/libxc/xc_cpufeature.h Thu Nov 17 18:41:59 2011 +0800 +++ b/tools/libxc/xc_cpufeature.h Thu Nov 17 23:09:45 2011 +0800 @@ -78,6 +78,7 @@ #define X86_FEATURE_CX16 13 /* CMPXCHG16B */ #define

Expose tsc adjust to hvm guest Intel latest SDM (17.13.3) release a new MSR CPUID.7.0.EBX[1]=1 indicates TSC_ADJUST MSR 0x3b is supported. This patch expose it to hvm guest. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r a6d12a1bc758 tools/libxc/xc_cpufeature.h --- a/tools/libxc/xc_cpufeature.h Thu Sep 20 00:03:25 2012 +0800 +++ b/tools/libxc/xc_cpufeature.h Thu Sep 20

X86: Prepare PCID/INVPCID for hvm This patch is used to prepare exposing PCID/INVPCID features to hvm guest. The specific exposure result depend on hvm paging mode (hap/shadow), which would be handled at next patch. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> diff -r 1b62d4e08880 tools/libxc/xc_cpuid_x86.c --- a/tools/libxc/xc_cpuid_x86.c Thu Nov 17 23:09:45 2011 +0800 +++

flight 6412 xen-4.1-testing real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/6412/ Regressions :-( Tests which did not succeed and are blocking: test-amd64-xcpkern-i386-xl-credit2 11 guest-localmigrate fail REGR. vs. 6379 Tests which did not succeed, but are not blocking, including regressions (tests previously passed) regarded as allowable: test-amd64-amd64-win 16

Add statistic interface for cx. Implement statistic interface for cx via sysctl & libxc. Provide a easy way to collect processor cx info within dom0. Signed-off-by: Wei Gang <gang.wei@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

flight 8270 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/8270/ Regressions :-( Tests which did not succeed and are blocking: test-amd64-amd64-xl-pcipt-intel 5 xen-boot fail REGR. vs. 8256 test-amd64-i386-rhel6hvm-intel 3 host-install(3) broken test-amd64-amd64-win 3 host-install(3) broken test-amd64-i386-pv

flight 10504 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/10504/ Regressions :-( Tests which did not succeed and are blocking: test-amd64-amd64-xl-sedf 14 guest-localmigrate/x10 fail REGR. vs. 10491 test-amd64-i386-win 7 windows-install fail REGR. vs. 10491 test-amd64-amd64-xl-winxpsp3 7 windows-install fail REGR. vs. 10491

flight 10511 xen-unstable real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/10511/ Regressions :-( Tests which did not succeed and are blocking: test-amd64-amd64-xl-sedf 14 guest-localmigrate/x10 fail in 10504 REGR. vs. 10491 Tests which are failing intermittently (not blocking): test-amd64-amd64-xl-sedf 13 guest-localmigrate.2 fail pass in 10504 test-i386-i386-win

Ian Campbell wrote: > On Mon, 2013-09-09 at 03:29 +0000, Liu, Jinsong wrote: >> From 18344216b432648605726b137b348f28ef64a4ef Mon Sep 17 00:00:00 >> 2001 >> From: Liu Jinsong <jinsong.liu@intel.com> >> Date: Fri, 23 Aug 2013 23:30:23 +0800 >> Subject: [PATCH V3] xl: HVM domain S3 bugfix >> >> Currently Xen hvm s3 has a bug coming from the

From 291adaf4ad6174c5641a7239c1801373e92e9975 Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Thu, 28 Nov 2013 05:26:06 +0800 Subject: [PATCH v4 3/7] X86: MPX IA32_BNDCFGS msr handle When MPX supported, a new guest-state field for IA32_BNDCFGS is added to the VMCS. In addition, two new controls are added: - a VM-exit control called "clear BNDCFGS" - a

it seems getting lost, and thus resend. Thanks, Kevin -----Original Message----- From: Tian, Kevin Sent: 2008年7月24日 8:39 To: ''Jan Beulich'' Cc: Liu, Jinsong; Keir Fraser; xen-devel@lists.xensource.com; mark.langsdorf@amd.com Subject: RE: [Xen-devel] cpufreq info propagation >From: Jan Beulich >Sent: 2008年7月23日 18:13 >> >>startup info is viable. But how

From 18344216b432648605726b137b348f28ef64a4ef Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Fri, 23 Aug 2013 23:30:23 +0800 Subject: [PATCH V3] xl: HVM domain S3 bugfix Currently Xen hvm s3 has a bug coming from the difference between qemu-traditioanl and qemu-xen. For qemu-traditional, the way to resume from hvm s3 is via ''xl trigger'' command.

From ba9abf6ee7e5fe0515e2d51b14743c8d5416285c Mon Sep 17 00:00:00 2001 From: Liu, Jinsong <jinsong.liu@intel.com> Date: Fri, 24 Feb 2012 02:18:02 +0800 Subject: [PATCH 2/2] Xen pad logic This patch implement Xen pad logic, and when getting pad device notification, it hypercalls to Xen hypervisor for core parking. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> ---

Hola: Posteo este asunto en la lista porque me consta que los "padres" del paquete pxR (por el que les estoy enormemente agradecido) son asiduos de ella y nos aclaran a muchos novatos como yo un montón de dudas de R. Si prefieren que tratemos este asunto de forma menos "publica" no tienen mas que decirlo. Bueno al turrón (nunca mejor dicho)!!! Estoy montando una serie de

X86 microcode: add S3 micorcode update When wakeup from S3, use per cpu microcode image to update cpu microcode. Signed-off-by: Liu, Jinsong <jinsong.liu@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

From 159251a04afcdcd8ca08e9f2bdfae279b2aa5471 Mon Sep 17 00:00:00 2001 From: Liu Jinsong <jinsong.liu@intel.com> Date: Thu, 31 Oct 2013 06:38:15 +0800 Subject: [PATCH 4/4] XSA-60 security hole: flush cache when vmentry back to UC guest This patch flush cache when vmentry back to UC guest, to prevent cache polluted by hypervisor access guest memory during UC mode. The elegant way to do this

x86 pm : provide CC7/PC2 residency Sandy bridge introduces new MSR to get cc7/pc2 residency (core C-state 7/package C-state 2). Print the cc7/pc2 residency when on sandy bridge platform. Signed-off-by: Yang Zhang <yang.z.zhang@intel.com> diff -r 662dbf6ee71c tools/libxc/xc_pm.c --- a/tools/libxc/xc_pm.c Mon Oct 24 18:01:07 2011 +0100 +++ b/tools/libxc/xc_pm.c Fri Oct 28

Sorry, forget to join lists. Regards, Jinsong -----Original Message----- From: Liu, Jinsong Sent: 2007年5月16日 8:23 To: ''Keir Fraser''; Tian, Kevin; xen-devel@lists.xensource.com Subject: RE: [Xen-devel] trap/interrupt gate for hypercall In native linux, syscall (gate type 15) and its RESTORE_ALL code provides weak fixup mechanism when reload segment register, by sending 0