similar to: [PATCH 9/9] [RFC] Add cpu idle pwr mgmt to xen

Local APIC timer may stop at deep C state (C3/C4...) entry/exit. Initial HPET broadcast working in legacy replacing mode, broke RTC intr, so was bypassed. This patch add the logic that use platform timer (PIT) to reenable local APIC timer at C state entry/exit. Currently, only keep PIT enabled with 100Hz freq. The next step is trying to dynamically enable/disable PIT while needed, and give it

Local APIC timer may stop at deep C state (C3/C4...) entry/exit. this patch add the logic that use platform timer (HPET) to reenable local APIC timer at C state entry/exit. Signed-off-by: Wei Gang <gang.wei@intel.com> Signed-off-by: Yu Ke <ke.yu@intel.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Add suspend/resume to devices owned by Xen. Signed-off-by Ke Yu <ke.yu@intel.com> Signed-off-by Kevin Tian <kevin.tian@intel.com> diff -r 3ef0510e44d0 xen/arch/x86/apic.c --- a/xen/arch/x86/apic.c Tue May 08 10:21:23 2007 +0100 +++ b/xen/arch/x86/apic.c Mon May 14 15:05:28 2007 -0400 @@ -579,6 +579,95 @@ void __devinit setup_local_APIC(void) apic_pm_activate(); } +static

Hi, Keir, Attached are the necessary changes in control panel to support ia64/vti domain builder. One is in common side, and the other is in vti specific image builder. Please take a look, and if no objection, I''d like to ask Dan''s help to check into xen-ia64-unstable.hg first. Signed-off-by Ke Yu <ke.yu@intel.com> Signed-off-by Anthony Xu <anthony.xu@intel.com>

HPET intr-near-missing means if the current counter value is too close to the comparator value to be reprogrammed the expected HPET intr may be missing. Linux kernel uses a mininal 48-hpet-ticks(~3.5us) distance to workaround this, but personal observation showed there is still failure case while delta=0xba (~13.5us). So choosing 20us as the MIN_DELTA_NS should be helpful to prevent near-missing

Initialize state_entry_time to zero for all idle vcpus NOW() is not usable since xen time sub-system hasn''t been initialized yet. On my box, it gives a initial stamp ~60s due to local tsc stamp as zero and TSC count is started from power on. Then a negative value is added to runstate of that idle vcpu at schedule point. The net effect is for some tool like xenpm to show a big idle time

On Thu, 30 Sep 2010 14:02:34 +0800, gang.wei@intel.com wrote: > I am the original developer of HPET broadcast code. > > First of all, to disable HPET broadcast, no additional patch is required. > Please simply add option "cpuidle=off" or "max_cstate=1" at xen cmdline in > /boot/grub/grub.conf. > > Second, I noticed that the issue just occur on

CPUIDLE: Avoid remnant LAPIC timer intr while force hpetbroadcast LAPIC will stop during C3, and resume to work after exit from C3. Considering below case: The LAPIC timer was programmed to expire after 1000us, but CPU enter C3 after 100us and exit C3 at 9xxus. 0us: reprogram_timer(1000us) 100us: entry C3, LAPIC timer stop 9xxus: exit C3 due to unexpected event, LAPIC timer continue running

One more fix about PMR disable. Move PMR disable into per-iommu enable function, instead of in current iommu_setup which only takes effect on first VT-d engine. This change also enlightens S3 resume path. Signed-off-by Gang Wei (Jimmy) <gang.wei@intel.com> Signed-off-by Kevin Tian <kevin.tian@intel.com> Thanks, Kevin _______________________________________________ Xen-devel

Isolate some of the non-VMI timer related changes in Linux. This patch moves the cyc_2_ns conversion code into a common location, eliminating redundant code in hpet and tsc timer implementations, and introduces some macros that may be redefined by the sub-architecture to avoid dependence on APIC routing, CMOS time sync, and testing for broken time hardware (which presumably, does not happen in a

Isolate some of the non-VMI timer related changes in Linux. This patch moves the cyc_2_ns conversion code into a common location, eliminating redundant code in hpet and tsc timer implementations, and introduces some macros that may be redefined by the sub-architecture to avoid dependence on APIC routing, CMOS time sync, and testing for broken time hardware (which presumably, does not happen in a

In order to share the common code in tsc.c which does CPU Khz calibration, we need to make an accurate value of CPU speed available to the tsc.c code. This value loses a lot of precision in a VM because of the timing differences with real hardware, but we need it to be as precise as possible so the guest can make accurate time calculations with the cycle counters. Signed-off-by: Zachary Amsden

In order to share the common code in tsc.c which does CPU Khz calibration, we need to make an accurate value of CPU speed available to the tsc.c code. This value loses a lot of precision in a VM because of the timing differences with real hardware, but we need it to be as precise as possible so the guest can make accurate time calculations with the cycle counters. Signed-off-by: Zachary Amsden

Add basic infrastructure for xen power management. Now only S3 (suspend to ram) is supported. Signed-off-by Ke Yu <ke.yu@intel.com> Signed-off-by Kevin Tian <kevin.tian@intel.com> diff -r 13e258a58044 xen/arch/x86/acpi/Makefile --- a/xen/arch/x86/acpi/Makefile Wed Feb 14 11:13:40 2007 +0800 +++ b/xen/arch/x86/acpi/Makefile Wed Feb 14 11:13:40 2007 +0800 @@ -1,1 +1,2 @@ obj-y +=

Hi, Dan, This patch fixes strange behavior on IA64, that IDLE is scheduled more than Dom0 with default sEDF scheduler. The key point is reprogram_ac_timer at the end of ac_timer dispatcher, which programs local apic timer with expire of next ac_timer on x86. Higher precision lapic timer can trigger ac_timer more precisely than simply done in PIT interrupt handler. That works perfectly on x86

>I''ve been seeing these pretty regularly on a single-socket dual-core Athlon >system for the last couple of months, and only on Friday finally found time >to start looking into these. Besides the messages above, I also see hangs >in about every other boot attempt but only if I do *not* use serial output >(which makes debugging a little harder), and never once initial boot

You might find this useful ... TSC and Power Management Events on AMD Processors - Nov 2, 2005 - Rich Brunner, AMD Fellow Current AMD Opteron(tm) and Athlon(tm)64 processors provide power management mechanisms that independently adjust the performance state ("P-state") and power state ("C-state") of the processor[1][2]; these state changes can affect a

vtdt: Define a new function gtsc_to_gtime() Define it to do the transform from guest tsc to guest time. Fix the typo in gtime_to_gtsc() definition. Signed-off-by: Wei Gang <gang.wei@intel.com> diff -r 373b7357d977 xen/arch/x86/time.c --- a/xen/arch/x86/time.c Thu Dec 09 22:32:43 2010 +0800 +++ b/xen/arch/x86/time.c Thu Dec 09 22:32:51 2010 +0800 @@ -1634,11 +1634,20 @@ static void __init

Basic infrastructure for Xen S3 support with a common CPU context save/restore logic for both 32bit and 64bit. Wakeup code is split into two parts: - the first locates after trampoline code, to share all the tricks on the latter, like relocation base and identy mapping - the 2nd part locates in xen code segment, to do the actual CPU context restore Signed-off-by Ke Yu

Hi all, I've got a weird issue, and I'm trying to confirm if it's a bug, and if so, if there is a workaround until it is fixed. The situation is this: If I virsh reboot <domain> --mode acpi, it will actually reboot the domain cleanly (watching from the console allows me to see the full shutdown messages, followed by a bootup). However, after this point, virsh domstate