similar to: [PATCH] SVM: handle page faults in emaulted instruction fetches

The guest handle checks should use paging_* predicates, not shadow_*. Also tidy up a few places where p2m definitions were being imported via asm/guest_access.h -> asm/shadow.h -> asm/p2m.h Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com> -- Tim Deegan <Tim.Deegan@citrix.com> Principal Software Engineer, Citrix Systems (R&D) Ltd. [Company #02300071, SL9 0DZ, UK.]

Shadow audit: paging-disabled shadows no longer need special treatment when translating the frame numbers found in the entries. multi.c | 31 +++++++++---------------------- 1 file changed, 9 insertions(+), 22 deletions(-) Signed-off-by: Tim Deegan <Tim.Deegan@citrix.com> -- Tim Deegan <Tim.Deegan@citrix.com> Principal Software Engineer, Citrix Systems (R&D) Ltd. [Company

Hi all! Did the nested xen stuff make it into the xen-unstable (4.1-rc1?) tree as suggested back in January by Tim Deegan? TIA ________________________________ Date: Fri, 7 Jan 2011 16:01:12 +0000 From: Tim Deegan <Tim.Deegan@citrix.com> Subject: Re: [Xen-devel] [PATCH 00/12] Nested Virtualization: Overview To: Christoph Egger <Christoph.Egger@amd.com> Cc: Keir Fraser

Hi all, Can Xen hypervisor modify HVM domU's Shadow page table, under the dom0's context, like trapped from dom0's hypercall? I think it have to call 2 functions at least: guest_walk_tables() and flush_tlb_all(). Can these 2 functions called in dom0's context? In my test, if hypervisor tries to modify HVM's shadow page table, it will bring down the whole system. I am not

Hi all, I''ve been reading through the code regarding paging --> spending a lot of time in mm/*.*, as well as some of the other parts up a level or two, but I''m still unclear as to some key things. Here''s what I think I know: I think I know how a domain''s shadow page table is first allocated E.G. the hash_table is xmalloc''ed and when it is

Intercepting this MSR is pointless - The swapgs instruction does not cause a vmexit, so the cached result of this is potentially stale after the next guest instruction. It is correctly saved and restored on vcpu context switch. Furthermore, 64bit Windows writes to this MSR on every thread context switch, so interception causes a substantial performance hit. From: Paul Durrant

Hi, all Page offline can be used by many purpose, like memory offline, memory power management, proactive action when multiple CE error happen to one page etc. In virtualization environment without guest offline support, we think offline a page usually means replace the old page with a new one transparently to guest. Currently we are trying to add page offline support in Xen environment .

Trying to migrate a 64bit PV guest with 64GB running medium to heavy load on xen 3.4.0, it is showing lot of soft lockups. The softlockups are causing dom0 reboot by the cluster FS. The hardware has 256GB and 32 CPUs. Looking into the hypervisor thru kdb, I see one cpu in sh_resync_all() while all other 31 appear spinning on the shadow_lock. I vaguely remember seeing some thread on this while

Signed-off-by: Christoph Egger <Christoph.Egger@amd.com> -- ---to satisfy European Law for business letters: Advanced Micro Devices GmbH Einsteinring 24, 85609 Dornach b. Muenchen Geschaeftsfuehrer: Alberto Bozzo, Andrew Bowd Sitz: Dornach, Gemeinde Aschheim, Landkreis Muenchen Registergericht Muenchen, HRB Nr. 43632 _______________________________________________ Xen-devel mailing list

Hi, I am really confused about NPT walks for guest page table , and eager to know the details about it. It is treated as data writes even if the access itself is a code read in AMD NPT.I just want to know : is it the same in EPT? Could anyone help me? I would like to know that very much Thank you in advance Bo Ma _______________________________________________ Xen-devel mailing list

flight 13925 xen-4.2-testing real [real] http://www.chiark.greenend.org.uk/~xensrcts/logs/13925/ Regressions :-( Tests which did not succeed and are blocking, including tests which could not be run: test-amd64-i386-qemuu-rhel6hvm-amd 9 guest-start.2 fail REGR. vs. 13922 Tests which did not succeed, but are not blocking: test-amd64-amd64-xl-sedf-pin 10 guest-saverestore fail

We''ve got reports of that change causing HVM data corruption issues. While I can''t see what''s wrong with the patch, I''d suggest at least reverting it from the 3.3 tree (which is what our code is based upon) for the time being. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com

Hi, Attached patch implements the VMCB cleanbits SVM feature. Upcoming AMD CPUs introduce them and they are basically hints for the CPU which vmcb values can be re-used from the previous VMRUN instruction. Each bit represents a certain set of fields in the VMCB. Setting a bit tells the cpu it can re-use the cached value from the previous VMRUN. Clearing a bit tells the cpu to reload the values

These two patches affect the interrupt injection logic for AMD-V (only). These patches fix issues with Windows HVM guests during boot menu screen: 1) the timer countdown is no longer very slow 2) kbd response is now no longer slow or non-existent We have also seen an occasional "dma lost interrupt"/expiry errors, and these patches seem to help with these, especially with SUSE10 HVM

Hi all, Can some one tell me where phys_to_machine_mapping is being initialized for a domU having paging mode set to PG_translate. I see that, populate_physmap() after calling __alloc_xen_heap_pages only updates the machine_to_physmap but how is the mfn for the allocated page being updated/set for phys_to_machine_mapping?? I see that phys_to_machine_mapping is a #defined to RO_MPT_VIRT_START

Hi, I looked at the function xc_translate_foreign_address(), and see that it walks the page table of the guest VM. So at best, it should return the pfn of the guest (?) We can see taht the Later part of the function is like this: ... if (pt_levels >= 3) mfn = (pte & L0_PAGETABLE_MASK_PAE) >> PAGE_SHIFT; else mfn = (pte & L0_PAGETABLE_MASK)

The self_nmi() code cause''s an NMI to be triggered by sending an APIC message to the local processor. However, NMIs are blocked by the VMEXIT, until the next iret or VMENTER. Volume 3 Chapter 27 Section 1 of the Intel SDM states: An NMI causes subsequent NMIs to be blocked, but only after the VM exit completes. As a result, as soon as the VMENTER happens, an immediate VMEXIT happens

Hi all, When i do ''xm dmesg'' the last statement says "*** Serial input -> DOM0 (type ''CTRL-a'' three times to switch input to Xen)" (i have no clue what''s that supposed to mean??) But when i press ctrl-a three times at the serial console, nothing happens. Iam using minicom to connect to the serial port of xen machine. Once xen

Is there any particular reason why on 32-bits the order is VMLOAD then HVM_SAVE_ALL_NOSEGREGS, while on 64-bits its is the other way around? Trying to put in the saving of EAX, I could save a GET_CURRENT() on 32-bits if I could order things the same way as on 64-bits. Also, both versions seem to have a redundant GET_CURRENT() right after the clgi/sti sequence - again, is there a particular reason